2 * Copyright 2008, Freescale Semiconductor, Inc
5 * Based vaguely on the Linux code
7 * SPDX-License-Identifier: GPL-2.0+
14 #include <dm/device-internal.h>
19 #include <linux/list.h>
21 #include "mmc_private.h"
23 static struct list_head mmc_devices;
24 static int cur_dev_num = -1;
26 __weak int board_mmc_getwp(struct mmc *mmc)
31 int mmc_getwp(struct mmc *mmc)
35 wp = board_mmc_getwp(mmc);
38 if (mmc->cfg->ops->getwp)
39 wp = mmc->cfg->ops->getwp(mmc);
47 __weak int board_mmc_getcd(struct mmc *mmc)
52 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
56 #ifdef CONFIG_MMC_TRACE
60 printf("CMD_SEND:%d\n", cmd->cmdidx);
61 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
62 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
63 switch (cmd->resp_type) {
65 printf("\t\tMMC_RSP_NONE\n");
68 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
72 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
76 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
78 printf("\t\t \t\t 0x%08X \n",
80 printf("\t\t \t\t 0x%08X \n",
82 printf("\t\t \t\t 0x%08X \n",
85 printf("\t\t\t\t\tDUMPING DATA\n");
86 for (i = 0; i < 4; i++) {
88 printf("\t\t\t\t\t%03d - ", i*4);
89 ptr = (u8 *)&cmd->response[i];
91 for (j = 0; j < 4; j++)
92 printf("%02X ", *ptr--);
97 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
101 printf("\t\tERROR MMC rsp not supported\n");
105 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
110 int mmc_send_status(struct mmc *mmc, int timeout)
113 int err, retries = 5;
114 #ifdef CONFIG_MMC_TRACE
118 cmd.cmdidx = MMC_CMD_SEND_STATUS;
119 cmd.resp_type = MMC_RSP_R1;
120 if (!mmc_host_is_spi(mmc))
121 cmd.cmdarg = mmc->rca << 16;
124 err = mmc_send_cmd(mmc, &cmd, NULL);
126 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
127 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
130 else if (cmd.response[0] & MMC_STATUS_MASK) {
131 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
132 printf("Status Error: 0x%08X\n",
137 } else if (--retries < 0)
146 #ifdef CONFIG_MMC_TRACE
147 status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9;
148 printf("CURR STATE:%d\n", status);
151 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
152 printf("Timeout waiting card ready\n");
156 if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR)
162 int mmc_set_blocklen(struct mmc *mmc, int len)
169 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
170 cmd.resp_type = MMC_RSP_R1;
173 return mmc_send_cmd(mmc, &cmd, NULL);
176 struct mmc *find_mmc_device(int dev_num)
179 struct list_head *entry;
181 list_for_each(entry, &mmc_devices) {
182 m = list_entry(entry, struct mmc, link);
184 if (m->block_dev.dev == dev_num)
188 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
189 printf("MMC Device %d not found\n", dev_num);
195 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
199 struct mmc_data data;
202 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
204 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
206 if (mmc->high_capacity)
209 cmd.cmdarg = start * mmc->read_bl_len;
211 cmd.resp_type = MMC_RSP_R1;
214 data.blocks = blkcnt;
215 data.blocksize = mmc->read_bl_len;
216 data.flags = MMC_DATA_READ;
218 if (mmc_send_cmd(mmc, &cmd, &data))
222 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
224 cmd.resp_type = MMC_RSP_R1b;
225 if (mmc_send_cmd(mmc, &cmd, NULL)) {
226 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
227 printf("mmc fail to send stop cmd\n");
236 static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst)
238 lbaint_t cur, blocks_todo = blkcnt;
243 struct mmc *mmc = find_mmc_device(dev_num);
247 if ((start + blkcnt) > mmc->block_dev.lba) {
248 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
249 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
250 start + blkcnt, mmc->block_dev.lba);
255 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
256 debug("%s: Failed to set blocklen\n", __func__);
261 cur = (blocks_todo > mmc->cfg->b_max) ?
262 mmc->cfg->b_max : blocks_todo;
263 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
264 debug("%s: Failed to read blocks\n", __func__);
269 dst += cur * mmc->read_bl_len;
270 } while (blocks_todo > 0);
275 static int mmc_go_idle(struct mmc *mmc)
282 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
284 cmd.resp_type = MMC_RSP_NONE;
286 err = mmc_send_cmd(mmc, &cmd, NULL);
296 static int sd_send_op_cond(struct mmc *mmc)
303 cmd.cmdidx = MMC_CMD_APP_CMD;
304 cmd.resp_type = MMC_RSP_R1;
307 err = mmc_send_cmd(mmc, &cmd, NULL);
312 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
313 cmd.resp_type = MMC_RSP_R3;
316 * Most cards do not answer if some reserved bits
317 * in the ocr are set. However, Some controller
318 * can set bit 7 (reserved for low voltages), but
319 * how to manage low voltages SD card is not yet
322 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
323 (mmc->cfg->voltages & 0xff8000);
325 if (mmc->version == SD_VERSION_2)
326 cmd.cmdarg |= OCR_HCS;
328 err = mmc_send_cmd(mmc, &cmd, NULL);
333 if (cmd.response[0] & OCR_BUSY)
342 if (mmc->version != SD_VERSION_2)
343 mmc->version = SD_VERSION_1_0;
345 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
346 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
347 cmd.resp_type = MMC_RSP_R3;
350 err = mmc_send_cmd(mmc, &cmd, NULL);
356 mmc->ocr = cmd.response[0];
358 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
364 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
369 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
370 cmd.resp_type = MMC_RSP_R3;
372 if (use_arg && !mmc_host_is_spi(mmc))
373 cmd.cmdarg = OCR_HCS |
374 (mmc->cfg->voltages &
375 (mmc->ocr & OCR_VOLTAGE_MASK)) |
376 (mmc->ocr & OCR_ACCESS_MODE);
378 err = mmc_send_cmd(mmc, &cmd, NULL);
381 mmc->ocr = cmd.response[0];
385 static int mmc_send_op_cond(struct mmc *mmc)
389 /* Some cards seem to need this */
392 /* Asking to the card its capabilities */
393 for (i = 0; i < 2; i++) {
394 err = mmc_send_op_cond_iter(mmc, i != 0);
398 /* exit if not busy (flag seems to be inverted) */
399 if (mmc->ocr & OCR_BUSY)
402 mmc->op_cond_pending = 1;
406 static int mmc_complete_op_cond(struct mmc *mmc)
413 mmc->op_cond_pending = 0;
414 if (!(mmc->ocr & OCR_BUSY)) {
415 start = get_timer(0);
417 err = mmc_send_op_cond_iter(mmc, 1);
420 if (mmc->ocr & OCR_BUSY)
422 if (get_timer(start) > timeout)
428 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
429 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
430 cmd.resp_type = MMC_RSP_R3;
433 err = mmc_send_cmd(mmc, &cmd, NULL);
438 mmc->ocr = cmd.response[0];
441 mmc->version = MMC_VERSION_UNKNOWN;
443 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
450 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
453 struct mmc_data data;
456 /* Get the Card Status Register */
457 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
458 cmd.resp_type = MMC_RSP_R1;
461 data.dest = (char *)ext_csd;
463 data.blocksize = MMC_MAX_BLOCK_LEN;
464 data.flags = MMC_DATA_READ;
466 err = mmc_send_cmd(mmc, &cmd, &data);
472 static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
478 cmd.cmdidx = MMC_CMD_SWITCH;
479 cmd.resp_type = MMC_RSP_R1b;
480 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
484 ret = mmc_send_cmd(mmc, &cmd, NULL);
486 /* Waiting for the ready status */
488 ret = mmc_send_status(mmc, timeout);
494 static int mmc_change_freq(struct mmc *mmc)
496 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
502 if (mmc_host_is_spi(mmc))
505 /* Only version 4 supports high-speed */
506 if (mmc->version < MMC_VERSION_4)
509 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
511 err = mmc_send_ext_csd(mmc, ext_csd);
516 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
518 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
521 return err == SWITCH_ERR ? 0 : err;
523 /* Now check to see that it worked */
524 err = mmc_send_ext_csd(mmc, ext_csd);
529 /* No high-speed support */
530 if (!ext_csd[EXT_CSD_HS_TIMING])
533 /* High Speed is set, there are two types: 52MHz and 26MHz */
534 if (cardtype & EXT_CSD_CARD_TYPE_52) {
535 if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
536 mmc->card_caps |= MMC_MODE_DDR_52MHz;
537 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
539 mmc->card_caps |= MMC_MODE_HS;
545 static int mmc_set_capacity(struct mmc *mmc, int part_num)
549 mmc->capacity = mmc->capacity_user;
553 mmc->capacity = mmc->capacity_boot;
556 mmc->capacity = mmc->capacity_rpmb;
562 mmc->capacity = mmc->capacity_gp[part_num - 4];
568 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
573 int mmc_select_hwpart(int dev_num, int hwpart)
575 struct mmc *mmc = find_mmc_device(dev_num);
581 if (mmc->part_num == hwpart)
584 if (mmc->part_config == MMCPART_NOAVAILABLE) {
585 printf("Card doesn't support part_switch\n");
589 ret = mmc_switch_part(dev_num, hwpart);
593 mmc->part_num = hwpart;
599 int mmc_switch_part(int dev_num, unsigned int part_num)
601 struct mmc *mmc = find_mmc_device(dev_num);
607 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
608 (mmc->part_config & ~PART_ACCESS_MASK)
609 | (part_num & PART_ACCESS_MASK));
612 * Set the capacity if the switch succeeded or was intended
613 * to return to representing the raw device.
615 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0)))
616 ret = mmc_set_capacity(mmc, part_num);
621 int mmc_hwpart_config(struct mmc *mmc,
622 const struct mmc_hwpart_conf *conf,
623 enum mmc_hwpart_conf_mode mode)
629 u32 max_enh_size_mult;
630 u32 tot_enh_size_mult = 0;
633 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
635 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
638 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
639 printf("eMMC >= 4.4 required for enhanced user data area\n");
643 if (!(mmc->part_support & PART_SUPPORT)) {
644 printf("Card does not support partitioning\n");
648 if (!mmc->hc_wp_grp_size) {
649 printf("Card does not define HC WP group size\n");
653 /* check partition alignment and total enhanced size */
654 if (conf->user.enh_size) {
655 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
656 conf->user.enh_start % mmc->hc_wp_grp_size) {
657 printf("User data enhanced area not HC WP group "
661 part_attrs |= EXT_CSD_ENH_USR;
662 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
663 if (mmc->high_capacity) {
664 enh_start_addr = conf->user.enh_start;
666 enh_start_addr = (conf->user.enh_start << 9);
672 tot_enh_size_mult += enh_size_mult;
674 for (pidx = 0; pidx < 4; pidx++) {
675 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
676 printf("GP%i partition not HC WP group size "
677 "aligned\n", pidx+1);
680 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
681 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
682 part_attrs |= EXT_CSD_ENH_GP(pidx);
683 tot_enh_size_mult += gp_size_mult[pidx];
687 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
688 printf("Card does not support enhanced attribute\n");
692 err = mmc_send_ext_csd(mmc, ext_csd);
697 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
698 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
699 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
700 if (tot_enh_size_mult > max_enh_size_mult) {
701 printf("Total enhanced size exceeds maximum (%u > %u)\n",
702 tot_enh_size_mult, max_enh_size_mult);
706 /* The default value of EXT_CSD_WR_REL_SET is device
707 * dependent, the values can only be changed if the
708 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
709 * changed only once and before partitioning is completed. */
710 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
711 if (conf->user.wr_rel_change) {
712 if (conf->user.wr_rel_set)
713 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
715 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
717 for (pidx = 0; pidx < 4; pidx++) {
718 if (conf->gp_part[pidx].wr_rel_change) {
719 if (conf->gp_part[pidx].wr_rel_set)
720 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
722 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
726 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
727 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
728 puts("Card does not support host controlled partition write "
729 "reliability settings\n");
733 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
734 EXT_CSD_PARTITION_SETTING_COMPLETED) {
735 printf("Card already partitioned\n");
739 if (mode == MMC_HWPART_CONF_CHECK)
742 /* Partitioning requires high-capacity size definitions */
743 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
744 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
745 EXT_CSD_ERASE_GROUP_DEF, 1);
750 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
752 /* update erase group size to be high-capacity */
753 mmc->erase_grp_size =
754 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
758 /* all OK, write the configuration */
759 for (i = 0; i < 4; i++) {
760 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
761 EXT_CSD_ENH_START_ADDR+i,
762 (enh_start_addr >> (i*8)) & 0xFF);
766 for (i = 0; i < 3; i++) {
767 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
768 EXT_CSD_ENH_SIZE_MULT+i,
769 (enh_size_mult >> (i*8)) & 0xFF);
773 for (pidx = 0; pidx < 4; pidx++) {
774 for (i = 0; i < 3; i++) {
775 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
776 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
777 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
782 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
783 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
787 if (mode == MMC_HWPART_CONF_SET)
790 /* The WR_REL_SET is a write-once register but shall be
791 * written before setting PART_SETTING_COMPLETED. As it is
792 * write-once we can only write it when completing the
794 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
795 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
796 EXT_CSD_WR_REL_SET, wr_rel_set);
801 /* Setting PART_SETTING_COMPLETED confirms the partition
802 * configuration but it only becomes effective after power
803 * cycle, so we do not adjust the partition related settings
804 * in the mmc struct. */
806 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
807 EXT_CSD_PARTITION_SETTING,
808 EXT_CSD_PARTITION_SETTING_COMPLETED);
815 int mmc_getcd(struct mmc *mmc)
819 cd = board_mmc_getcd(mmc);
822 if (mmc->cfg->ops->getcd)
823 cd = mmc->cfg->ops->getcd(mmc);
831 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
834 struct mmc_data data;
836 /* Switch the frequency */
837 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
838 cmd.resp_type = MMC_RSP_R1;
839 cmd.cmdarg = (mode << 31) | 0xffffff;
840 cmd.cmdarg &= ~(0xf << (group * 4));
841 cmd.cmdarg |= value << (group * 4);
843 data.dest = (char *)resp;
846 data.flags = MMC_DATA_READ;
848 return mmc_send_cmd(mmc, &cmd, &data);
852 static int sd_change_freq(struct mmc *mmc)
856 ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2);
857 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
858 struct mmc_data data;
863 if (mmc_host_is_spi(mmc))
866 /* Read the SCR to find out if this card supports higher speeds */
867 cmd.cmdidx = MMC_CMD_APP_CMD;
868 cmd.resp_type = MMC_RSP_R1;
869 cmd.cmdarg = mmc->rca << 16;
871 err = mmc_send_cmd(mmc, &cmd, NULL);
876 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
877 cmd.resp_type = MMC_RSP_R1;
883 data.dest = (char *)scr;
886 data.flags = MMC_DATA_READ;
888 err = mmc_send_cmd(mmc, &cmd, &data);
897 mmc->scr[0] = __be32_to_cpu(scr[0]);
898 mmc->scr[1] = __be32_to_cpu(scr[1]);
900 switch ((mmc->scr[0] >> 24) & 0xf) {
902 mmc->version = SD_VERSION_1_0;
905 mmc->version = SD_VERSION_1_10;
908 mmc->version = SD_VERSION_2;
909 if ((mmc->scr[0] >> 15) & 0x1)
910 mmc->version = SD_VERSION_3;
913 mmc->version = SD_VERSION_1_0;
917 if (mmc->scr[0] & SD_DATA_4BIT)
918 mmc->card_caps |= MMC_MODE_4BIT;
920 /* Version 1.0 doesn't support switching */
921 if (mmc->version == SD_VERSION_1_0)
926 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
927 (u8 *)switch_status);
932 /* The high-speed function is busy. Try again */
933 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
937 /* If high-speed isn't supported, we return */
938 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
942 * If the host doesn't support SD_HIGHSPEED, do not switch card to
943 * HIGHSPEED mode even if the card support SD_HIGHSPPED.
944 * This can avoid furthur problem when the card runs in different
945 * mode between the host.
947 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) &&
948 (mmc->cfg->host_caps & MMC_MODE_HS)))
951 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
956 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000)
957 mmc->card_caps |= MMC_MODE_HS;
962 /* frequency bases */
963 /* divided by 10 to be nice to platforms without floating point */
964 static const int fbase[] = {
971 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
972 * to platforms without floating point.
974 static const int multipliers[] = {
993 static void mmc_set_ios(struct mmc *mmc)
995 if (mmc->cfg->ops->set_ios)
996 mmc->cfg->ops->set_ios(mmc);
999 void mmc_set_clock(struct mmc *mmc, uint clock)
1001 if (clock > mmc->cfg->f_max)
1002 clock = mmc->cfg->f_max;
1004 if (clock < mmc->cfg->f_min)
1005 clock = mmc->cfg->f_min;
1012 static void mmc_set_bus_width(struct mmc *mmc, uint width)
1014 mmc->bus_width = width;
1019 static int mmc_startup(struct mmc *mmc)
1023 u64 cmult, csize, capacity;
1025 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1026 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1028 bool has_parts = false;
1029 bool part_completed;
1031 #ifdef CONFIG_MMC_SPI_CRC_ON
1032 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
1033 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
1034 cmd.resp_type = MMC_RSP_R1;
1036 err = mmc_send_cmd(mmc, &cmd, NULL);
1043 /* Put the Card in Identify Mode */
1044 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
1045 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
1046 cmd.resp_type = MMC_RSP_R2;
1049 err = mmc_send_cmd(mmc, &cmd, NULL);
1054 memcpy(mmc->cid, cmd.response, 16);
1057 * For MMC cards, set the Relative Address.
1058 * For SD cards, get the Relatvie Address.
1059 * This also puts the cards into Standby State
1061 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1062 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
1063 cmd.cmdarg = mmc->rca << 16;
1064 cmd.resp_type = MMC_RSP_R6;
1066 err = mmc_send_cmd(mmc, &cmd, NULL);
1072 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
1075 /* Get the Card-Specific Data */
1076 cmd.cmdidx = MMC_CMD_SEND_CSD;
1077 cmd.resp_type = MMC_RSP_R2;
1078 cmd.cmdarg = mmc->rca << 16;
1080 err = mmc_send_cmd(mmc, &cmd, NULL);
1082 /* Waiting for the ready status */
1083 mmc_send_status(mmc, timeout);
1088 mmc->csd[0] = cmd.response[0];
1089 mmc->csd[1] = cmd.response[1];
1090 mmc->csd[2] = cmd.response[2];
1091 mmc->csd[3] = cmd.response[3];
1093 if (mmc->version == MMC_VERSION_UNKNOWN) {
1094 int version = (cmd.response[0] >> 26) & 0xf;
1098 mmc->version = MMC_VERSION_1_2;
1101 mmc->version = MMC_VERSION_1_4;
1104 mmc->version = MMC_VERSION_2_2;
1107 mmc->version = MMC_VERSION_3;
1110 mmc->version = MMC_VERSION_4;
1113 mmc->version = MMC_VERSION_1_2;
1118 /* divide frequency by 10, since the mults are 10x bigger */
1119 freq = fbase[(cmd.response[0] & 0x7)];
1120 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
1122 mmc->tran_speed = freq * mult;
1124 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
1125 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
1128 mmc->write_bl_len = mmc->read_bl_len;
1130 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
1132 if (mmc->high_capacity) {
1133 csize = (mmc->csd[1] & 0x3f) << 16
1134 | (mmc->csd[2] & 0xffff0000) >> 16;
1137 csize = (mmc->csd[1] & 0x3ff) << 2
1138 | (mmc->csd[2] & 0xc0000000) >> 30;
1139 cmult = (mmc->csd[2] & 0x00038000) >> 15;
1142 mmc->capacity_user = (csize + 1) << (cmult + 2);
1143 mmc->capacity_user *= mmc->read_bl_len;
1144 mmc->capacity_boot = 0;
1145 mmc->capacity_rpmb = 0;
1146 for (i = 0; i < 4; i++)
1147 mmc->capacity_gp[i] = 0;
1149 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
1150 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1152 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
1153 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1155 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
1156 cmd.cmdidx = MMC_CMD_SET_DSR;
1157 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
1158 cmd.resp_type = MMC_RSP_NONE;
1159 if (mmc_send_cmd(mmc, &cmd, NULL))
1160 printf("MMC: SET_DSR failed\n");
1163 /* Select the card, and put it into Transfer Mode */
1164 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1165 cmd.cmdidx = MMC_CMD_SELECT_CARD;
1166 cmd.resp_type = MMC_RSP_R1;
1167 cmd.cmdarg = mmc->rca << 16;
1168 err = mmc_send_cmd(mmc, &cmd, NULL);
1175 * For SD, its erase group is always one sector
1177 mmc->erase_grp_size = 1;
1178 mmc->part_config = MMCPART_NOAVAILABLE;
1179 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
1180 /* check ext_csd version and capacity */
1181 err = mmc_send_ext_csd(mmc, ext_csd);
1184 if (ext_csd[EXT_CSD_REV] >= 2) {
1186 * According to the JEDEC Standard, the value of
1187 * ext_csd's capacity is valid if the value is more
1190 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
1191 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
1192 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
1193 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
1194 capacity *= MMC_MAX_BLOCK_LEN;
1195 if ((capacity >> 20) > 2 * 1024)
1196 mmc->capacity_user = capacity;
1199 switch (ext_csd[EXT_CSD_REV]) {
1201 mmc->version = MMC_VERSION_4_1;
1204 mmc->version = MMC_VERSION_4_2;
1207 mmc->version = MMC_VERSION_4_3;
1210 mmc->version = MMC_VERSION_4_41;
1213 mmc->version = MMC_VERSION_4_5;
1216 mmc->version = MMC_VERSION_5_0;
1220 /* The partition data may be non-zero but it is only
1221 * effective if PARTITION_SETTING_COMPLETED is set in
1222 * EXT_CSD, so ignore any data if this bit is not set,
1223 * except for enabling the high-capacity group size
1224 * definition (see below). */
1225 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
1226 EXT_CSD_PARTITION_SETTING_COMPLETED);
1228 /* store the partition info of emmc */
1229 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
1230 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1231 ext_csd[EXT_CSD_BOOT_MULT])
1232 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
1233 if (part_completed &&
1234 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
1235 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
1237 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1239 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1241 for (i = 0; i < 4; i++) {
1242 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
1243 uint mult = (ext_csd[idx + 2] << 16) +
1244 (ext_csd[idx + 1] << 8) + ext_csd[idx];
1247 if (!part_completed)
1249 mmc->capacity_gp[i] = mult;
1250 mmc->capacity_gp[i] *=
1251 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1252 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1253 mmc->capacity_gp[i] <<= 19;
1256 if (part_completed) {
1257 mmc->enh_user_size =
1258 (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) +
1259 (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) +
1260 ext_csd[EXT_CSD_ENH_SIZE_MULT];
1261 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1262 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1263 mmc->enh_user_size <<= 19;
1264 mmc->enh_user_start =
1265 (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) +
1266 (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) +
1267 (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) +
1268 ext_csd[EXT_CSD_ENH_START_ADDR];
1269 if (mmc->high_capacity)
1270 mmc->enh_user_start <<= 9;
1274 * Host needs to enable ERASE_GRP_DEF bit if device is
1275 * partitioned. This bit will be lost every time after a reset
1276 * or power off. This will affect erase size.
1280 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
1281 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
1284 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1285 EXT_CSD_ERASE_GROUP_DEF, 1);
1290 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1293 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
1294 /* Read out group size from ext_csd */
1295 mmc->erase_grp_size =
1296 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1298 * if high capacity and partition setting completed
1299 * SEC_COUNT is valid even if it is smaller than 2 GiB
1300 * JEDEC Standard JESD84-B45, 6.2.4
1302 if (mmc->high_capacity && part_completed) {
1303 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
1304 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
1305 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
1306 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
1307 capacity *= MMC_MAX_BLOCK_LEN;
1308 mmc->capacity_user = capacity;
1311 /* Calculate the group size from the csd value. */
1312 int erase_gsz, erase_gmul;
1313 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
1314 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
1315 mmc->erase_grp_size = (erase_gsz + 1)
1319 mmc->hc_wp_grp_size = 1024
1320 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1321 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1323 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1326 err = mmc_set_capacity(mmc, mmc->part_num);
1331 err = sd_change_freq(mmc);
1333 err = mmc_change_freq(mmc);
1338 /* Restrict card's capabilities by what the host can do */
1339 mmc->card_caps &= mmc->cfg->host_caps;
1342 if (mmc->card_caps & MMC_MODE_4BIT) {
1343 cmd.cmdidx = MMC_CMD_APP_CMD;
1344 cmd.resp_type = MMC_RSP_R1;
1345 cmd.cmdarg = mmc->rca << 16;
1347 err = mmc_send_cmd(mmc, &cmd, NULL);
1351 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1352 cmd.resp_type = MMC_RSP_R1;
1354 err = mmc_send_cmd(mmc, &cmd, NULL);
1358 mmc_set_bus_width(mmc, 4);
1361 if (mmc->card_caps & MMC_MODE_HS)
1362 mmc->tran_speed = 50000000;
1364 mmc->tran_speed = 25000000;
1365 } else if (mmc->version >= MMC_VERSION_4) {
1366 /* Only version 4 of MMC supports wider bus widths */
1369 /* An array of possible bus widths in order of preference */
1370 static unsigned ext_csd_bits[] = {
1371 EXT_CSD_DDR_BUS_WIDTH_8,
1372 EXT_CSD_DDR_BUS_WIDTH_4,
1373 EXT_CSD_BUS_WIDTH_8,
1374 EXT_CSD_BUS_WIDTH_4,
1375 EXT_CSD_BUS_WIDTH_1,
1378 /* An array to map CSD bus widths to host cap bits */
1379 static unsigned ext_to_hostcaps[] = {
1380 [EXT_CSD_DDR_BUS_WIDTH_4] =
1381 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
1382 [EXT_CSD_DDR_BUS_WIDTH_8] =
1383 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
1384 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
1385 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
1388 /* An array to map chosen bus width to an integer */
1389 static unsigned widths[] = {
1393 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
1394 unsigned int extw = ext_csd_bits[idx];
1395 unsigned int caps = ext_to_hostcaps[extw];
1398 * If the bus width is still not changed,
1399 * don't try to set the default again.
1400 * Otherwise, recover from switch attempts
1401 * by switching to 1-bit bus width.
1403 if (extw == EXT_CSD_BUS_WIDTH_1 &&
1404 mmc->bus_width == 1) {
1410 * Check to make sure the card and controller support
1411 * these capabilities
1413 if ((mmc->card_caps & caps) != caps)
1416 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1417 EXT_CSD_BUS_WIDTH, extw);
1422 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
1423 mmc_set_bus_width(mmc, widths[idx]);
1425 err = mmc_send_ext_csd(mmc, test_csd);
1430 /* Only compare read only fields */
1431 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1432 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1433 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1434 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1435 ext_csd[EXT_CSD_REV]
1436 == test_csd[EXT_CSD_REV] &&
1437 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1438 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1439 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1440 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1449 if (mmc->card_caps & MMC_MODE_HS) {
1450 if (mmc->card_caps & MMC_MODE_HS_52MHz)
1451 mmc->tran_speed = 52000000;
1453 mmc->tran_speed = 26000000;
1457 mmc_set_clock(mmc, mmc->tran_speed);
1459 /* Fix the block length for DDR mode */
1460 if (mmc->ddr_mode) {
1461 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1462 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1465 /* fill in device description */
1466 mmc->block_dev.lun = 0;
1467 mmc->block_dev.type = 0;
1468 mmc->block_dev.blksz = mmc->read_bl_len;
1469 mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz);
1470 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
1471 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1472 sprintf(mmc->block_dev.vendor, "Man %06x Snr %04x%04x",
1473 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
1474 (mmc->cid[3] >> 16) & 0xffff);
1475 sprintf(mmc->block_dev.product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
1476 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
1477 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
1478 (mmc->cid[2] >> 24) & 0xff);
1479 sprintf(mmc->block_dev.revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
1480 (mmc->cid[2] >> 16) & 0xf);
1482 mmc->block_dev.vendor[0] = 0;
1483 mmc->block_dev.product[0] = 0;
1484 mmc->block_dev.revision[0] = 0;
1486 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
1487 init_part(&mmc->block_dev);
1493 static int mmc_send_if_cond(struct mmc *mmc)
1498 cmd.cmdidx = SD_CMD_SEND_IF_COND;
1499 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
1500 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
1501 cmd.resp_type = MMC_RSP_R7;
1503 err = mmc_send_cmd(mmc, &cmd, NULL);
1508 if ((cmd.response[0] & 0xff) != 0xaa)
1509 return UNUSABLE_ERR;
1511 mmc->version = SD_VERSION_2;
1516 /* not used any more */
1517 int __deprecated mmc_register(struct mmc *mmc)
1519 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1520 printf("%s is deprecated! use mmc_create() instead.\n", __func__);
1525 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv)
1529 /* quick validation */
1530 if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL ||
1531 cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0)
1534 mmc = calloc(1, sizeof(*mmc));
1541 /* the following chunk was mmc_register() */
1543 /* Setup dsr related values */
1545 mmc->dsr = 0xffffffff;
1546 /* Setup the universal parts of the block interface just once */
1547 mmc->block_dev.if_type = IF_TYPE_MMC;
1548 mmc->block_dev.dev = cur_dev_num++;
1549 mmc->block_dev.removable = 1;
1550 mmc->block_dev.block_read = mmc_bread;
1551 mmc->block_dev.block_write = mmc_bwrite;
1552 mmc->block_dev.block_erase = mmc_berase;
1554 /* setup initial part type */
1555 mmc->block_dev.part_type = mmc->cfg->part_type;
1557 INIT_LIST_HEAD(&mmc->link);
1559 list_add_tail(&mmc->link, &mmc_devices);
1564 void mmc_destroy(struct mmc *mmc)
1566 /* only freeing memory for now */
1570 #ifdef CONFIG_PARTITIONS
1571 block_dev_desc_t *mmc_get_dev(int dev)
1573 struct mmc *mmc = find_mmc_device(dev);
1574 if (!mmc || mmc_init(mmc))
1577 return &mmc->block_dev;
1581 /* board-specific MMC power initializations. */
1582 __weak void board_mmc_power_init(void)
1586 int mmc_start_init(struct mmc *mmc)
1590 /* we pretend there's no card when init is NULL */
1591 if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) {
1593 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1594 printf("MMC: no card present\n");
1602 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1603 mmc_adapter_card_type_ident();
1605 board_mmc_power_init();
1607 /* made sure it's not NULL earlier */
1608 err = mmc->cfg->ops->init(mmc);
1614 mmc_set_bus_width(mmc, 1);
1615 mmc_set_clock(mmc, 1);
1617 /* Reset the Card */
1618 err = mmc_go_idle(mmc);
1623 /* The internal partition reset to user partition(0) at every CMD0*/
1626 /* Test for SD version 2 */
1627 err = mmc_send_if_cond(mmc);
1629 /* Now try to get the SD card's operating condition */
1630 err = sd_send_op_cond(mmc);
1632 /* If the command timed out, we check for an MMC card */
1633 if (err == TIMEOUT) {
1634 err = mmc_send_op_cond(mmc);
1637 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1638 printf("Card did not respond to voltage select!\n");
1640 return UNUSABLE_ERR;
1645 mmc->init_in_progress = 1;
1650 static int mmc_complete_init(struct mmc *mmc)
1654 mmc->init_in_progress = 0;
1655 if (mmc->op_cond_pending)
1656 err = mmc_complete_op_cond(mmc);
1659 err = mmc_startup(mmc);
1667 int mmc_init(struct mmc *mmc)
1675 start = get_timer(0);
1677 if (!mmc->init_in_progress)
1678 err = mmc_start_init(mmc);
1681 err = mmc_complete_init(mmc);
1682 debug("%s: %d, time %lu\n", __func__, err, get_timer(start));
1686 int mmc_set_dsr(struct mmc *mmc, u16 val)
1692 /* CPU-specific MMC initializations */
1693 __weak int cpu_mmc_init(bd_t *bis)
1698 /* board-specific MMC initializations. */
1699 __weak int board_mmc_init(bd_t *bis)
1704 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1706 void print_mmc_devices(char separator)
1709 struct list_head *entry;
1712 list_for_each(entry, &mmc_devices) {
1713 m = list_entry(entry, struct mmc, link);
1716 mmc_type = IS_SD(m) ? "SD" : "eMMC";
1720 printf("%s: %d", m->cfg->name, m->block_dev.dev);
1722 printf(" (%s)", mmc_type);
1724 if (entry->next != &mmc_devices) {
1725 printf("%c", separator);
1726 if (separator != '\n')
1735 void print_mmc_devices(char separator) { }
1738 int get_mmc_num(void)
1743 void mmc_set_preinit(struct mmc *mmc, int preinit)
1745 mmc->preinit = preinit;
1748 static void do_preinit(void)
1751 struct list_head *entry;
1753 list_for_each(entry, &mmc_devices) {
1754 m = list_entry(entry, struct mmc, link);
1756 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1757 mmc_set_preinit(m, 1);
1764 #if defined(CONFIG_DM_MMC) && defined(CONFIG_SPL_BUILD)
1765 static int mmc_probe(bd_t *bis)
1769 #elif defined(CONFIG_DM_MMC)
1770 static int mmc_probe(bd_t *bis)
1776 ret = uclass_get(UCLASS_MMC, &uc);
1780 uclass_foreach_dev(m, uc) {
1781 ret = device_probe(m);
1783 printf("%s - probe failed: %d\n", m->name, ret);
1789 static int mmc_probe(bd_t *bis)
1791 if (board_mmc_init(bis) < 0)
1798 int mmc_initialize(bd_t *bis)
1800 static int initialized = 0;
1802 if (initialized) /* Avoid initializing mmc multiple times */
1806 INIT_LIST_HEAD (&mmc_devices);
1809 ret = mmc_probe(bis);
1813 #ifndef CONFIG_SPL_BUILD
1814 print_mmc_devices(',');
1821 #ifdef CONFIG_SUPPORT_EMMC_BOOT
1823 * This function changes the size of boot partition and the size of rpmb
1824 * partition present on EMMC devices.
1827 * struct *mmc: pointer for the mmc device strcuture
1828 * bootsize: size of boot partition
1829 * rpmbsize: size of rpmb partition
1831 * Returns 0 on success.
1834 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
1835 unsigned long rpmbsize)
1840 /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */
1841 cmd.cmdidx = MMC_CMD_RES_MAN;
1842 cmd.resp_type = MMC_RSP_R1b;
1843 cmd.cmdarg = MMC_CMD62_ARG1;
1845 err = mmc_send_cmd(mmc, &cmd, NULL);
1847 debug("mmc_boot_partition_size_change: Error1 = %d\n", err);
1851 /* Boot partition changing mode */
1852 cmd.cmdidx = MMC_CMD_RES_MAN;
1853 cmd.resp_type = MMC_RSP_R1b;
1854 cmd.cmdarg = MMC_CMD62_ARG2;
1856 err = mmc_send_cmd(mmc, &cmd, NULL);
1858 debug("mmc_boot_partition_size_change: Error2 = %d\n", err);
1861 /* boot partition size is multiple of 128KB */
1862 bootsize = (bootsize * 1024) / 128;
1864 /* Arg: boot partition size */
1865 cmd.cmdidx = MMC_CMD_RES_MAN;
1866 cmd.resp_type = MMC_RSP_R1b;
1867 cmd.cmdarg = bootsize;
1869 err = mmc_send_cmd(mmc, &cmd, NULL);
1871 debug("mmc_boot_partition_size_change: Error3 = %d\n", err);
1874 /* RPMB partition size is multiple of 128KB */
1875 rpmbsize = (rpmbsize * 1024) / 128;
1876 /* Arg: RPMB partition size */
1877 cmd.cmdidx = MMC_CMD_RES_MAN;
1878 cmd.resp_type = MMC_RSP_R1b;
1879 cmd.cmdarg = rpmbsize;
1881 err = mmc_send_cmd(mmc, &cmd, NULL);
1883 debug("mmc_boot_partition_size_change: Error4 = %d\n", err);
1890 * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH
1891 * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH
1894 * Returns 0 on success.
1896 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode)
1900 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH,
1901 EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) |
1902 EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) |
1903 EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width));
1911 * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG)
1912 * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and
1915 * Returns 0 on success.
1917 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access)
1921 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
1922 EXT_CSD_BOOT_ACK(ack) |
1923 EXT_CSD_BOOT_PART_NUM(part_num) |
1924 EXT_CSD_PARTITION_ACCESS(access));
1932 * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value
1933 * for enable. Note that this is a write-once field for non-zero values.
1935 * Returns 0 on success.
1937 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable)
1939 return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION,