2 * Marvell MMC/SD/SDIO driver
5 * Marvell Semiconductor <www.marvell.com>
6 * Written-by: Maen Suleiman, Gerald Kerma
8 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/cpu.h>
17 #include <asm/arch/soc.h>
18 #include <mvebu_mmc.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 #define DRIVER_NAME "MVEBU_MMC"
24 #define MVEBU_TARGET_DRAM 0
26 static void mvebu_mmc_write(u32 offs, u32 val)
28 writel(val, CONFIG_SYS_MMC_BASE + (offs));
31 static u32 mvebu_mmc_read(u32 offs)
33 return readl(CONFIG_SYS_MMC_BASE + (offs));
36 static int mvebu_mmc_setup_data(struct mmc_data *data)
40 debug("%s, data %s : blocks=%d blksz=%d\n", DRIVER_NAME,
41 (data->flags & MMC_DATA_READ) ? "read" : "write",
42 data->blocks, data->blocksize);
44 /* default to maximum timeout */
45 ctrl_reg = mvebu_mmc_read(SDIO_HOST_CTRL);
46 ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);
47 mvebu_mmc_write(SDIO_HOST_CTRL, ctrl_reg);
49 if (data->flags & MMC_DATA_READ) {
50 mvebu_mmc_write(SDIO_SYS_ADDR_LOW, (u32)data->dest & 0xffff);
51 mvebu_mmc_write(SDIO_SYS_ADDR_HI, (u32)data->dest >> 16);
53 mvebu_mmc_write(SDIO_SYS_ADDR_LOW, (u32)data->src & 0xffff);
54 mvebu_mmc_write(SDIO_SYS_ADDR_HI, (u32)data->src >> 16);
57 mvebu_mmc_write(SDIO_BLK_COUNT, data->blocks);
58 mvebu_mmc_write(SDIO_BLK_SIZE, data->blocksize);
63 static int mvebu_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
64 struct mmc_data *data)
72 debug("cmdidx [0x%x] resp_type[0x%x] cmdarg[0x%x]\n",
73 cmd->cmdidx, cmd->resp_type, cmd->cmdarg);
77 debug("%s: cmd %d (hw state 0x%04x)\n", DRIVER_NAME,
78 cmd->cmdidx, mvebu_mmc_read(SDIO_HW_STATE));
80 /* Checking if card is busy */
81 while ((mvebu_mmc_read(SDIO_HW_STATE) & CARD_BUSY)) {
83 printf("%s: card busy!\n", DRIVER_NAME);
90 /* Set up for a data transfer if we have one */
92 int err = mvebu_mmc_setup_data(data);
98 resptype = SDIO_CMD_INDEX(cmd->cmdidx);
100 /* Analyzing resptype/xfertype/waittype for the command */
101 if (cmd->resp_type & MMC_RSP_BUSY)
102 resptype |= SDIO_CMD_RSP_48BUSY;
103 else if (cmd->resp_type & MMC_RSP_136)
104 resptype |= SDIO_CMD_RSP_136;
105 else if (cmd->resp_type & MMC_RSP_PRESENT)
106 resptype |= SDIO_CMD_RSP_48;
108 resptype |= SDIO_CMD_RSP_NONE;
110 if (cmd->resp_type & MMC_RSP_CRC)
111 resptype |= SDIO_CMD_CHECK_CMDCRC;
113 if (cmd->resp_type & MMC_RSP_OPCODE)
114 resptype |= SDIO_CMD_INDX_CHECK;
116 if (cmd->resp_type & MMC_RSP_PRESENT) {
117 resptype |= SDIO_UNEXPECTED_RESP;
118 waittype |= SDIO_NOR_UNEXP_RSP;
122 resptype |= SDIO_CMD_DATA_PRESENT | SDIO_CMD_CHECK_DATACRC16;
123 xfertype |= SDIO_XFER_MODE_HW_WR_DATA_EN;
124 if (data->flags & MMC_DATA_READ) {
125 xfertype |= SDIO_XFER_MODE_TO_HOST;
126 waittype = SDIO_NOR_DMA_INI;
128 waittype |= SDIO_NOR_XFER_DONE;
131 waittype |= SDIO_NOR_CMD_DONE;
134 /* Setting cmd arguments */
135 mvebu_mmc_write(SDIO_ARG_LOW, cmd->cmdarg & 0xffff);
136 mvebu_mmc_write(SDIO_ARG_HI, cmd->cmdarg >> 16);
138 /* Setting Xfer mode */
139 mvebu_mmc_write(SDIO_XFER_MODE, xfertype);
141 mvebu_mmc_write(SDIO_NOR_INTR_STATUS, ~SDIO_NOR_CARD_INT);
142 mvebu_mmc_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
144 /* Sending command */
145 mvebu_mmc_write(SDIO_CMD, resptype);
147 mvebu_mmc_write(SDIO_NOR_INTR_EN, SDIO_POLL_MASK);
148 mvebu_mmc_write(SDIO_ERR_INTR_EN, SDIO_POLL_MASK);
150 /* Waiting for completion */
153 while (!((mvebu_mmc_read(SDIO_NOR_INTR_STATUS)) & waittype)) {
154 if (mvebu_mmc_read(SDIO_NOR_INTR_STATUS) & SDIO_NOR_ERROR) {
155 debug("%s: error! cmdidx : %d, err reg: %04x\n",
156 DRIVER_NAME, cmd->cmdidx,
157 mvebu_mmc_read(SDIO_ERR_INTR_STATUS));
158 if (mvebu_mmc_read(SDIO_ERR_INTR_STATUS) &
159 (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT))
167 printf("%s: command timed out\n", DRIVER_NAME);
171 if (mvebu_mmc_read(SDIO_ERR_INTR_STATUS) &
172 (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT))
175 /* Handling response */
176 if (cmd->resp_type & MMC_RSP_136) {
179 for (resp_indx = 0; resp_indx < 8; resp_indx++)
181 = mvebu_mmc_read(SDIO_RSP(resp_indx));
183 cmd->response[0] = ((response[0] & 0x03ff) << 22) |
184 ((response[1] & 0xffff) << 6) |
185 ((response[2] & 0xfc00) >> 10);
186 cmd->response[1] = ((response[2] & 0x03ff) << 22) |
187 ((response[3] & 0xffff) << 6) |
188 ((response[4] & 0xfc00) >> 10);
189 cmd->response[2] = ((response[4] & 0x03ff) << 22) |
190 ((response[5] & 0xffff) << 6) |
191 ((response[6] & 0xfc00) >> 10);
192 cmd->response[3] = ((response[6] & 0x03ff) << 22) |
193 ((response[7] & 0x3fff) << 8);
194 } else if (cmd->resp_type & MMC_RSP_PRESENT) {
197 for (resp_indx = 0; resp_indx < 3; resp_indx++)
199 = mvebu_mmc_read(SDIO_RSP(resp_indx));
201 cmd->response[0] = ((response[2] & 0x003f) << (8 - 8)) |
202 ((response[1] & 0xffff) << (14 - 8)) |
203 ((response[0] & 0x03ff) << (30 - 8));
204 cmd->response[1] = ((response[0] & 0xfc00) >> 10);
205 cmd->response[2] = 0;
206 cmd->response[3] = 0;
209 debug("%s: resp[0x%x] ", DRIVER_NAME, cmd->resp_type);
210 debug("[0x%x] ", cmd->response[0]);
211 debug("[0x%x] ", cmd->response[1]);
212 debug("[0x%x] ", cmd->response[2]);
213 debug("[0x%x] ", cmd->response[3]);
219 static void mvebu_mmc_power_up(void)
221 debug("%s: power up\n", DRIVER_NAME);
223 /* disable interrupts */
224 mvebu_mmc_write(SDIO_NOR_INTR_EN, 0);
225 mvebu_mmc_write(SDIO_ERR_INTR_EN, 0);
228 mvebu_mmc_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);
230 mvebu_mmc_write(SDIO_XFER_MODE, 0);
233 mvebu_mmc_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
234 mvebu_mmc_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
236 /* enable interrupts status */
237 mvebu_mmc_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);
238 mvebu_mmc_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
241 static void mvebu_mmc_set_clk(unsigned int clock)
246 debug("%s: clock off\n", DRIVER_NAME);
247 mvebu_mmc_write(SDIO_XFER_MODE, SDIO_XFER_MODE_STOP_CLK);
248 mvebu_mmc_write(SDIO_CLK_DIV, MVEBU_MMC_BASE_DIV_MAX);
250 m = MVEBU_MMC_BASE_FAST_CLOCK/(2*clock) - 1;
251 if (m > MVEBU_MMC_BASE_DIV_MAX)
252 m = MVEBU_MMC_BASE_DIV_MAX;
253 mvebu_mmc_write(SDIO_CLK_DIV, m & MVEBU_MMC_BASE_DIV_MAX);
259 static void mvebu_mmc_set_bus(unsigned int bus)
263 ctrl_reg = mvebu_mmc_read(SDIO_HOST_CTRL);
264 ctrl_reg &= ~SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;
268 ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;
272 ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_1_BIT;
275 /* default transfer mode */
276 ctrl_reg |= SDIO_HOST_CTRL_BIG_ENDIAN;
277 ctrl_reg &= ~SDIO_HOST_CTRL_LSB_FIRST;
279 /* default to maximum timeout */
280 ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);
281 ctrl_reg |= SDIO_HOST_CTRL_TMOUT_EN;
283 ctrl_reg |= SDIO_HOST_CTRL_PUSH_PULL_EN;
285 ctrl_reg |= SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY;
287 debug("%s: ctrl 0x%04x: %s %s %s\n", DRIVER_NAME, ctrl_reg,
288 (ctrl_reg & SDIO_HOST_CTRL_PUSH_PULL_EN) ?
289 "push-pull" : "open-drain",
290 (ctrl_reg & SDIO_HOST_CTRL_DATA_WIDTH_4_BITS) ?
291 "4bit-width" : "1bit-width",
292 (ctrl_reg & SDIO_HOST_CTRL_HI_SPEED_EN) ?
295 mvebu_mmc_write(SDIO_HOST_CTRL, ctrl_reg);
299 static void mvebu_mmc_set_ios(struct mmc *mmc)
301 debug("%s: bus[%d] clock[%d]\n", DRIVER_NAME,
302 mmc->bus_width, mmc->clock);
303 mvebu_mmc_set_bus(mmc->bus_width);
304 mvebu_mmc_set_clk(mmc->clock);
308 * Set window register.
310 static void mvebu_window_setup(void)
314 for (i = 0; i < 4; i++) {
315 mvebu_mmc_write(WINDOW_CTRL(i), 0);
316 mvebu_mmc_write(WINDOW_BASE(i), 0);
318 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
319 u32 size, base, attrib;
321 /* Enable DRAM bank */
324 attrib = KWCPU_ATTR_DRAM_CS0;
327 attrib = KWCPU_ATTR_DRAM_CS1;
330 attrib = KWCPU_ATTR_DRAM_CS2;
333 attrib = KWCPU_ATTR_DRAM_CS3;
336 /* invalide bank, disable access */
341 size = gd->bd->bi_dram[i].size;
342 base = gd->bd->bi_dram[i].start;
343 if (size && attrib) {
344 mvebu_mmc_write(WINDOW_CTRL(i),
345 MVCPU_WIN_CTRL_DATA(size,
350 mvebu_mmc_write(WINDOW_CTRL(i), MVCPU_WIN_DISABLE);
352 mvebu_mmc_write(WINDOW_BASE(i), base);
356 static int mvebu_mmc_initialize(struct mmc *mmc)
358 debug("%s: mvebu_mmc_initialize", DRIVER_NAME);
361 * Setting host parameters
362 * Initial Host Ctrl : Timeout : max , Normal Speed mode,
363 * 4-bit data mode, Big Endian, SD memory Card, Push_pull CMD Line
365 mvebu_mmc_write(SDIO_HOST_CTRL,
366 SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX) |
367 SDIO_HOST_CTRL_DATA_WIDTH_4_BITS |
368 SDIO_HOST_CTRL_BIG_ENDIAN |
369 SDIO_HOST_CTRL_PUSH_PULL_EN |
370 SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY);
372 mvebu_mmc_write(SDIO_CLK_CTRL, 0);
375 mvebu_mmc_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
376 mvebu_mmc_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
378 /* disable interrupts */
379 mvebu_mmc_write(SDIO_NOR_INTR_EN, 0);
380 mvebu_mmc_write(SDIO_ERR_INTR_EN, 0);
382 mvebu_window_setup();
385 mvebu_mmc_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);
392 static const struct mmc_ops mvebu_mmc_ops = {
393 .send_cmd = mvebu_mmc_send_cmd,
394 .set_ios = mvebu_mmc_set_ios,
395 .init = mvebu_mmc_initialize,
398 static struct mmc_config mvebu_mmc_cfg = {
400 .ops = &mvebu_mmc_ops,
401 .f_min = MVEBU_MMC_BASE_FAST_CLOCK / MVEBU_MMC_BASE_DIV_MAX,
402 .f_max = MVEBU_MMC_CLOCKRATE_MAX,
403 .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
404 .host_caps = MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HC |
406 .part_type = PART_TYPE_DOS,
407 .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
410 int mvebu_mmc_init(bd_t *bis)
414 mvebu_mmc_power_up();
416 mmc = mmc_create(&mvebu_mmc_cfg, bis);