2 * Freescale i.MX28 SSP MMC driver
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
11 * Copyright 2007, Freescale Semiconductor, Inc
14 * Based vaguely on the pxa mmc code:
16 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
18 * See file CREDITS for list of people who contributed to this
21 * This program is free software; you can redistribute it and/or
22 * modify it under the terms of the GNU General Public License as
23 * published by the Free Software Foundation; either version 2 of
24 * the License, or (at your option) any later version.
26 * This program is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU General Public License for more details.
31 * You should have received a copy of the GNU General Public License
32 * along with this program; if not, write to the Free Software
33 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
39 #include <asm/errno.h>
41 #include <asm/arch/clock.h>
42 #include <asm/arch/imx-regs.h>
43 #include <asm/arch/sys_proto.h>
44 #include <asm/arch/dma.h>
47 * CONFIG_MXS_MMC_DMA: This feature is highly experimental and has no
48 * performance benefit unless you operate the platform with
49 * data cache enabled. This is disabled by default, enable
50 * only if you know what you're doing.
55 struct mxs_ssp_regs *regs;
56 uint32_t clkseq_bypass;
57 uint32_t *clkctrl_ssp;
59 int (*mmc_is_wp)(int);
60 struct mxs_dma_desc *desc;
63 #define MXSMMC_MAX_TIMEOUT 10000
66 * Sends a command out on the bus. Takes the mmc pointer,
67 * a command pointer, and an optional data pointer.
70 mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
72 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
73 struct mxs_ssp_regs *ssp_regs = priv->regs;
78 #ifndef CONFIG_MXS_MMC_DMA
81 uint32_t cache_data_count;
85 debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx);
88 timeout = MXSMMC_MAX_TIMEOUT;
91 reg = readl(&ssp_regs->hw_ssp_status);
93 (SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY |
94 SSP_STATUS_CMD_BUSY))) {
100 printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev);
104 /* See if card is present */
105 if (readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT) {
106 printf("MMC%d: No card detected!\n", mmc->block_dev.dev);
110 /* Start building CTRL0 contents */
111 ctrl0 = priv->buswidth;
114 if (!(cmd->resp_type & MMC_RSP_CRC))
115 ctrl0 |= SSP_CTRL0_IGNORE_CRC;
116 if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */
117 ctrl0 |= SSP_CTRL0_GET_RESP;
118 if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */
119 ctrl0 |= SSP_CTRL0_LONG_RESP;
122 reg = readl(&ssp_regs->hw_ssp_cmd0);
123 reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC);
124 reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET;
125 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
126 reg |= SSP_CMD0_APPEND_8CYC;
127 writel(reg, &ssp_regs->hw_ssp_cmd0);
129 /* Command argument */
130 writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1);
135 if (data->flags & MMC_DATA_READ) {
136 ctrl0 |= SSP_CTRL0_READ;
137 } else if (priv->mmc_is_wp &&
138 priv->mmc_is_wp(mmc->block_dev.dev)) {
139 printf("MMC%d: Can not write a locked card!\n",
144 ctrl0 |= SSP_CTRL0_DATA_XFER;
145 reg = ((data->blocks - 1) <<
146 SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) |
147 ((ffs(data->blocksize) - 1) <<
148 SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET);
149 writel(reg, &ssp_regs->hw_ssp_block_size);
151 reg = data->blocksize * data->blocks;
152 writel(reg, &ssp_regs->hw_ssp_xfer_size);
155 /* Kick off the command */
156 ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN;
157 writel(ctrl0, &ssp_regs->hw_ssp_ctrl0);
159 /* Wait for the command to complete */
160 timeout = MXSMMC_MAX_TIMEOUT;
163 reg = readl(&ssp_regs->hw_ssp_status);
164 if (!(reg & SSP_STATUS_CMD_BUSY))
169 printf("MMC%d: Command %d busy\n",
170 mmc->block_dev.dev, cmd->cmdidx);
174 /* Check command timeout */
175 if (reg & SSP_STATUS_RESP_TIMEOUT) {
176 printf("MMC%d: Command %d timeout (status 0x%08x)\n",
177 mmc->block_dev.dev, cmd->cmdidx, reg);
181 /* Check command errors */
182 if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) {
183 printf("MMC%d: Command %d error (status 0x%08x)!\n",
184 mmc->block_dev.dev, cmd->cmdidx, reg);
188 /* Copy response to response buffer */
189 if (cmd->resp_type & MMC_RSP_136) {
190 cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0);
191 cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1);
192 cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2);
193 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3);
195 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0);
197 /* Return if no data to process */
201 data_count = data->blocksize * data->blocks;
202 timeout = MXSMMC_MAX_TIMEOUT;
204 #ifdef CONFIG_MXS_MMC_DMA
205 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
207 if (data_count % ARCH_DMA_MINALIGN)
208 cache_data_count = roundup(data_count, ARCH_DMA_MINALIGN);
210 cache_data_count = data_count;
212 if (data->flags & MMC_DATA_READ) {
213 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
214 priv->desc->cmd.address = (dma_addr_t)data->dest;
216 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
217 priv->desc->cmd.address = (dma_addr_t)data->src;
219 /* Flush data to DRAM so DMA can pick them up */
220 flush_dcache_range((uint32_t)priv->desc->cmd.address,
221 (uint32_t)(priv->desc->cmd.address + cache_data_count));
224 priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
225 (data_count << MXS_DMA_DESC_BYTES_OFFSET);
228 dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id;
229 mxs_dma_desc_append(dmach, priv->desc);
230 if (mxs_dma_go(dmach)) {
231 printf("MMC%d: DMA transfer failed\n", mmc->block_dev.dev);
235 /* The data arrived into DRAM, invalidate cache over them */
236 if (data->flags & MMC_DATA_READ) {
237 invalidate_dcache_range((uint32_t)priv->desc->cmd.address,
238 (uint32_t)(priv->desc->cmd.address + cache_data_count));
241 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
243 if (data->flags & MMC_DATA_READ) {
244 data_ptr = (uint32_t *)data->dest;
245 while (data_count && --timeout) {
246 reg = readl(&ssp_regs->hw_ssp_status);
247 if (!(reg & SSP_STATUS_FIFO_EMPTY)) {
248 *data_ptr++ = readl(&ssp_regs->hw_ssp_data);
250 timeout = MXSMMC_MAX_TIMEOUT;
255 data_ptr = (uint32_t *)data->src;
257 while (data_count && --timeout) {
258 reg = readl(&ssp_regs->hw_ssp_status);
259 if (!(reg & SSP_STATUS_FIFO_FULL)) {
260 writel(*data_ptr++, &ssp_regs->hw_ssp_data);
262 timeout = MXSMMC_MAX_TIMEOUT;
269 printf("MMC%d: Data timeout with command %d (status 0x%08x)!\n",
270 mmc->block_dev.dev, cmd->cmdidx, reg);
275 /* Check data errors */
276 reg = readl(&ssp_regs->hw_ssp_status);
278 (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR |
279 SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) {
280 printf("MMC%d: Data error with command %d (status 0x%08x)!\n",
281 mmc->block_dev.dev, cmd->cmdidx, reg);
288 static void mxsmmc_set_ios(struct mmc *mmc)
290 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
291 struct mxs_ssp_regs *ssp_regs = priv->regs;
293 /* Set the clock speed */
295 mx28_set_ssp_busclock(priv->id, mmc->clock / 1000);
297 switch (mmc->bus_width) {
299 priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
302 priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
305 priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
309 /* Set the bus width */
310 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
311 SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);
313 debug("MMC%d: Set %d bits bus width\n",
314 mmc->block_dev.dev, mmc->bus_width);
317 static int mxsmmc_init(struct mmc *mmc)
319 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
320 struct mxs_ssp_regs *ssp_regs = priv->regs;
323 mx28_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
325 /* 8 bits word length in MMC mode */
326 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1,
327 SSP_CTRL1_SSP_MODE_MASK | SSP_CTRL1_WORD_LENGTH_MASK,
328 SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
329 SSP_CTRL1_DMA_ENABLE);
331 /* Set initial bit clock 400 KHz */
332 mx28_set_ssp_busclock(priv->id, 400);
334 /* Send initial 74 clock cycles (185 us @ 400 KHz)*/
335 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
337 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);
342 int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int))
344 struct mxs_clkctrl_regs *clkctrl_regs =
345 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
346 struct mmc *mmc = NULL;
347 struct mxsmmc_priv *priv = NULL;
350 mmc = malloc(sizeof(struct mmc));
354 priv = malloc(sizeof(struct mxsmmc_priv));
360 priv->desc = mxs_dma_desc_alloc();
367 ret = mxs_dma_init_channel(id);
371 priv->mmc_is_wp = wp;
375 priv->regs = (struct mxs_ssp_regs *)MXS_SSP0_BASE;
376 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP0;
377 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp0;
380 priv->regs = (struct mxs_ssp_regs *)MXS_SSP1_BASE;
381 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP1;
382 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp1;
385 priv->regs = (struct mxs_ssp_regs *)MXS_SSP2_BASE;
386 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP2;
387 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp2;
390 priv->regs = (struct mxs_ssp_regs *)MXS_SSP3_BASE;
391 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP3;
392 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp3;
396 sprintf(mmc->name, "MXS MMC");
397 mmc->send_cmd = mxsmmc_send_cmd;
398 mmc->set_ios = mxsmmc_set_ios;
399 mmc->init = mxsmmc_init;
403 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
405 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
406 MMC_MODE_HS_52MHz | MMC_MODE_HS;
409 * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
410 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
411 * CLOCK_DIVIDE has to be an even value from 2 to 254, and
412 * CLOCK_RATE could be any integer from 0 to 255.
415 mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + id) * 1000 / 2;