git.sur5r.net Git - u-boot/blob - drivers/mmc/omap_hsmmc.c

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  * Sukumar Ghorai <s-ghorai@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation's version 2 of
  12  * the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26 #include <common.h>
  27 #include <malloc.h>
  28 #include <memalign.h>
  29 #include <mmc.h>
  30 #include <part.h>
  31 #include <i2c.h>
  32 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
  33 #include <palmas.h>
  34 #endif
  35 #include <asm/io.h>
  36 #include <asm/arch/mmc_host_def.h>
  37 #ifdef CONFIG_OMAP54XX
  38 #include <asm/arch/mux_dra7xx.h>
  39 #include <asm/arch/dra7xx_iodelay.h>
  40 #endif
  41 #if !defined(CONFIG_SOC_KEYSTONE)
  42 #include <asm/gpio.h>
  43 #include <asm/arch/sys_proto.h>
  44 #endif
  45 #ifdef CONFIG_MMC_OMAP36XX_PINS
  46 #include <asm/arch/mux.h>
  47 #endif
  48 #include <dm.h>
  49 #include <power/regulator.h>
  50
  51 DECLARE_GLOBAL_DATA_PTR;
  52
  53 /* simplify defines to OMAP_HSMMC_USE_GPIO */
  54 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
  55         (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
  56 #define OMAP_HSMMC_USE_GPIO
  57 #else
  58 #undef OMAP_HSMMC_USE_GPIO
  59 #endif
  60
  61 /* common definitions for all OMAPs */
  62 #define SYSCTL_SRC      (1 << 25)
  63 #define SYSCTL_SRD      (1 << 26)
  64
  65 #ifdef CONFIG_IODELAY_RECALIBRATION
  66 struct omap_hsmmc_pinctrl_state {
  67         struct pad_conf_entry *padconf;
  68         int npads;
  69         struct iodelay_cfg_entry *iodelay;
  70         int niodelays;
  71 };
  72 #endif
  73
  74 struct omap_hsmmc_data {
  75         struct hsmmc *base_addr;
  76 #if !CONFIG_IS_ENABLED(DM_MMC)
  77         struct mmc_config cfg;
  78 #endif
  79         uint bus_width;
  80         uint clock;
  81         ushort last_cmd;
  82 #ifdef OMAP_HSMMC_USE_GPIO
  83 #if CONFIG_IS_ENABLED(DM_MMC)
  84         struct gpio_desc cd_gpio;       /* Change Detect GPIO */
  85         struct gpio_desc wp_gpio;       /* Write Protect GPIO */
  86         bool cd_inverted;
  87 #else
  88         int cd_gpio;
  89         int wp_gpio;
  90 #endif
  91 #endif
  92 #if CONFIG_IS_ENABLED(DM_MMC)
  93         enum bus_mode mode;
  94 #endif
  95         u8 controller_flags;
  96 #ifndef CONFIG_OMAP34XX
  97         struct omap_hsmmc_adma_desc *adma_desc_table;
  98         uint desc_slot;
  99 #endif
 100         const char *hw_rev;
 101         struct udevice *pbias_supply;
 102         uint signal_voltage;
 103 #ifdef CONFIG_IODELAY_RECALIBRATION
 104         struct omap_hsmmc_pinctrl_state *default_pinctrl_state;
 105         struct omap_hsmmc_pinctrl_state *hs_pinctrl_state;
 106         struct omap_hsmmc_pinctrl_state *hs200_1_8v_pinctrl_state;
 107         struct omap_hsmmc_pinctrl_state *ddr_1_8v_pinctrl_state;
 108         struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state;
 109         struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state;
 110         struct omap_hsmmc_pinctrl_state *ddr50_pinctrl_state;
 111         struct omap_hsmmc_pinctrl_state *sdr50_pinctrl_state;
 112         struct omap_hsmmc_pinctrl_state *sdr104_pinctrl_state;
 113 #endif
 114 };
 115
 116 struct omap_mmc_of_data {
 117         u8 controller_flags;
 118 };
 119
 120 #ifndef CONFIG_OMAP34XX
 121 struct omap_hsmmc_adma_desc {
 122         u8 attr;
 123         u8 reserved;
 124         u16 len;
 125         u32 addr;
 126 };
 127
 128 #define ADMA_MAX_LEN    63488
 129
 130 /* Decriptor table defines */
 131 #define ADMA_DESC_ATTR_VALID            BIT(0)
 132 #define ADMA_DESC_ATTR_END              BIT(1)
 133 #define ADMA_DESC_ATTR_INT              BIT(2)
 134 #define ADMA_DESC_ATTR_ACT1             BIT(4)
 135 #define ADMA_DESC_ATTR_ACT2             BIT(5)
 136
 137 #define ADMA_DESC_TRANSFER_DATA         ADMA_DESC_ATTR_ACT2
 138 #define ADMA_DESC_LINK_DESC     (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
 139 #endif
 140
 141 /* If we fail after 1 second wait, something is really bad */
 142 #define MAX_RETRY_MS    1000
 143 #define MMC_TIMEOUT_MS  20
 144
 145 /* DMA transfers can take a long time if a lot a data is transferred.
 146  * The timeout must take in account the amount of data. Let's assume
 147  * that the time will never exceed 333 ms per MB (in other word we assume
 148  * that the bandwidth is always above 3MB/s).
 149  */
 150 #define DMA_TIMEOUT_PER_MB      333
 151 #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT           BIT(0)
 152 #define OMAP_HSMMC_NO_1_8_V                     BIT(1)
 153 #define OMAP_HSMMC_USE_ADMA                     BIT(2)
 154 #define OMAP_HSMMC_REQUIRE_IODELAY              BIT(3)
 155
 156 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
 157 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 158                         unsigned int siz);
 159 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
 160 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
 161 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit);
 162
 163 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
 164 {
 165 #if CONFIG_IS_ENABLED(DM_MMC)
 166         return dev_get_priv(mmc->dev);
 167 #else
 168         return (struct omap_hsmmc_data *)mmc->priv;
 169 #endif
 170 }
 171 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
 172 {
 173 #if CONFIG_IS_ENABLED(DM_MMC)
 174         struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
 175         return &plat->cfg;
 176 #else
 177         return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
 178 #endif
 179 }
 180
 181 #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
 182 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
 183 {
 184         int ret;
 185
 186 #ifndef CONFIG_DM_GPIO
 187         if (!gpio_is_valid(gpio))
 188                 return -1;
 189 #endif
 190         ret = gpio_request(gpio, label);
 191         if (ret)
 192                 return ret;
 193
 194         ret = gpio_direction_input(gpio);
 195         if (ret)
 196                 return ret;
 197
 198         return gpio;
 199 }
 200 #endif
 201
 202 static unsigned char mmc_board_init(struct mmc *mmc)
 203 {
 204 #if defined(CONFIG_OMAP34XX)
 205         struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
 206         t2_t *t2_base = (t2_t *)T2_BASE;
 207         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 208         u32 pbias_lite;
 209 #ifdef CONFIG_MMC_OMAP36XX_PINS
 210         u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
 211 #endif
 212
 213         pbias_lite = readl(&t2_base->pbias_lite);
 214         pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
 215 #ifdef CONFIG_TARGET_OMAP3_CAIRO
 216         /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
 217         pbias_lite &= ~PBIASLITEVMODE0;
 218 #endif
 219 #ifdef CONFIG_MMC_OMAP36XX_PINS
 220         if (get_cpu_family() == CPU_OMAP36XX) {
 221                 /* Disable extended drain IO before changing PBIAS */
 222                 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
 223                 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
 224         }
 225 #endif
 226         writel(pbias_lite, &t2_base->pbias_lite);
 227
 228         writel(pbias_lite | PBIASLITEPWRDNZ1 |
 229                 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
 230                 &t2_base->pbias_lite);
 231
 232 #ifdef CONFIG_MMC_OMAP36XX_PINS
 233         if (get_cpu_family() == CPU_OMAP36XX)
 234                 /* Enable extended drain IO after changing PBIAS */
 235                 writel(wkup_ctrl |
 236                                 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
 237                                 OMAP34XX_CTRL_WKUP_CTRL);
 238 #endif
 239         writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
 240                 &t2_base->devconf0);
 241
 242         writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
 243                 &t2_base->devconf1);
 244
 245         /* Change from default of 52MHz to 26MHz if necessary */
 246         if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
 247                 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
 248                         &t2_base->ctl_prog_io1);
 249
 250         writel(readl(&prcm_base->fclken1_core) |
 251                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 252                 &prcm_base->fclken1_core);
 253
 254         writel(readl(&prcm_base->iclken1_core) |
 255                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 256                 &prcm_base->iclken1_core);
 257 #endif
 258
 259 #if (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) &&\
 260         !CONFIG_IS_ENABLED(DM_REGULATOR)
 261         /* PBIAS config needed for MMC1 only */
 262         if (mmc_get_blk_desc(mmc)->devnum == 0)
 263                 vmmc_pbias_config(LDO_VOLT_3V0);
 264 #endif
 265
 266         return 0;
 267 }
 268
 269 void mmc_init_stream(struct hsmmc *mmc_base)
 270 {
 271         ulong start;
 272
 273         writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
 274
 275         writel(MMC_CMD0, &mmc_base->cmd);
 276         start = get_timer(0);
 277         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 278                 if (get_timer(0) - start > MAX_RETRY_MS) {
 279                         printf("%s: timedout waiting for cc!\n", __func__);
 280                         return;
 281                 }
 282         }
 283         writel(CC_MASK, &mmc_base->stat)
 284                 ;
 285         writel(MMC_CMD0, &mmc_base->cmd)
 286                 ;
 287         start = get_timer(0);
 288         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 289                 if (get_timer(0) - start > MAX_RETRY_MS) {
 290                         printf("%s: timedout waiting for cc2!\n", __func__);
 291                         return;
 292                 }
 293         }
 294         writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
 295 }
 296
 297 #if CONFIG_IS_ENABLED(DM_MMC)
 298 #ifdef CONFIG_IODELAY_RECALIBRATION
 299 static void omap_hsmmc_io_recalibrate(struct mmc *mmc)
 300 {
 301         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 302         struct omap_hsmmc_pinctrl_state *pinctrl_state;
 303
 304         switch (priv->mode) {
 305         case MMC_HS_200:
 306                 pinctrl_state = priv->hs200_1_8v_pinctrl_state;
 307                 break;
 308         case UHS_SDR104:
 309                 pinctrl_state = priv->sdr104_pinctrl_state;
 310                 break;
 311         case UHS_SDR50:
 312                 pinctrl_state = priv->sdr50_pinctrl_state;
 313                 break;
 314         case UHS_DDR50:
 315                 pinctrl_state = priv->ddr50_pinctrl_state;
 316                 break;
 317         case UHS_SDR25:
 318                 pinctrl_state = priv->sdr25_pinctrl_state;
 319                 break;
 320         case UHS_SDR12:
 321                 pinctrl_state = priv->sdr12_pinctrl_state;
 322                 break;
 323         case SD_HS:
 324         case MMC_HS:
 325         case MMC_HS_52:
 326                 pinctrl_state = priv->hs_pinctrl_state;
 327                 break;
 328         case MMC_DDR_52:
 329                 pinctrl_state = priv->ddr_1_8v_pinctrl_state;
 330         default:
 331                 pinctrl_state = priv->default_pinctrl_state;
 332                 break;
 333         }
 334
 335         if (!pinctrl_state)
 336                 pinctrl_state = priv->default_pinctrl_state;
 337
 338         if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) {
 339                 if (pinctrl_state->iodelay)
 340                         late_recalibrate_iodelay(pinctrl_state->padconf,
 341                                                  pinctrl_state->npads,
 342                                                  pinctrl_state->iodelay,
 343                                                  pinctrl_state->niodelays);
 344                 else
 345                         do_set_mux32((*ctrl)->control_padconf_core_base,
 346                                      pinctrl_state->padconf,
 347                                      pinctrl_state->npads);
 348         }
 349 }
 350 #endif
 351 static void omap_hsmmc_set_timing(struct mmc *mmc)
 352 {
 353         u32 val;
 354         struct hsmmc *mmc_base;
 355         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 356
 357         mmc_base = priv->base_addr;
 358
 359         omap_hsmmc_stop_clock(mmc_base);
 360         val = readl(&mmc_base->ac12);
 361         val &= ~AC12_UHSMC_MASK;
 362         priv->mode = mmc->selected_mode;
 363
 364         if (mmc_is_mode_ddr(priv->mode))
 365                 writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
 366         else
 367                 writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
 368
 369         switch (priv->mode) {
 370         case MMC_HS_200:
 371         case UHS_SDR104:
 372                 val |= AC12_UHSMC_SDR104;
 373                 break;
 374         case UHS_SDR50:
 375                 val |= AC12_UHSMC_SDR50;
 376                 break;
 377         case MMC_DDR_52:
 378         case UHS_DDR50:
 379                 val |= AC12_UHSMC_DDR50;
 380                 break;
 381         case SD_HS:
 382         case MMC_HS_52:
 383         case UHS_SDR25:
 384                 val |= AC12_UHSMC_SDR25;
 385                 break;
 386         case MMC_LEGACY:
 387         case MMC_HS:
 388         case SD_LEGACY:
 389         case UHS_SDR12:
 390                 val |= AC12_UHSMC_SDR12;
 391                 break;
 392         default:
 393                 val |= AC12_UHSMC_RES;
 394                 break;
 395         }
 396         writel(val, &mmc_base->ac12);
 397
 398 #ifdef CONFIG_IODELAY_RECALIBRATION
 399         omap_hsmmc_io_recalibrate(mmc);
 400 #endif
 401         omap_hsmmc_start_clock(mmc_base);
 402 }
 403
 404 static void omap_hsmmc_conf_bus_power(struct mmc *mmc, uint signal_voltage)
 405 {
 406         struct hsmmc *mmc_base;
 407         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 408         u32 hctl, ac12;
 409
 410         mmc_base = priv->base_addr;
 411
 412         hctl = readl(&mmc_base->hctl) & ~SDVS_MASK;
 413         ac12 = readl(&mmc_base->ac12) & ~AC12_V1V8_SIGEN;
 414
 415         switch (signal_voltage) {
 416         case MMC_SIGNAL_VOLTAGE_330:
 417                 hctl |= SDVS_3V0;
 418                 break;
 419         case MMC_SIGNAL_VOLTAGE_180:
 420                 hctl |= SDVS_1V8;
 421                 ac12 |= AC12_V1V8_SIGEN;
 422                 break;
 423         }
 424
 425         writel(hctl, &mmc_base->hctl);
 426         writel(ac12, &mmc_base->ac12);
 427 }
 428
 429 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 430 static int omap_hsmmc_wait_dat0(struct udevice *dev, int state, int timeout)
 431 {
 432         int ret = -ETIMEDOUT;
 433         u32 con;
 434         bool dat0_high;
 435         bool target_dat0_high = !!state;
 436         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 437         struct hsmmc *mmc_base = priv->base_addr;
 438
 439         con = readl(&mmc_base->con);
 440         writel(con | CON_CLKEXTFREE | CON_PADEN, &mmc_base->con);
 441
 442         timeout = DIV_ROUND_UP(timeout, 10); /* check every 10 us. */
 443         while (timeout--)       {
 444                 dat0_high = !!(readl(&mmc_base->pstate) & PSTATE_DLEV_DAT0);
 445                 if (dat0_high == target_dat0_high) {
 446                         ret = 0;
 447                         break;
 448                 }
 449                 udelay(10);
 450         }
 451         writel(con, &mmc_base->con);
 452
 453         return ret;
 454 }
 455 #endif
 456
 457 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
 458 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 459 static int omap_hsmmc_set_io_regulator(struct mmc *mmc, int mV)
 460 {
 461         int ret = 0;
 462         int uV = mV * 1000;
 463
 464         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 465
 466         if (!mmc->vqmmc_supply)
 467                 return 0;
 468
 469         /* Disable PBIAS */
 470         ret = regulator_set_enable(priv->pbias_supply, false);
 471         if (ret && ret != -ENOSYS)
 472                 return ret;
 473
 474         /* Turn off IO voltage */
 475         ret = regulator_set_enable(mmc->vqmmc_supply, false);
 476         if (ret && ret != -ENOSYS)
 477                 return ret;
 478         /* Program a new IO voltage value */
 479         ret = regulator_set_value(mmc->vqmmc_supply, uV);
 480         if (ret)
 481                 return ret;
 482         /* Turn on IO voltage */
 483         ret = regulator_set_enable(mmc->vqmmc_supply, true);
 484         if (ret && ret != -ENOSYS)
 485                 return ret;
 486
 487         /* Program PBIAS voltage*/
 488         ret = regulator_set_value(priv->pbias_supply, uV);
 489         if (ret && ret != -ENOSYS)
 490                 return ret;
 491         /* Enable PBIAS */
 492         ret = regulator_set_enable(priv->pbias_supply, true);
 493         if (ret && ret != -ENOSYS)
 494                 return ret;
 495
 496         return 0;
 497 }
 498 #endif
 499
 500 static int omap_hsmmc_set_signal_voltage(struct mmc *mmc)
 501 {
 502         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 503         struct hsmmc *mmc_base = priv->base_addr;
 504         int mv = mmc_voltage_to_mv(mmc->signal_voltage);
 505         u32 capa_mask;
 506         __maybe_unused u8 palmas_ldo_volt;
 507         u32 val;
 508
 509         if (mv < 0)
 510                 return -EINVAL;
 511
 512         if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
 513                 /* Use 3.0V rather than 3.3V */
 514                 mv = 3000;
 515                 capa_mask = VS30_3V0SUP;
 516                 palmas_ldo_volt = LDO_VOLT_3V0;
 517         } else if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
 518                 capa_mask = VS18_1V8SUP;
 519                 palmas_ldo_volt = LDO_VOLT_1V8;
 520         } else {
 521                 return -EOPNOTSUPP;
 522         }
 523
 524         val = readl(&mmc_base->capa);
 525         if (!(val & capa_mask))
 526                 return -EOPNOTSUPP;
 527
 528         priv->signal_voltage = mmc->signal_voltage;
 529
 530         omap_hsmmc_conf_bus_power(mmc, mmc->signal_voltage);
 531
 532 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 533         return omap_hsmmc_set_io_regulator(mmc, mv);
 534 #elif (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) && \
 535         defined(CONFIG_PALMAS_POWER)
 536         if (mmc_get_blk_desc(mmc)->devnum == 0)
 537                 vmmc_pbias_config(palmas_ldo_volt);
 538         return 0;
 539 #else
 540         return 0;
 541 #endif
 542 }
 543 #endif
 544
 545 static uint32_t omap_hsmmc_set_capabilities(struct mmc *mmc)
 546 {
 547         struct hsmmc *mmc_base;
 548         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 549         u32 val;
 550
 551         mmc_base = priv->base_addr;
 552         val = readl(&mmc_base->capa);
 553
 554         if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
 555                 val |= (VS30_3V0SUP | VS18_1V8SUP);
 556         } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
 557                 val |= VS30_3V0SUP;
 558                 val &= ~VS18_1V8SUP;
 559         } else {
 560                 val |= VS18_1V8SUP;
 561                 val &= ~VS30_3V0SUP;
 562         }
 563
 564         writel(val, &mmc_base->capa);
 565
 566         return val;
 567 }
 568
 569 #ifdef MMC_SUPPORTS_TUNING
 570 static void omap_hsmmc_disable_tuning(struct mmc *mmc)
 571 {
 572         struct hsmmc *mmc_base;
 573         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 574         u32 val;
 575
 576         mmc_base = priv->base_addr;
 577         val = readl(&mmc_base->ac12);
 578         val &= ~(AC12_SCLK_SEL);
 579         writel(val, &mmc_base->ac12);
 580
 581         val = readl(&mmc_base->dll);
 582         val &= ~(DLL_FORCE_VALUE | DLL_SWT);
 583         writel(val, &mmc_base->dll);
 584 }
 585
 586 static void omap_hsmmc_set_dll(struct mmc *mmc, int count)
 587 {
 588         int i;
 589         struct hsmmc *mmc_base;
 590         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 591         u32 val;
 592
 593         mmc_base = priv->base_addr;
 594         val = readl(&mmc_base->dll);
 595         val |= DLL_FORCE_VALUE;
 596         val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT);
 597         val |= (count << DLL_FORCE_SR_C_SHIFT);
 598         writel(val, &mmc_base->dll);
 599
 600         val |= DLL_CALIB;
 601         writel(val, &mmc_base->dll);
 602         for (i = 0; i < 1000; i++) {
 603                 if (readl(&mmc_base->dll) & DLL_CALIB)
 604                         break;
 605         }
 606         val &= ~DLL_CALIB;
 607         writel(val, &mmc_base->dll);
 608 }
 609
 610 static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode)
 611 {
 612         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 613         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 614         struct mmc *mmc = upriv->mmc;
 615         struct hsmmc *mmc_base;
 616         u32 val;
 617         u8 cur_match, prev_match = 0;
 618         int ret;
 619         u32 phase_delay = 0;
 620         u32 start_window = 0, max_window = 0;
 621         u32 length = 0, max_len = 0;
 622
 623         mmc_base = priv->base_addr;
 624         val = readl(&mmc_base->capa2);
 625
 626         /* clock tuning is not needed for upto 52MHz */
 627         if (!((mmc->selected_mode == MMC_HS_200) ||
 628               (mmc->selected_mode == UHS_SDR104) ||
 629               ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50))))
 630                 return 0;
 631
 632         val = readl(&mmc_base->dll);
 633         val |= DLL_SWT;
 634         writel(val, &mmc_base->dll);
 635         while (phase_delay <= MAX_PHASE_DELAY) {
 636                 omap_hsmmc_set_dll(mmc, phase_delay);
 637
 638                 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
 639
 640                 if (cur_match) {
 641                         if (prev_match) {
 642                                 length++;
 643                         } else {
 644                                 start_window = phase_delay;
 645                                 length = 1;
 646                         }
 647                 }
 648
 649                 if (length > max_len) {
 650                         max_window = start_window;
 651                         max_len = length;
 652                 }
 653
 654                 prev_match = cur_match;
 655                 phase_delay += 4;
 656         }
 657
 658         if (!max_len) {
 659                 ret = -EIO;
 660                 goto tuning_error;
 661         }
 662
 663         val = readl(&mmc_base->ac12);
 664         if (!(val & AC12_SCLK_SEL)) {
 665                 ret = -EIO;
 666                 goto tuning_error;
 667         }
 668
 669         phase_delay = max_window + 4 * ((3 * max_len) >> 2);
 670         omap_hsmmc_set_dll(mmc, phase_delay);
 671
 672         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 673         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 674
 675         return 0;
 676
 677 tuning_error:
 678
 679         omap_hsmmc_disable_tuning(mmc);
 680         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 681         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 682
 683         return ret;
 684 }
 685 #endif
 686
 687 static void omap_hsmmc_send_init_stream(struct udevice *dev)
 688 {
 689         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 690         struct hsmmc *mmc_base = priv->base_addr;
 691
 692         mmc_init_stream(mmc_base);
 693 }
 694 #endif
 695
 696 static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
 697 {
 698         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 699         struct hsmmc *mmc_base = priv->base_addr;
 700         u32 irq_mask = INT_EN_MASK;
 701
 702         /*
 703          * TODO: Errata i802 indicates only DCRC interrupts can occur during
 704          * tuning procedure and DCRC should be disabled. But see occurences
 705          * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These
 706          * interrupts occur along with BRR, so the data is actually in the
 707          * buffer. It has to be debugged why these interrutps occur
 708          */
 709         if (cmd && mmc_is_tuning_cmd(cmd->cmdidx))
 710                 irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC);
 711
 712         writel(irq_mask, &mmc_base->ie);
 713 }
 714
 715 static int omap_hsmmc_init_setup(struct mmc *mmc)
 716 {
 717         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 718         struct hsmmc *mmc_base;
 719         unsigned int reg_val;
 720         unsigned int dsor;
 721         ulong start;
 722
 723         mmc_base = priv->base_addr;
 724         mmc_board_init(mmc);
 725
 726         writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
 727                 &mmc_base->sysconfig);
 728         start = get_timer(0);
 729         while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
 730                 if (get_timer(0) - start > MAX_RETRY_MS) {
 731                         printf("%s: timedout waiting for cc2!\n", __func__);
 732                         return -ETIMEDOUT;
 733                 }
 734         }
 735         writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
 736         start = get_timer(0);
 737         while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
 738                 if (get_timer(0) - start > MAX_RETRY_MS) {
 739                         printf("%s: timedout waiting for softresetall!\n",
 740                                 __func__);
 741                         return -ETIMEDOUT;
 742                 }
 743         }
 744 #ifndef CONFIG_OMAP34XX
 745         reg_val = readl(&mmc_base->hl_hwinfo);
 746         if (reg_val & MADMA_EN)
 747                 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
 748 #endif
 749
 750 #if CONFIG_IS_ENABLED(DM_MMC)
 751         reg_val = omap_hsmmc_set_capabilities(mmc);
 752         omap_hsmmc_conf_bus_power(mmc, (reg_val & VS30_3V0SUP) ?
 753                           MMC_SIGNAL_VOLTAGE_330 : MMC_SIGNAL_VOLTAGE_180);
 754 #else
 755         writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
 756         writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
 757                 &mmc_base->capa);
 758 #endif
 759
 760         reg_val = readl(&mmc_base->con) & RESERVED_MASK;
 761
 762         writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
 763                 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
 764                 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
 765
 766         dsor = 240;
 767         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 768                 (ICE_STOP | DTO_15THDTO));
 769         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 770                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 771         start = get_timer(0);
 772         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 773                 if (get_timer(0) - start > MAX_RETRY_MS) {
 774                         printf("%s: timedout waiting for ics!\n", __func__);
 775                         return -ETIMEDOUT;
 776                 }
 777         }
 778         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 779
 780         writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
 781
 782         mmc_enable_irq(mmc, NULL);
 783
 784 #if !CONFIG_IS_ENABLED(DM_MMC)
 785         mmc_init_stream(mmc_base);
 786 #endif
 787
 788         return 0;
 789 }
 790
 791 /*
 792  * MMC controller internal finite state machine reset
 793  *
 794  * Used to reset command or data internal state machines, using respectively
 795  * SRC or SRD bit of SYSCTL register
 796  */
 797 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
 798 {
 799         ulong start;
 800
 801         mmc_reg_out(&mmc_base->sysctl, bit, bit);
 802
 803         /*
 804          * CMD(DAT) lines reset procedures are slightly different
 805          * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
 806          * According to OMAP3 TRM:
 807          * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
 808          * returns to 0x0.
 809          * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
 810          * procedure steps must be as follows:
 811          * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
 812          *    MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
 813          * 2. Poll the SRC(SRD) bit until it is set to 0x1.
 814          * 3. Wait until the SRC (SRD) bit returns to 0x0
 815          *    (reset procedure is completed).
 816          */
 817 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
 818         defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
 819         if (!(readl(&mmc_base->sysctl) & bit)) {
 820                 start = get_timer(0);
 821                 while (!(readl(&mmc_base->sysctl) & bit)) {
 822                         if (get_timer(0) - start > MMC_TIMEOUT_MS)
 823                                 return;
 824                 }
 825         }
 826 #endif
 827         start = get_timer(0);
 828         while ((readl(&mmc_base->sysctl) & bit) != 0) {
 829                 if (get_timer(0) - start > MAX_RETRY_MS) {
 830                         printf("%s: timedout waiting for sysctl %x to clear\n",
 831                                 __func__, bit);
 832                         return;
 833                 }
 834         }
 835 }
 836
 837 #ifndef CONFIG_OMAP34XX
 838 static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
 839 {
 840         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 841         struct omap_hsmmc_adma_desc *desc;
 842         u8 attr;
 843
 844         desc = &priv->adma_desc_table[priv->desc_slot];
 845
 846         attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
 847         if (!end)
 848                 priv->desc_slot++;
 849         else
 850                 attr |= ADMA_DESC_ATTR_END;
 851
 852         desc->len = len;
 853         desc->addr = (u32)buf;
 854         desc->reserved = 0;
 855         desc->attr = attr;
 856 }
 857
 858 static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
 859                                           struct mmc_data *data)
 860 {
 861         uint total_len = data->blocksize * data->blocks;
 862         uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
 863         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 864         int i = desc_count;
 865         char *buf;
 866
 867         priv->desc_slot = 0;
 868         priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
 869                                 memalign(ARCH_DMA_MINALIGN, desc_count *
 870                                 sizeof(struct omap_hsmmc_adma_desc));
 871
 872         if (data->flags & MMC_DATA_READ)
 873                 buf = data->dest;
 874         else
 875                 buf = (char *)data->src;
 876
 877         while (--i) {
 878                 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
 879                 buf += ADMA_MAX_LEN;
 880                 total_len -= ADMA_MAX_LEN;
 881         }
 882
 883         omap_hsmmc_adma_desc(mmc, buf, total_len, true);
 884
 885         flush_dcache_range((long)priv->adma_desc_table,
 886                            (long)priv->adma_desc_table +
 887                            ROUND(desc_count *
 888                            sizeof(struct omap_hsmmc_adma_desc),
 889                            ARCH_DMA_MINALIGN));
 890 }
 891
 892 static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
 893 {
 894         struct hsmmc *mmc_base;
 895         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 896         u32 val;
 897         char *buf;
 898
 899         mmc_base = priv->base_addr;
 900         omap_hsmmc_prepare_adma_table(mmc, data);
 901
 902         if (data->flags & MMC_DATA_READ)
 903                 buf = data->dest;
 904         else
 905                 buf = (char *)data->src;
 906
 907         val = readl(&mmc_base->hctl);
 908         val |= DMA_SELECT;
 909         writel(val, &mmc_base->hctl);
 910
 911         val = readl(&mmc_base->con);
 912         val |= DMA_MASTER;
 913         writel(val, &mmc_base->con);
 914
 915         writel((u32)priv->adma_desc_table, &mmc_base->admasal);
 916
 917         flush_dcache_range((u32)buf,
 918                            (u32)buf +
 919                            ROUND(data->blocksize * data->blocks,
 920                                  ARCH_DMA_MINALIGN));
 921 }
 922
 923 static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
 924 {
 925         struct hsmmc *mmc_base;
 926         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 927         u32 val;
 928
 929         mmc_base = priv->base_addr;
 930
 931         val = readl(&mmc_base->con);
 932         val &= ~DMA_MASTER;
 933         writel(val, &mmc_base->con);
 934
 935         val = readl(&mmc_base->hctl);
 936         val &= ~DMA_SELECT;
 937         writel(val, &mmc_base->hctl);
 938
 939         kfree(priv->adma_desc_table);
 940 }
 941 #else
 942 #define omap_hsmmc_adma_desc
 943 #define omap_hsmmc_prepare_adma_table
 944 #define omap_hsmmc_prepare_data
 945 #define omap_hsmmc_dma_cleanup
 946 #endif
 947
 948 #if !CONFIG_IS_ENABLED(DM_MMC)
 949 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 950                         struct mmc_data *data)
 951 {
 952         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 953 #else
 954 static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 955                         struct mmc_data *data)
 956 {
 957         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 958         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 959         struct mmc *mmc = upriv->mmc;
 960 #endif
 961         struct hsmmc *mmc_base;
 962         unsigned int flags, mmc_stat;
 963         ulong start;
 964         priv->last_cmd = cmd->cmdidx;
 965
 966         mmc_base = priv->base_addr;
 967
 968         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 969                 return 0;
 970
 971         start = get_timer(0);
 972         while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
 973                 if (get_timer(0) - start > MAX_RETRY_MS) {
 974                         printf("%s: timedout waiting on cmd inhibit to clear\n",
 975                                         __func__);
 976                         return -ETIMEDOUT;
 977                 }
 978         }
 979         writel(0xFFFFFFFF, &mmc_base->stat);
 980         start = get_timer(0);
 981         while (readl(&mmc_base->stat)) {
 982                 if (get_timer(0) - start > MAX_RETRY_MS) {
 983                         printf("%s: timedout waiting for STAT (%x) to clear\n",
 984                                 __func__, readl(&mmc_base->stat));
 985                         return -ETIMEDOUT;
 986                 }
 987         }
 988         /*
 989          * CMDREG
 990          * CMDIDX[13:8] : Command index
 991          * DATAPRNT[5]  : Data Present Select
 992          * ENCMDIDX[4]  : Command Index Check Enable
 993          * ENCMDCRC[3]  : Command CRC Check Enable
 994          * RSPTYP[1:0]
 995          *      00 = No Response
 996          *      01 = Length 136
 997          *      10 = Length 48
 998          *      11 = Length 48 Check busy after response
 999          */
1000         /* Delay added before checking the status of frq change
1001          * retry not supported by mmc.c(core file)
1002          */
1003         if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
1004                 udelay(50000); /* wait 50 ms */
1005
1006         if (!(cmd->resp_type & MMC_RSP_PRESENT))
1007                 flags = 0;
1008         else if (cmd->resp_type & MMC_RSP_136)
1009                 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
1010         else if (cmd->resp_type & MMC_RSP_BUSY)
1011                 flags = RSP_TYPE_LGHT48B;
1012         else
1013                 flags = RSP_TYPE_LGHT48;
1014
1015         /* enable default flags */
1016         flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
1017                         MSBS_SGLEBLK);
1018         flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
1019
1020         if (cmd->resp_type & MMC_RSP_CRC)
1021                 flags |= CCCE_CHECK;
1022         if (cmd->resp_type & MMC_RSP_OPCODE)
1023                 flags |= CICE_CHECK;
1024
1025         if (data) {
1026                 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
1027                          (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
1028                         flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
1029                         data->blocksize = 512;
1030                         writel(data->blocksize | (data->blocks << 16),
1031                                                         &mmc_base->blk);
1032                 } else
1033                         writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
1034
1035                 if (data->flags & MMC_DATA_READ)
1036                         flags |= (DP_DATA | DDIR_READ);
1037                 else
1038                         flags |= (DP_DATA | DDIR_WRITE);
1039
1040 #ifndef CONFIG_OMAP34XX
1041                 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
1042                     !mmc_is_tuning_cmd(cmd->cmdidx)) {
1043                         omap_hsmmc_prepare_data(mmc, data);
1044                         flags |= DE_ENABLE;
1045                 }
1046 #endif
1047         }
1048
1049         mmc_enable_irq(mmc, cmd);
1050
1051         writel(cmd->cmdarg, &mmc_base->arg);
1052         udelay(20);             /* To fix "No status update" error on eMMC */
1053         writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
1054
1055         start = get_timer(0);
1056         do {
1057                 mmc_stat = readl(&mmc_base->stat);
1058                 if (get_timer(start) > MAX_RETRY_MS) {
1059                         printf("%s : timeout: No status update\n", __func__);
1060                         return -ETIMEDOUT;
1061                 }
1062         } while (!mmc_stat);
1063
1064         if ((mmc_stat & IE_CTO) != 0) {
1065                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1066                 return -ETIMEDOUT;
1067         } else if ((mmc_stat & ERRI_MASK) != 0)
1068                 return -1;
1069
1070         if (mmc_stat & CC_MASK) {
1071                 writel(CC_MASK, &mmc_base->stat);
1072                 if (cmd->resp_type & MMC_RSP_PRESENT) {
1073                         if (cmd->resp_type & MMC_RSP_136) {
1074                                 /* response type 2 */
1075                                 cmd->response[3] = readl(&mmc_base->rsp10);
1076                                 cmd->response[2] = readl(&mmc_base->rsp32);
1077                                 cmd->response[1] = readl(&mmc_base->rsp54);
1078                                 cmd->response[0] = readl(&mmc_base->rsp76);
1079                         } else
1080                                 /* response types 1, 1b, 3, 4, 5, 6 */
1081                                 cmd->response[0] = readl(&mmc_base->rsp10);
1082                 }
1083         }
1084
1085 #ifndef CONFIG_OMAP34XX
1086         if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
1087             !mmc_is_tuning_cmd(cmd->cmdidx)) {
1088                 u32 sz_mb, timeout;
1089
1090                 if (mmc_stat & IE_ADMAE) {
1091                         omap_hsmmc_dma_cleanup(mmc);
1092                         return -EIO;
1093                 }
1094
1095                 sz_mb = DIV_ROUND_UP(data->blocksize *  data->blocks, 1 << 20);
1096                 timeout = sz_mb * DMA_TIMEOUT_PER_MB;
1097                 if (timeout < MAX_RETRY_MS)
1098                         timeout = MAX_RETRY_MS;
1099
1100                 start = get_timer(0);
1101                 do {
1102                         mmc_stat = readl(&mmc_base->stat);
1103                         if (mmc_stat & TC_MASK) {
1104                                 writel(readl(&mmc_base->stat) | TC_MASK,
1105                                        &mmc_base->stat);
1106                                 break;
1107                         }
1108                         if (get_timer(start) > timeout) {
1109                                 printf("%s : DMA timeout: No status update\n",
1110                                        __func__);
1111                                 return -ETIMEDOUT;
1112                         }
1113                 } while (1);
1114
1115                 omap_hsmmc_dma_cleanup(mmc);
1116                 return 0;
1117         }
1118 #endif
1119
1120         if (data && (data->flags & MMC_DATA_READ)) {
1121                 mmc_read_data(mmc_base, data->dest,
1122                                 data->blocksize * data->blocks);
1123         } else if (data && (data->flags & MMC_DATA_WRITE)) {
1124                 mmc_write_data(mmc_base, data->src,
1125                                 data->blocksize * data->blocks);
1126         }
1127         return 0;
1128 }
1129
1130 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
1131 {
1132         unsigned int *output_buf = (unsigned int *)buf;
1133         unsigned int mmc_stat;
1134         unsigned int count;
1135
1136         /*
1137          * Start Polled Read
1138          */
1139         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1140         count /= 4;
1141
1142         while (size) {
1143                 ulong start = get_timer(0);
1144                 do {
1145                         mmc_stat = readl(&mmc_base->stat);
1146                         if (get_timer(0) - start > MAX_RETRY_MS) {
1147                                 printf("%s: timedout waiting for status!\n",
1148                                                 __func__);
1149                                 return -ETIMEDOUT;
1150                         }
1151                 } while (mmc_stat == 0);
1152
1153                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1154                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1155
1156                 if ((mmc_stat & ERRI_MASK) != 0)
1157                         return 1;
1158
1159                 if (mmc_stat & BRR_MASK) {
1160                         unsigned int k;
1161
1162                         writel(readl(&mmc_base->stat) | BRR_MASK,
1163                                 &mmc_base->stat);
1164                         for (k = 0; k < count; k++) {
1165                                 *output_buf = readl(&mmc_base->data);
1166                                 output_buf++;
1167                         }
1168                         size -= (count*4);
1169                 }
1170
1171                 if (mmc_stat & BWR_MASK)
1172                         writel(readl(&mmc_base->stat) | BWR_MASK,
1173                                 &mmc_base->stat);
1174
1175                 if (mmc_stat & TC_MASK) {
1176                         writel(readl(&mmc_base->stat) | TC_MASK,
1177                                 &mmc_base->stat);
1178                         break;
1179                 }
1180         }
1181         return 0;
1182 }
1183
1184 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1185                                 unsigned int size)
1186 {
1187         unsigned int *input_buf = (unsigned int *)buf;
1188         unsigned int mmc_stat;
1189         unsigned int count;
1190
1191         /*
1192          * Start Polled Write
1193          */
1194         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1195         count /= 4;
1196
1197         while (size) {
1198                 ulong start = get_timer(0);
1199                 do {
1200                         mmc_stat = readl(&mmc_base->stat);
1201                         if (get_timer(0) - start > MAX_RETRY_MS) {
1202                                 printf("%s: timedout waiting for status!\n",
1203                                                 __func__);
1204                                 return -ETIMEDOUT;
1205                         }
1206                 } while (mmc_stat == 0);
1207
1208                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1209                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1210
1211                 if ((mmc_stat & ERRI_MASK) != 0)
1212                         return 1;
1213
1214                 if (mmc_stat & BWR_MASK) {
1215                         unsigned int k;
1216
1217                         writel(readl(&mmc_base->stat) | BWR_MASK,
1218                                         &mmc_base->stat);
1219                         for (k = 0; k < count; k++) {
1220                                 writel(*input_buf, &mmc_base->data);
1221                                 input_buf++;
1222                         }
1223                         size -= (count*4);
1224                 }
1225
1226                 if (mmc_stat & BRR_MASK)
1227                         writel(readl(&mmc_base->stat) | BRR_MASK,
1228                                 &mmc_base->stat);
1229
1230                 if (mmc_stat & TC_MASK) {
1231                         writel(readl(&mmc_base->stat) | TC_MASK,
1232                                 &mmc_base->stat);
1233                         break;
1234                 }
1235         }
1236         return 0;
1237 }
1238
1239 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
1240 {
1241         writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
1242 }
1243
1244 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
1245 {
1246         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
1247 }
1248
1249 static void omap_hsmmc_set_clock(struct mmc *mmc)
1250 {
1251         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1252         struct hsmmc *mmc_base;
1253         unsigned int dsor = 0;
1254         ulong start;
1255
1256         mmc_base = priv->base_addr;
1257         omap_hsmmc_stop_clock(mmc_base);
1258
1259         /* TODO: Is setting DTO required here? */
1260         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
1261                     (ICE_STOP | DTO_15THDTO));
1262
1263         if (mmc->clock != 0) {
1264                 dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
1265                 if (dsor > CLKD_MAX)
1266                         dsor = CLKD_MAX;
1267         } else {
1268                 dsor = CLKD_MAX;
1269         }
1270
1271         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
1272                     (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
1273
1274         start = get_timer(0);
1275         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
1276                 if (get_timer(0) - start > MAX_RETRY_MS) {
1277                         printf("%s: timedout waiting for ics!\n", __func__);
1278                         return;
1279                 }
1280         }
1281
1282         priv->clock = MMC_CLOCK_REFERENCE * 1000000 / dsor;
1283         mmc->clock = priv->clock;
1284         omap_hsmmc_start_clock(mmc_base);
1285 }
1286
1287 static void omap_hsmmc_set_bus_width(struct mmc *mmc)
1288 {
1289         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1290         struct hsmmc *mmc_base;
1291
1292         mmc_base = priv->base_addr;
1293         /* configue bus width */
1294         switch (mmc->bus_width) {
1295         case 8:
1296                 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
1297                         &mmc_base->con);
1298                 break;
1299
1300         case 4:
1301                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1302                         &mmc_base->con);
1303                 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
1304                         &mmc_base->hctl);
1305                 break;
1306
1307         case 1:
1308         default:
1309                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1310                         &mmc_base->con);
1311                 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
1312                         &mmc_base->hctl);
1313                 break;
1314         }
1315
1316         priv->bus_width = mmc->bus_width;
1317 }
1318
1319 #if !CONFIG_IS_ENABLED(DM_MMC)
1320 static int omap_hsmmc_set_ios(struct mmc *mmc)
1321 {
1322         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1323 #else
1324 static int omap_hsmmc_set_ios(struct udevice *dev)
1325 {
1326         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1327         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1328         struct mmc *mmc = upriv->mmc;
1329 #endif
1330         struct hsmmc *mmc_base = priv->base_addr;
1331         int ret = 0;
1332
1333         if (priv->bus_width != mmc->bus_width)
1334                 omap_hsmmc_set_bus_width(mmc);
1335
1336         if (priv->clock != mmc->clock)
1337                 omap_hsmmc_set_clock(mmc);
1338
1339         if (mmc->clk_disable)
1340                 omap_hsmmc_stop_clock(mmc_base);
1341         else
1342                 omap_hsmmc_start_clock(mmc_base);
1343
1344 #if CONFIG_IS_ENABLED(DM_MMC)
1345         if (priv->mode != mmc->selected_mode)
1346                 omap_hsmmc_set_timing(mmc);
1347
1348 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1349         if (priv->signal_voltage != mmc->signal_voltage)
1350                 ret = omap_hsmmc_set_signal_voltage(mmc);
1351 #endif
1352 #endif
1353         return ret;
1354 }
1355
1356 #ifdef OMAP_HSMMC_USE_GPIO
1357 #if CONFIG_IS_ENABLED(DM_MMC)
1358 static int omap_hsmmc_getcd(struct udevice *dev)
1359 {
1360         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1361         int value;
1362
1363         value = dm_gpio_get_value(&priv->cd_gpio);
1364         /* if no CD return as 1 */
1365         if (value < 0)
1366                 return 1;
1367
1368         if (priv->cd_inverted)
1369                 return !value;
1370         return value;
1371 }
1372
1373 static int omap_hsmmc_getwp(struct udevice *dev)
1374 {
1375         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1376         int value;
1377
1378         value = dm_gpio_get_value(&priv->wp_gpio);
1379         /* if no WP return as 0 */
1380         if (value < 0)
1381                 return 0;
1382         return value;
1383 }
1384 #else
1385 static int omap_hsmmc_getcd(struct mmc *mmc)
1386 {
1387         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1388         int cd_gpio;
1389
1390         /* if no CD return as 1 */
1391         cd_gpio = priv->cd_gpio;
1392         if (cd_gpio < 0)
1393                 return 1;
1394
1395         /* NOTE: assumes card detect signal is active-low */
1396         return !gpio_get_value(cd_gpio);
1397 }
1398
1399 static int omap_hsmmc_getwp(struct mmc *mmc)
1400 {
1401         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1402         int wp_gpio;
1403
1404         /* if no WP return as 0 */
1405         wp_gpio = priv->wp_gpio;
1406         if (wp_gpio < 0)
1407                 return 0;
1408
1409         /* NOTE: assumes write protect signal is active-high */
1410         return gpio_get_value(wp_gpio);
1411 }
1412 #endif
1413 #endif
1414
1415 #if CONFIG_IS_ENABLED(DM_MMC)
1416 static const struct dm_mmc_ops omap_hsmmc_ops = {
1417         .send_cmd       = omap_hsmmc_send_cmd,
1418         .set_ios        = omap_hsmmc_set_ios,
1419 #ifdef OMAP_HSMMC_USE_GPIO
1420         .get_cd         = omap_hsmmc_getcd,
1421         .get_wp         = omap_hsmmc_getwp,
1422 #endif
1423 #ifdef MMC_SUPPORTS_TUNING
1424         .execute_tuning = omap_hsmmc_execute_tuning,
1425 #endif
1426         .send_init_stream       = omap_hsmmc_send_init_stream,
1427 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1428         .wait_dat0      = omap_hsmmc_wait_dat0,
1429 #endif
1430 };
1431 #else
1432 static const struct mmc_ops omap_hsmmc_ops = {
1433         .send_cmd       = omap_hsmmc_send_cmd,
1434         .set_ios        = omap_hsmmc_set_ios,
1435         .init           = omap_hsmmc_init_setup,
1436 #ifdef OMAP_HSMMC_USE_GPIO
1437         .getcd          = omap_hsmmc_getcd,
1438         .getwp          = omap_hsmmc_getwp,
1439 #endif
1440 };
1441 #endif
1442
1443 #if !CONFIG_IS_ENABLED(DM_MMC)
1444 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
1445                 int wp_gpio)
1446 {
1447         struct mmc *mmc;
1448         struct omap_hsmmc_data *priv;
1449         struct mmc_config *cfg;
1450         uint host_caps_val;
1451
1452         priv = malloc(sizeof(*priv));
1453         if (priv == NULL)
1454                 return -1;
1455
1456         host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
1457
1458         switch (dev_index) {
1459         case 0:
1460                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1461                 break;
1462 #ifdef OMAP_HSMMC2_BASE
1463         case 1:
1464                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
1465 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
1466         defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
1467         defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
1468                 defined(CONFIG_HSMMC2_8BIT)
1469                 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
1470                 host_caps_val |= MMC_MODE_8BIT;
1471 #endif
1472                 break;
1473 #endif
1474 #ifdef OMAP_HSMMC3_BASE
1475         case 2:
1476                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
1477 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
1478                 /* Enable 8-bit interface for eMMC on DRA7XX */
1479                 host_caps_val |= MMC_MODE_8BIT;
1480 #endif
1481                 break;
1482 #endif
1483         default:
1484                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1485                 return 1;
1486         }
1487 #ifdef OMAP_HSMMC_USE_GPIO
1488         /* on error gpio values are set to -1, which is what we want */
1489         priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
1490         priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
1491 #endif
1492
1493         cfg = &priv->cfg;
1494
1495         cfg->name = "OMAP SD/MMC";
1496         cfg->ops = &omap_hsmmc_ops;
1497
1498         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1499         cfg->host_caps = host_caps_val & ~host_caps_mask;
1500
1501         cfg->f_min = 400000;
1502
1503         if (f_max != 0)
1504                 cfg->f_max = f_max;
1505         else {
1506                 if (cfg->host_caps & MMC_MODE_HS) {
1507                         if (cfg->host_caps & MMC_MODE_HS_52MHz)
1508                                 cfg->f_max = 52000000;
1509                         else
1510                                 cfg->f_max = 26000000;
1511                 } else
1512                         cfg->f_max = 20000000;
1513         }
1514
1515         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1516
1517 #if defined(CONFIG_OMAP34XX)
1518         /*
1519          * Silicon revs 2.1 and older do not support multiblock transfers.
1520          */
1521         if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
1522                 cfg->b_max = 1;
1523 #endif
1524
1525         mmc = mmc_create(cfg, priv);
1526         if (mmc == NULL)
1527                 return -1;
1528
1529         return 0;
1530 }
1531 #else
1532
1533 #ifdef CONFIG_IODELAY_RECALIBRATION
1534 static struct pad_conf_entry *
1535 omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count)
1536 {
1537         int index = 0;
1538         struct pad_conf_entry *padconf;
1539
1540         padconf = (struct pad_conf_entry *)malloc(sizeof(*padconf) * count);
1541         if (!padconf) {
1542                 debug("failed to allocate memory\n");
1543                 return 0;
1544         }
1545
1546         while (index < count) {
1547                 padconf[index].offset = fdt32_to_cpu(pinctrl[2 * index]);
1548                 padconf[index].val = fdt32_to_cpu(pinctrl[2 * index + 1]);
1549                 index++;
1550         }
1551
1552         return padconf;
1553 }
1554
1555 static struct iodelay_cfg_entry *
1556 omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t *pinctrl, int count)
1557 {
1558         int index = 0;
1559         struct iodelay_cfg_entry *iodelay;
1560
1561         iodelay = (struct iodelay_cfg_entry *)malloc(sizeof(*iodelay) * count);
1562         if (!iodelay) {
1563                 debug("failed to allocate memory\n");
1564                 return 0;
1565         }
1566
1567         while (index < count) {
1568                 iodelay[index].offset = fdt32_to_cpu(pinctrl[3 * index]);
1569                 iodelay[index].a_delay = fdt32_to_cpu(pinctrl[3 * index + 1]);
1570                 iodelay[index].g_delay = fdt32_to_cpu(pinctrl[3 * index + 2]);
1571                 index++;
1572         }
1573
1574         return iodelay;
1575 }
1576
1577 static const fdt32_t *omap_hsmmc_get_pinctrl_entry(u32  phandle,
1578                                                    const char *name, int *len)
1579 {
1580         const void *fdt = gd->fdt_blob;
1581         int offset;
1582         const fdt32_t *pinctrl;
1583
1584         offset = fdt_node_offset_by_phandle(fdt, phandle);
1585         if (offset < 0) {
1586                 debug("failed to get pinctrl node %s.\n",
1587                       fdt_strerror(offset));
1588                 return 0;
1589         }
1590
1591         pinctrl = fdt_getprop(fdt, offset, name, len);
1592         if (!pinctrl) {
1593                 debug("failed to get property %s\n", name);
1594                 return 0;
1595         }
1596
1597         return pinctrl;
1598 }
1599
1600 static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc *mmc,
1601                                                 char *prop_name)
1602 {
1603         const void *fdt = gd->fdt_blob;
1604         const __be32 *phandle;
1605         int node = dev_of_offset(mmc->dev);
1606
1607         phandle = fdt_getprop(fdt, node, prop_name, NULL);
1608         if (!phandle) {
1609                 debug("failed to get property %s\n", prop_name);
1610                 return 0;
1611         }
1612
1613         return fdt32_to_cpu(*phandle);
1614 }
1615
1616 static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc *mmc,
1617                                                char *prop_name)
1618 {
1619         const void *fdt = gd->fdt_blob;
1620         const __be32 *phandle;
1621         int len;
1622         int count;
1623         int node = dev_of_offset(mmc->dev);
1624
1625         phandle = fdt_getprop(fdt, node, prop_name, &len);
1626         if (!phandle) {
1627                 debug("failed to get property %s\n", prop_name);
1628                 return 0;
1629         }
1630
1631         /* No manual mode iodelay values if count < 2 */
1632         count = len / sizeof(*phandle);
1633         if (count < 2)
1634                 return 0;
1635
1636         return fdt32_to_cpu(*(phandle + 1));
1637 }
1638
1639 static struct pad_conf_entry *
1640 omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads)
1641 {
1642         int len;
1643         int count;
1644         struct pad_conf_entry *padconf;
1645         u32 phandle;
1646         const fdt32_t *pinctrl;
1647
1648         phandle = omap_hsmmc_get_pad_conf_phandle(mmc, prop_name);
1649         if (!phandle)
1650                 return ERR_PTR(-EINVAL);
1651
1652         pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-single,pins",
1653                                                &len);
1654         if (!pinctrl)
1655                 return ERR_PTR(-EINVAL);
1656
1657         count = (len / sizeof(*pinctrl)) / 2;
1658         padconf = omap_hsmmc_get_pad_conf_entry(pinctrl, count);
1659         if (!padconf)
1660                 return ERR_PTR(-EINVAL);
1661
1662         *npads = count;
1663
1664         return padconf;
1665 }
1666
1667 static struct iodelay_cfg_entry *
1668 omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay)
1669 {
1670         int len;
1671         int count;
1672         struct iodelay_cfg_entry *iodelay;
1673         u32 phandle;
1674         const fdt32_t *pinctrl;
1675
1676         phandle = omap_hsmmc_get_iodelay_phandle(mmc, prop_name);
1677         /* Not all modes have manual mode iodelay values. So its not fatal */
1678         if (!phandle)
1679                 return 0;
1680
1681         pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-pin-array",
1682                                                &len);
1683         if (!pinctrl)
1684                 return ERR_PTR(-EINVAL);
1685
1686         count = (len / sizeof(*pinctrl)) / 3;
1687         iodelay = omap_hsmmc_get_iodelay_cfg_entry(pinctrl, count);
1688         if (!iodelay)
1689                 return ERR_PTR(-EINVAL);
1690
1691         *niodelay = count;
1692
1693         return iodelay;
1694 }
1695
1696 static struct omap_hsmmc_pinctrl_state *
1697 omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode)
1698 {
1699         int index;
1700         int npads = 0;
1701         int niodelays = 0;
1702         const void *fdt = gd->fdt_blob;
1703         int node = dev_of_offset(mmc->dev);
1704         char prop_name[11];
1705         struct omap_hsmmc_pinctrl_state *pinctrl_state;
1706
1707         pinctrl_state = (struct omap_hsmmc_pinctrl_state *)
1708                          malloc(sizeof(*pinctrl_state));
1709         if (!pinctrl_state) {
1710                 debug("failed to allocate memory\n");
1711                 return 0;
1712         }
1713
1714         index = fdt_stringlist_search(fdt, node, "pinctrl-names", mode);
1715         if (index < 0) {
1716                 debug("fail to find %s mode %s\n", mode, fdt_strerror(index));
1717                 goto err_pinctrl_state;
1718         }
1719
1720         sprintf(prop_name, "pinctrl-%d", index);
1721
1722         pinctrl_state->padconf = omap_hsmmc_get_pad_conf(mmc, prop_name,
1723                                                          &npads);
1724         if (IS_ERR(pinctrl_state->padconf))
1725                 goto err_pinctrl_state;
1726         pinctrl_state->npads = npads;
1727
1728         pinctrl_state->iodelay = omap_hsmmc_get_iodelay(mmc, prop_name,
1729                                                         &niodelays);
1730         if (IS_ERR(pinctrl_state->iodelay))
1731                 goto err_padconf;
1732         pinctrl_state->niodelays = niodelays;
1733
1734         return pinctrl_state;
1735
1736 err_padconf:
1737         kfree(pinctrl_state->padconf);
1738
1739 err_pinctrl_state:
1740         kfree(pinctrl_state);
1741         return 0;
1742 }
1743
1744 #define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode, optional)               \
1745         do {                                                            \
1746                 struct omap_hsmmc_pinctrl_state *s = NULL;              \
1747                 char str[20];                                           \
1748                 if (!(cfg->host_caps & capmask))                        \
1749                         break;                                          \
1750                                                                         \
1751                 if (priv->hw_rev) {                                     \
1752                         sprintf(str, "%s-%s", #mode, priv->hw_rev);     \
1753                         s = omap_hsmmc_get_pinctrl_by_mode(mmc, str);   \
1754                 }                                                       \
1755                                                                         \
1756                 if (!s)                                                 \
1757                         s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \
1758                                                                         \
1759                 if (!s && !optional) {                                  \
1760                         debug("%s: no pinctrl for %s\n",                \
1761                               mmc->dev->name, #mode);                   \
1762                         cfg->host_caps &= ~(capmask);                   \
1763                 } else {                                                \
1764                         priv->mode##_pinctrl_state = s;                 \
1765                 }                                                       \
1766         } while (0)
1767
1768 static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc)
1769 {
1770         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1771         struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
1772         struct omap_hsmmc_pinctrl_state *default_pinctrl;
1773
1774         if (!(priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY))
1775                 return 0;
1776
1777         default_pinctrl = omap_hsmmc_get_pinctrl_by_mode(mmc, "default");
1778         if (!default_pinctrl) {
1779                 printf("no pinctrl state for default mode\n");
1780                 return -EINVAL;
1781         }
1782
1783         priv->default_pinctrl_state = default_pinctrl;
1784
1785         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104, false);
1786         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50, false);
1787         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50, false);
1788         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25, false);
1789         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12, false);
1790
1791         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v, false);
1792         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v, false);
1793         OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs, true);
1794
1795         return 0;
1796 }
1797 #endif
1798
1799 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1800 #ifdef CONFIG_OMAP54XX
1801 __weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
1802 {
1803         return NULL;
1804 }
1805 #endif
1806
1807 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
1808 {
1809         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1810         struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev);
1811
1812         struct mmc_config *cfg = &plat->cfg;
1813 #ifdef CONFIG_OMAP54XX
1814         const struct mmc_platform_fixups *fixups;
1815 #endif
1816         const void *fdt = gd->fdt_blob;
1817         int node = dev_of_offset(dev);
1818         int ret;
1819
1820         plat->base_addr = map_physmem(devfdt_get_addr(dev),
1821                                       sizeof(struct hsmmc *),
1822                                       MAP_NOCACHE);
1823
1824         ret = mmc_of_parse(dev, cfg);
1825         if (ret < 0)
1826                 return ret;
1827
1828         cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1829         cfg->f_min = 400000;
1830         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1831         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1832         if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
1833                 plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1834         if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
1835                 plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
1836         if (of_data)
1837                 plat->controller_flags |= of_data->controller_flags;
1838
1839 #ifdef CONFIG_OMAP54XX
1840         fixups = platform_fixups_mmc(devfdt_get_addr(dev));
1841         if (fixups) {
1842                 plat->hw_rev = fixups->hw_rev;
1843                 cfg->host_caps &= ~fixups->unsupported_caps;
1844                 cfg->f_max = fixups->max_freq;
1845         }
1846 #endif
1847
1848 #ifdef OMAP_HSMMC_USE_GPIO
1849         plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted");
1850 #endif
1851
1852         return 0;
1853 }
1854 #endif
1855
1856 #ifdef CONFIG_BLK
1857
1858 static int omap_hsmmc_bind(struct udevice *dev)
1859 {
1860         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1861
1862         return mmc_bind(dev, &plat->mmc, &plat->cfg);
1863 }
1864 #endif
1865 static int omap_hsmmc_probe(struct udevice *dev)
1866 {
1867         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1868         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1869         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1870         struct mmc_config *cfg = &plat->cfg;
1871         struct mmc *mmc;
1872 #ifdef CONFIG_IODELAY_RECALIBRATION
1873         int ret;
1874 #endif
1875
1876         cfg->name = "OMAP SD/MMC";
1877         priv->base_addr = plat->base_addr;
1878         priv->controller_flags = plat->controller_flags;
1879         priv->hw_rev = plat->hw_rev;
1880 #ifdef OMAP_HSMMC_USE_GPIO
1881         priv->cd_inverted = plat->cd_inverted;
1882 #endif
1883
1884 #ifdef CONFIG_BLK
1885         mmc = &plat->mmc;
1886 #else
1887         mmc = mmc_create(cfg, priv);
1888         if (mmc == NULL)
1889                 return -1;
1890 #endif
1891 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1892         device_get_supply_regulator(dev, "pbias-supply",
1893                                     &priv->pbias_supply);
1894 #endif
1895 #if defined(OMAP_HSMMC_USE_GPIO) && CONFIG_IS_ENABLED(OF_CONTROL)
1896         gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1897         gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1898 #endif
1899
1900         mmc->dev = dev;
1901         upriv->mmc = mmc;
1902
1903 #ifdef CONFIG_IODELAY_RECALIBRATION
1904         ret = omap_hsmmc_get_pinctrl_state(mmc);
1905         /*
1906          * disable high speed modes for the platforms that require IO delay
1907          * and for which we don't have this information
1908          */
1909         if ((ret < 0) &&
1910             (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) {
1911                 priv->controller_flags &= ~OMAP_HSMMC_REQUIRE_IODELAY;
1912                 cfg->host_caps &= ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_DDR_52) |
1913                                     UHS_CAPS);
1914         }
1915 #endif
1916
1917         return omap_hsmmc_init_setup(mmc);
1918 }
1919
1920 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1921
1922 static const struct omap_mmc_of_data dra7_mmc_of_data = {
1923         .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY,
1924 };
1925
1926 static const struct udevice_id omap_hsmmc_ids[] = {
1927         { .compatible = "ti,omap3-hsmmc" },
1928         { .compatible = "ti,omap4-hsmmc" },
1929         { .compatible = "ti,am33xx-hsmmc" },
1930         { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data },
1931         { }
1932 };
1933 #endif
1934
1935 U_BOOT_DRIVER(omap_hsmmc) = {
1936         .name   = "omap_hsmmc",
1937         .id     = UCLASS_MMC,
1938 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1939         .of_match = omap_hsmmc_ids,
1940         .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
1941         .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
1942 #endif
1943 #ifdef CONFIG_BLK
1944         .bind = omap_hsmmc_bind,
1945 #endif
1946         .ops = &omap_hsmmc_ops,
1947         .probe  = omap_hsmmc_probe,
1948         .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
1949         .flags  = DM_FLAG_PRE_RELOC,
1950 };
1951 #endif