3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
35 #include <asm/arch/mmc_host_def.h>
36 #if !defined(CONFIG_SOC_KEYSTONE)
38 #include <asm/arch/sys_proto.h>
40 #ifdef CONFIG_MMC_OMAP36XX_PINS
41 #include <asm/arch/mux.h>
45 DECLARE_GLOBAL_DATA_PTR;
47 /* simplify defines to OMAP_HSMMC_USE_GPIO */
48 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
49 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
50 #define OMAP_HSMMC_USE_GPIO
52 #undef OMAP_HSMMC_USE_GPIO
55 /* common definitions for all OMAPs */
56 #define SYSCTL_SRC (1 << 25)
57 #define SYSCTL_SRD (1 << 26)
59 struct omap_hsmmc_plat {
60 struct mmc_config cfg;
64 struct omap_hsmmc_data {
65 struct hsmmc *base_addr;
67 struct mmc_config cfg;
69 #ifdef OMAP_HSMMC_USE_GPIO
71 struct gpio_desc cd_gpio; /* Change Detect GPIO */
72 struct gpio_desc wp_gpio; /* Write Protect GPIO */
81 /* If we fail after 1 second wait, something is really bad */
82 #define MAX_RETRY_MS 1000
84 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
85 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
88 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
91 return dev_get_priv(mmc->dev);
93 return (struct omap_hsmmc_data *)mmc->priv;
96 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
99 struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
102 return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
106 #if defined(OMAP_HSMMC_USE_GPIO) && !defined(CONFIG_DM_MMC)
107 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
111 #ifndef CONFIG_DM_GPIO
112 if (!gpio_is_valid(gpio))
115 ret = gpio_request(gpio, label);
119 ret = gpio_direction_input(gpio);
127 static unsigned char mmc_board_init(struct mmc *mmc)
129 #if defined(CONFIG_OMAP34XX)
130 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
131 t2_t *t2_base = (t2_t *)T2_BASE;
132 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
134 #ifdef CONFIG_MMC_OMAP36XX_PINS
135 u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
138 pbias_lite = readl(&t2_base->pbias_lite);
139 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
140 #ifdef CONFIG_TARGET_OMAP3_CAIRO
141 /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
142 pbias_lite &= ~PBIASLITEVMODE0;
144 #ifdef CONFIG_MMC_OMAP36XX_PINS
145 if (get_cpu_family() == CPU_OMAP36XX) {
146 /* Disable extended drain IO before changing PBIAS */
147 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
148 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
151 writel(pbias_lite, &t2_base->pbias_lite);
153 writel(pbias_lite | PBIASLITEPWRDNZ1 |
154 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
155 &t2_base->pbias_lite);
157 #ifdef CONFIG_MMC_OMAP36XX_PINS
158 if (get_cpu_family() == CPU_OMAP36XX)
159 /* Enable extended drain IO after changing PBIAS */
161 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
162 OMAP34XX_CTRL_WKUP_CTRL);
164 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
167 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
170 /* Change from default of 52MHz to 26MHz if necessary */
171 if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
172 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
173 &t2_base->ctl_prog_io1);
175 writel(readl(&prcm_base->fclken1_core) |
176 EN_MMC1 | EN_MMC2 | EN_MMC3,
177 &prcm_base->fclken1_core);
179 writel(readl(&prcm_base->iclken1_core) |
180 EN_MMC1 | EN_MMC2 | EN_MMC3,
181 &prcm_base->iclken1_core);
184 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
185 /* PBIAS config needed for MMC1 only */
186 if (mmc_get_blk_desc(mmc)->devnum == 0)
187 vmmc_pbias_config(LDO_VOLT_3V0);
193 void mmc_init_stream(struct hsmmc *mmc_base)
197 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
199 writel(MMC_CMD0, &mmc_base->cmd);
200 start = get_timer(0);
201 while (!(readl(&mmc_base->stat) & CC_MASK)) {
202 if (get_timer(0) - start > MAX_RETRY_MS) {
203 printf("%s: timedout waiting for cc!\n", __func__);
207 writel(CC_MASK, &mmc_base->stat)
209 writel(MMC_CMD0, &mmc_base->cmd)
211 start = get_timer(0);
212 while (!(readl(&mmc_base->stat) & CC_MASK)) {
213 if (get_timer(0) - start > MAX_RETRY_MS) {
214 printf("%s: timedout waiting for cc2!\n", __func__);
218 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
221 static int omap_hsmmc_init_setup(struct mmc *mmc)
223 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
224 struct hsmmc *mmc_base;
225 unsigned int reg_val;
229 mmc_base = priv->base_addr;
232 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
233 &mmc_base->sysconfig);
234 start = get_timer(0);
235 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
236 if (get_timer(0) - start > MAX_RETRY_MS) {
237 printf("%s: timedout waiting for cc2!\n", __func__);
241 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
242 start = get_timer(0);
243 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
244 if (get_timer(0) - start > MAX_RETRY_MS) {
245 printf("%s: timedout waiting for softresetall!\n",
250 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
251 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
254 reg_val = readl(&mmc_base->con) & RESERVED_MASK;
256 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
257 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
258 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
261 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
262 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
263 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
264 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
265 start = get_timer(0);
266 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
267 if (get_timer(0) - start > MAX_RETRY_MS) {
268 printf("%s: timedout waiting for ics!\n", __func__);
272 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
274 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
276 writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
277 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
280 mmc_init_stream(mmc_base);
286 * MMC controller internal finite state machine reset
288 * Used to reset command or data internal state machines, using respectively
289 * SRC or SRD bit of SYSCTL register
291 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
295 mmc_reg_out(&mmc_base->sysctl, bit, bit);
298 * CMD(DAT) lines reset procedures are slightly different
299 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
300 * According to OMAP3 TRM:
301 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
303 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
304 * procedure steps must be as follows:
305 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
306 * MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
307 * 2. Poll the SRC(SRD) bit until it is set to 0x1.
308 * 3. Wait until the SRC (SRD) bit returns to 0x0
309 * (reset procedure is completed).
311 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
312 defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
313 if (!(readl(&mmc_base->sysctl) & bit)) {
314 start = get_timer(0);
315 while (!(readl(&mmc_base->sysctl) & bit)) {
316 if (get_timer(0) - start > MAX_RETRY_MS)
321 start = get_timer(0);
322 while ((readl(&mmc_base->sysctl) & bit) != 0) {
323 if (get_timer(0) - start > MAX_RETRY_MS) {
324 printf("%s: timedout waiting for sysctl %x to clear\n",
331 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
332 struct mmc_data *data)
334 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
335 struct hsmmc *mmc_base;
336 unsigned int flags, mmc_stat;
339 mmc_base = priv->base_addr;
340 start = get_timer(0);
341 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
342 if (get_timer(0) - start > MAX_RETRY_MS) {
343 printf("%s: timedout waiting on cmd inhibit to clear\n",
348 writel(0xFFFFFFFF, &mmc_base->stat);
349 start = get_timer(0);
350 while (readl(&mmc_base->stat)) {
351 if (get_timer(0) - start > MAX_RETRY_MS) {
352 printf("%s: timedout waiting for STAT (%x) to clear\n",
353 __func__, readl(&mmc_base->stat));
359 * CMDIDX[13:8] : Command index
360 * DATAPRNT[5] : Data Present Select
361 * ENCMDIDX[4] : Command Index Check Enable
362 * ENCMDCRC[3] : Command CRC Check Enable
367 * 11 = Length 48 Check busy after response
369 /* Delay added before checking the status of frq change
370 * retry not supported by mmc.c(core file)
372 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
373 udelay(50000); /* wait 50 ms */
375 if (!(cmd->resp_type & MMC_RSP_PRESENT))
377 else if (cmd->resp_type & MMC_RSP_136)
378 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
379 else if (cmd->resp_type & MMC_RSP_BUSY)
380 flags = RSP_TYPE_LGHT48B;
382 flags = RSP_TYPE_LGHT48;
384 /* enable default flags */
385 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
386 MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
388 if (cmd->resp_type & MMC_RSP_CRC)
390 if (cmd->resp_type & MMC_RSP_OPCODE)
394 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
395 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
396 flags |= (MSBS_MULTIBLK | BCE_ENABLE);
397 data->blocksize = 512;
398 writel(data->blocksize | (data->blocks << 16),
401 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
403 if (data->flags & MMC_DATA_READ)
404 flags |= (DP_DATA | DDIR_READ);
406 flags |= (DP_DATA | DDIR_WRITE);
409 writel(cmd->cmdarg, &mmc_base->arg);
410 udelay(20); /* To fix "No status update" error on eMMC */
411 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
413 start = get_timer(0);
415 mmc_stat = readl(&mmc_base->stat);
416 if (get_timer(0) - start > MAX_RETRY_MS) {
417 printf("%s : timeout: No status update\n", __func__);
422 if ((mmc_stat & IE_CTO) != 0) {
423 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
425 } else if ((mmc_stat & ERRI_MASK) != 0)
428 if (mmc_stat & CC_MASK) {
429 writel(CC_MASK, &mmc_base->stat);
430 if (cmd->resp_type & MMC_RSP_PRESENT) {
431 if (cmd->resp_type & MMC_RSP_136) {
432 /* response type 2 */
433 cmd->response[3] = readl(&mmc_base->rsp10);
434 cmd->response[2] = readl(&mmc_base->rsp32);
435 cmd->response[1] = readl(&mmc_base->rsp54);
436 cmd->response[0] = readl(&mmc_base->rsp76);
438 /* response types 1, 1b, 3, 4, 5, 6 */
439 cmd->response[0] = readl(&mmc_base->rsp10);
443 if (data && (data->flags & MMC_DATA_READ)) {
444 mmc_read_data(mmc_base, data->dest,
445 data->blocksize * data->blocks);
446 } else if (data && (data->flags & MMC_DATA_WRITE)) {
447 mmc_write_data(mmc_base, data->src,
448 data->blocksize * data->blocks);
453 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
455 unsigned int *output_buf = (unsigned int *)buf;
456 unsigned int mmc_stat;
462 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
466 ulong start = get_timer(0);
468 mmc_stat = readl(&mmc_base->stat);
469 if (get_timer(0) - start > MAX_RETRY_MS) {
470 printf("%s: timedout waiting for status!\n",
474 } while (mmc_stat == 0);
476 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
477 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
479 if ((mmc_stat & ERRI_MASK) != 0)
482 if (mmc_stat & BRR_MASK) {
485 writel(readl(&mmc_base->stat) | BRR_MASK,
487 for (k = 0; k < count; k++) {
488 *output_buf = readl(&mmc_base->data);
494 if (mmc_stat & BWR_MASK)
495 writel(readl(&mmc_base->stat) | BWR_MASK,
498 if (mmc_stat & TC_MASK) {
499 writel(readl(&mmc_base->stat) | TC_MASK,
507 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
510 unsigned int *input_buf = (unsigned int *)buf;
511 unsigned int mmc_stat;
517 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
521 ulong start = get_timer(0);
523 mmc_stat = readl(&mmc_base->stat);
524 if (get_timer(0) - start > MAX_RETRY_MS) {
525 printf("%s: timedout waiting for status!\n",
529 } while (mmc_stat == 0);
531 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
532 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
534 if ((mmc_stat & ERRI_MASK) != 0)
537 if (mmc_stat & BWR_MASK) {
540 writel(readl(&mmc_base->stat) | BWR_MASK,
542 for (k = 0; k < count; k++) {
543 writel(*input_buf, &mmc_base->data);
549 if (mmc_stat & BRR_MASK)
550 writel(readl(&mmc_base->stat) | BRR_MASK,
553 if (mmc_stat & TC_MASK) {
554 writel(readl(&mmc_base->stat) | TC_MASK,
562 static int omap_hsmmc_set_ios(struct mmc *mmc)
564 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
565 struct hsmmc *mmc_base;
566 unsigned int dsor = 0;
569 mmc_base = priv->base_addr;
570 /* configue bus width */
571 switch (mmc->bus_width) {
573 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
578 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
580 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
586 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
588 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
593 /* configure clock with 96Mhz system clock.
595 if (mmc->clock != 0) {
596 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
597 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
601 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
602 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
604 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
605 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
607 start = get_timer(0);
608 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
609 if (get_timer(0) - start > MAX_RETRY_MS) {
610 printf("%s: timedout waiting for ics!\n", __func__);
614 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
619 #ifdef OMAP_HSMMC_USE_GPIO
621 static int omap_hsmmc_getcd(struct mmc *mmc)
623 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
626 value = dm_gpio_get_value(&priv->cd_gpio);
627 /* if no CD return as 1 */
631 if (priv->cd_inverted)
636 static int omap_hsmmc_getwp(struct mmc *mmc)
638 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
641 value = dm_gpio_get_value(&priv->wp_gpio);
642 /* if no WP return as 0 */
648 static int omap_hsmmc_getcd(struct mmc *mmc)
650 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
653 /* if no CD return as 1 */
654 cd_gpio = priv->cd_gpio;
658 /* NOTE: assumes card detect signal is active-low */
659 return !gpio_get_value(cd_gpio);
662 static int omap_hsmmc_getwp(struct mmc *mmc)
664 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
667 /* if no WP return as 0 */
668 wp_gpio = priv->wp_gpio;
672 /* NOTE: assumes write protect signal is active-high */
673 return gpio_get_value(wp_gpio);
678 static const struct mmc_ops omap_hsmmc_ops = {
679 .send_cmd = omap_hsmmc_send_cmd,
680 .set_ios = omap_hsmmc_set_ios,
681 .init = omap_hsmmc_init_setup,
682 #ifdef OMAP_HSMMC_USE_GPIO
683 .getcd = omap_hsmmc_getcd,
684 .getwp = omap_hsmmc_getwp,
688 #ifndef CONFIG_DM_MMC
689 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
693 struct omap_hsmmc_data *priv;
694 struct mmc_config *cfg;
697 priv = malloc(sizeof(*priv));
701 host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
705 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
707 #ifdef OMAP_HSMMC2_BASE
709 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
710 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
711 defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
712 defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
713 defined(CONFIG_HSMMC2_8BIT)
714 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
715 host_caps_val |= MMC_MODE_8BIT;
719 #ifdef OMAP_HSMMC3_BASE
721 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
722 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
723 /* Enable 8-bit interface for eMMC on DRA7XX */
724 host_caps_val |= MMC_MODE_8BIT;
729 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
732 #ifdef OMAP_HSMMC_USE_GPIO
733 /* on error gpio values are set to -1, which is what we want */
734 priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
735 priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
740 cfg->name = "OMAP SD/MMC";
741 cfg->ops = &omap_hsmmc_ops;
743 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
744 cfg->host_caps = host_caps_val & ~host_caps_mask;
751 if (cfg->host_caps & MMC_MODE_HS) {
752 if (cfg->host_caps & MMC_MODE_HS_52MHz)
753 cfg->f_max = 52000000;
755 cfg->f_max = 26000000;
757 cfg->f_max = 20000000;
760 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
762 #if defined(CONFIG_OMAP34XX)
764 * Silicon revs 2.1 and older do not support multiblock transfers.
766 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
769 mmc = mmc_create(cfg, priv);
776 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
778 struct omap_hsmmc_data *priv = dev_get_priv(dev);
779 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
780 struct mmc_config *cfg = &plat->cfg;
781 const void *fdt = gd->fdt_blob;
782 int node = dev_of_offset(dev);
785 priv->base_addr = map_physmem(dev_get_addr(dev), sizeof(struct hsmmc *),
788 cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
789 val = fdtdec_get_int(fdt, node, "bus-width", -1);
791 printf("error: bus-width property missing\n");
797 cfg->host_caps |= MMC_MODE_8BIT;
799 cfg->host_caps |= MMC_MODE_4BIT;
802 printf("error: invalid bus-width property\n");
807 cfg->f_max = fdtdec_get_int(fdt, node, "max-frequency", 52000000);
808 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
809 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
811 #ifdef OMAP_HSMMC_USE_GPIO
812 priv->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted");
820 static int omap_hsmmc_bind(struct udevice *dev)
822 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
824 return mmc_bind(dev, &plat->mmc, &plat->cfg);
827 static int omap_hsmmc_probe(struct udevice *dev)
829 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
830 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
831 struct omap_hsmmc_data *priv = dev_get_priv(dev);
832 struct mmc_config *cfg = &plat->cfg;
835 cfg->name = "OMAP SD/MMC";
836 cfg->ops = &omap_hsmmc_ops;
841 mmc = mmc_create(cfg, priv);
846 #ifdef OMAP_HSMMC_USE_GPIO
847 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
848 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
857 static const struct udevice_id omap_hsmmc_ids[] = {
858 { .compatible = "ti,omap3-hsmmc" },
859 { .compatible = "ti,omap4-hsmmc" },
860 { .compatible = "ti,am33xx-hsmmc" },
864 U_BOOT_DRIVER(omap_hsmmc) = {
865 .name = "omap_hsmmc",
867 .of_match = omap_hsmmc_ids,
868 .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
870 .bind = omap_hsmmc_bind,
872 .probe = omap_hsmmc_probe,
873 .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
874 .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),