3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/arch/mmc_host_def.h>
34 #include <asm/arch/sys_proto.h>
36 /* If we fail after 1 second wait, something is really bad */
37 #define MAX_RETRY_MS 1000
39 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
40 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
42 static struct mmc hsmmc_dev[2];
44 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
45 static void omap4_vmmc_pbias_config(struct mmc *mmc)
48 struct omap4_sys_ctrl_regs *const ctrl =
49 (struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
52 value = readl(&ctrl->control_pbiaslite);
53 value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
54 writel(value, &ctrl->control_pbiaslite);
56 twl6030_power_mmc_init();
57 value = readl(&ctrl->control_pbiaslite);
58 value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
59 writel(value, &ctrl->control_pbiaslite);
63 unsigned char mmc_board_init(struct mmc *mmc)
65 #if defined(CONFIG_OMAP34XX)
66 t2_t *t2_base = (t2_t *)T2_BASE;
67 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
70 pbias_lite = readl(&t2_base->pbias_lite);
71 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
72 writel(pbias_lite, &t2_base->pbias_lite);
74 #if defined(CONFIG_TWL4030_POWER)
75 twl4030_power_mmc_init();
76 mdelay(100); /* ramp-up delay from Linux code */
78 #if defined(CONFIG_OMAP34XX)
79 writel(pbias_lite | PBIASLITEPWRDNZ1 |
80 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
81 &t2_base->pbias_lite);
83 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
86 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
89 writel(readl(&prcm_base->fclken1_core) |
90 EN_MMC1 | EN_MMC2 | EN_MMC3,
91 &prcm_base->fclken1_core);
93 writel(readl(&prcm_base->iclken1_core) |
94 EN_MMC1 | EN_MMC2 | EN_MMC3,
95 &prcm_base->iclken1_core);
98 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
99 /* PBIAS config needed for MMC1 only */
100 if (mmc->block_dev.dev == 0)
101 omap4_vmmc_pbias_config(mmc);
107 void mmc_init_stream(struct hsmmc *mmc_base)
111 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
113 writel(MMC_CMD0, &mmc_base->cmd);
114 start = get_timer(0);
115 while (!(readl(&mmc_base->stat) & CC_MASK)) {
116 if (get_timer(0) - start > MAX_RETRY_MS) {
117 printf("%s: timedout waiting for cc!\n", __func__);
121 writel(CC_MASK, &mmc_base->stat)
123 writel(MMC_CMD0, &mmc_base->cmd)
125 start = get_timer(0);
126 while (!(readl(&mmc_base->stat) & CC_MASK)) {
127 if (get_timer(0) - start > MAX_RETRY_MS) {
128 printf("%s: timedout waiting for cc2!\n", __func__);
132 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
136 static int mmc_init_setup(struct mmc *mmc)
138 struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
139 unsigned int reg_val;
145 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
146 &mmc_base->sysconfig);
147 start = get_timer(0);
148 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
149 if (get_timer(0) - start > MAX_RETRY_MS) {
150 printf("%s: timedout waiting for cc2!\n", __func__);
154 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
155 start = get_timer(0);
156 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
157 if (get_timer(0) - start > MAX_RETRY_MS) {
158 printf("%s: timedout waiting for softresetall!\n",
163 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
164 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
167 reg_val = readl(&mmc_base->con) & RESERVED_MASK;
169 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
170 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
171 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
174 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
175 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
176 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
177 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
178 start = get_timer(0);
179 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
180 if (get_timer(0) - start > MAX_RETRY_MS) {
181 printf("%s: timedout waiting for ics!\n", __func__);
185 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
187 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
189 writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
190 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
193 mmc_init_stream(mmc_base);
199 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
200 struct mmc_data *data)
202 struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
203 unsigned int flags, mmc_stat;
206 start = get_timer(0);
207 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
208 if (get_timer(0) - start > MAX_RETRY_MS) {
209 printf("%s: timedout waiting on cmd inhibit to clear\n",
214 writel(0xFFFFFFFF, &mmc_base->stat);
215 start = get_timer(0);
216 while (readl(&mmc_base->stat)) {
217 if (get_timer(0) - start > MAX_RETRY_MS) {
218 printf("%s: timedout waiting for STAT (%x) to clear\n",
219 __func__, readl(&mmc_base->stat));
225 * CMDIDX[13:8] : Command index
226 * DATAPRNT[5] : Data Present Select
227 * ENCMDIDX[4] : Command Index Check Enable
228 * ENCMDCRC[3] : Command CRC Check Enable
233 * 11 = Length 48 Check busy after response
235 /* Delay added before checking the status of frq change
236 * retry not supported by mmc.c(core file)
238 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
239 udelay(50000); /* wait 50 ms */
241 if (!(cmd->resp_type & MMC_RSP_PRESENT))
243 else if (cmd->resp_type & MMC_RSP_136)
244 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
245 else if (cmd->resp_type & MMC_RSP_BUSY)
246 flags = RSP_TYPE_LGHT48B;
248 flags = RSP_TYPE_LGHT48;
250 /* enable default flags */
251 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
252 MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
254 if (cmd->resp_type & MMC_RSP_CRC)
256 if (cmd->resp_type & MMC_RSP_OPCODE)
260 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
261 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
262 flags |= (MSBS_MULTIBLK | BCE_ENABLE);
263 data->blocksize = 512;
264 writel(data->blocksize | (data->blocks << 16),
267 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
269 if (data->flags & MMC_DATA_READ)
270 flags |= (DP_DATA | DDIR_READ);
272 flags |= (DP_DATA | DDIR_WRITE);
275 writel(cmd->cmdarg, &mmc_base->arg);
276 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
278 start = get_timer(0);
280 mmc_stat = readl(&mmc_base->stat);
281 if (get_timer(0) - start > MAX_RETRY_MS) {
282 printf("%s : timeout: No status update\n", __func__);
287 if ((mmc_stat & IE_CTO) != 0)
289 else if ((mmc_stat & ERRI_MASK) != 0)
292 if (mmc_stat & CC_MASK) {
293 writel(CC_MASK, &mmc_base->stat);
294 if (cmd->resp_type & MMC_RSP_PRESENT) {
295 if (cmd->resp_type & MMC_RSP_136) {
296 /* response type 2 */
297 cmd->response[3] = readl(&mmc_base->rsp10);
298 cmd->response[2] = readl(&mmc_base->rsp32);
299 cmd->response[1] = readl(&mmc_base->rsp54);
300 cmd->response[0] = readl(&mmc_base->rsp76);
302 /* response types 1, 1b, 3, 4, 5, 6 */
303 cmd->response[0] = readl(&mmc_base->rsp10);
307 if (data && (data->flags & MMC_DATA_READ)) {
308 mmc_read_data(mmc_base, data->dest,
309 data->blocksize * data->blocks);
310 } else if (data && (data->flags & MMC_DATA_WRITE)) {
311 mmc_write_data(mmc_base, data->src,
312 data->blocksize * data->blocks);
317 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
319 unsigned int *output_buf = (unsigned int *)buf;
320 unsigned int mmc_stat;
326 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
330 ulong start = get_timer(0);
332 mmc_stat = readl(&mmc_base->stat);
333 if (get_timer(0) - start > MAX_RETRY_MS) {
334 printf("%s: timedout waiting for status!\n",
338 } while (mmc_stat == 0);
340 if ((mmc_stat & ERRI_MASK) != 0)
343 if (mmc_stat & BRR_MASK) {
346 writel(readl(&mmc_base->stat) | BRR_MASK,
348 for (k = 0; k < count; k++) {
349 *output_buf = readl(&mmc_base->data);
355 if (mmc_stat & BWR_MASK)
356 writel(readl(&mmc_base->stat) | BWR_MASK,
359 if (mmc_stat & TC_MASK) {
360 writel(readl(&mmc_base->stat) | TC_MASK,
368 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
371 unsigned int *input_buf = (unsigned int *)buf;
372 unsigned int mmc_stat;
378 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
382 ulong start = get_timer(0);
384 mmc_stat = readl(&mmc_base->stat);
385 if (get_timer(0) - start > MAX_RETRY_MS) {
386 printf("%s: timedout waiting for status!\n",
390 } while (mmc_stat == 0);
392 if ((mmc_stat & ERRI_MASK) != 0)
395 if (mmc_stat & BWR_MASK) {
398 writel(readl(&mmc_base->stat) | BWR_MASK,
400 for (k = 0; k < count; k++) {
401 writel(*input_buf, &mmc_base->data);
407 if (mmc_stat & BRR_MASK)
408 writel(readl(&mmc_base->stat) | BRR_MASK,
411 if (mmc_stat & TC_MASK) {
412 writel(readl(&mmc_base->stat) | TC_MASK,
420 static void mmc_set_ios(struct mmc *mmc)
422 struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
423 unsigned int dsor = 0;
426 /* configue bus width */
427 switch (mmc->bus_width) {
429 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
434 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
436 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
442 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
444 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
449 /* configure clock with 96Mhz system clock.
451 if (mmc->clock != 0) {
452 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
453 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
457 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
458 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
460 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
461 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
463 start = get_timer(0);
464 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
465 if (get_timer(0) - start > MAX_RETRY_MS) {
466 printf("%s: timedout waiting for ics!\n", __func__);
470 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
473 int omap_mmc_init(int dev_index)
477 mmc = &hsmmc_dev[dev_index];
479 sprintf(mmc->name, "OMAP SD/MMC");
480 mmc->send_cmd = mmc_send_cmd;
481 mmc->set_ios = mmc_set_ios;
482 mmc->init = mmc_init_setup;
487 mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
489 #ifdef OMAP_HSMMC2_BASE
491 mmc->priv = (struct hsmmc *)OMAP_HSMMC2_BASE;
494 #ifdef OMAP_HSMMC3_BASE
496 mmc->priv = (struct hsmmc *)OMAP_HSMMC3_BASE;
500 mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
503 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
504 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
508 mmc->f_max = 52000000;
512 #if defined(CONFIG_OMAP34XX)
514 * Silicon revs 2.1 and older do not support multiblock transfers.
516 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))