3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
36 #include <asm/arch/mmc_host_def.h>
37 #ifdef CONFIG_OMAP54XX
38 #include <asm/arch/mux_dra7xx.h>
39 #include <asm/arch/dra7xx_iodelay.h>
41 #if !defined(CONFIG_SOC_KEYSTONE)
43 #include <asm/arch/sys_proto.h>
45 #ifdef CONFIG_MMC_OMAP36XX_PINS
46 #include <asm/arch/mux.h>
49 #include <power/regulator.h>
51 DECLARE_GLOBAL_DATA_PTR;
53 /* simplify defines to OMAP_HSMMC_USE_GPIO */
54 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
55 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
56 #define OMAP_HSMMC_USE_GPIO
58 #undef OMAP_HSMMC_USE_GPIO
61 /* common definitions for all OMAPs */
62 #define SYSCTL_SRC (1 << 25)
63 #define SYSCTL_SRD (1 << 26)
65 #ifdef CONFIG_IODELAY_RECALIBRATION
66 struct omap_hsmmc_pinctrl_state {
67 struct pad_conf_entry *padconf;
69 struct iodelay_cfg_entry *iodelay;
74 struct omap_hsmmc_data {
75 struct hsmmc *base_addr;
76 #if !CONFIG_IS_ENABLED(DM_MMC)
77 struct mmc_config cfg;
81 #ifdef OMAP_HSMMC_USE_GPIO
82 #if CONFIG_IS_ENABLED(DM_MMC)
83 struct gpio_desc cd_gpio; /* Change Detect GPIO */
84 struct gpio_desc wp_gpio; /* Write Protect GPIO */
91 #if CONFIG_IS_ENABLED(DM_MMC)
96 #ifndef CONFIG_OMAP34XX
97 struct omap_hsmmc_adma_desc *adma_desc_table;
101 #ifdef CONFIG_IODELAY_RECALIBRATION
102 struct omap_hsmmc_pinctrl_state *default_pinctrl_state;
103 struct omap_hsmmc_pinctrl_state *hs_pinctrl_state;
104 struct omap_hsmmc_pinctrl_state *hs200_1_8v_pinctrl_state;
105 struct omap_hsmmc_pinctrl_state *ddr_1_8v_pinctrl_state;
106 struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state;
107 struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state;
108 struct omap_hsmmc_pinctrl_state *ddr50_pinctrl_state;
109 struct omap_hsmmc_pinctrl_state *sdr50_pinctrl_state;
110 struct omap_hsmmc_pinctrl_state *sdr104_pinctrl_state;
114 struct omap_mmc_of_data {
118 #ifndef CONFIG_OMAP34XX
119 struct omap_hsmmc_adma_desc {
126 #define ADMA_MAX_LEN 63488
128 /* Decriptor table defines */
129 #define ADMA_DESC_ATTR_VALID BIT(0)
130 #define ADMA_DESC_ATTR_END BIT(1)
131 #define ADMA_DESC_ATTR_INT BIT(2)
132 #define ADMA_DESC_ATTR_ACT1 BIT(4)
133 #define ADMA_DESC_ATTR_ACT2 BIT(5)
135 #define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
136 #define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
139 /* If we fail after 1 second wait, something is really bad */
140 #define MAX_RETRY_MS 1000
141 #define MMC_TIMEOUT_MS 20
143 /* DMA transfers can take a long time if a lot a data is transferred.
144 * The timeout must take in account the amount of data. Let's assume
145 * that the time will never exceed 333 ms per MB (in other word we assume
146 * that the bandwidth is always above 3MB/s).
148 #define DMA_TIMEOUT_PER_MB 333
149 #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(0)
150 #define OMAP_HSMMC_NO_1_8_V BIT(1)
151 #define OMAP_HSMMC_USE_ADMA BIT(2)
152 #define OMAP_HSMMC_REQUIRE_IODELAY BIT(3)
154 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
155 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
157 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
158 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
159 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit);
161 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
163 #if CONFIG_IS_ENABLED(DM_MMC)
164 return dev_get_priv(mmc->dev);
166 return (struct omap_hsmmc_data *)mmc->priv;
169 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
171 #if CONFIG_IS_ENABLED(DM_MMC)
172 struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
175 return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
179 #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
180 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
184 #ifndef CONFIG_DM_GPIO
185 if (!gpio_is_valid(gpio))
188 ret = gpio_request(gpio, label);
192 ret = gpio_direction_input(gpio);
200 static unsigned char mmc_board_init(struct mmc *mmc)
202 #if defined(CONFIG_OMAP34XX)
203 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
204 t2_t *t2_base = (t2_t *)T2_BASE;
205 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
207 #ifdef CONFIG_MMC_OMAP36XX_PINS
208 u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
211 pbias_lite = readl(&t2_base->pbias_lite);
212 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
213 #ifdef CONFIG_TARGET_OMAP3_CAIRO
214 /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
215 pbias_lite &= ~PBIASLITEVMODE0;
217 #ifdef CONFIG_MMC_OMAP36XX_PINS
218 if (get_cpu_family() == CPU_OMAP36XX) {
219 /* Disable extended drain IO before changing PBIAS */
220 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
221 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
224 writel(pbias_lite, &t2_base->pbias_lite);
226 writel(pbias_lite | PBIASLITEPWRDNZ1 |
227 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
228 &t2_base->pbias_lite);
230 #ifdef CONFIG_MMC_OMAP36XX_PINS
231 if (get_cpu_family() == CPU_OMAP36XX)
232 /* Enable extended drain IO after changing PBIAS */
234 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
235 OMAP34XX_CTRL_WKUP_CTRL);
237 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
240 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
243 /* Change from default of 52MHz to 26MHz if necessary */
244 if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
245 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
246 &t2_base->ctl_prog_io1);
248 writel(readl(&prcm_base->fclken1_core) |
249 EN_MMC1 | EN_MMC2 | EN_MMC3,
250 &prcm_base->fclken1_core);
252 writel(readl(&prcm_base->iclken1_core) |
253 EN_MMC1 | EN_MMC2 | EN_MMC3,
254 &prcm_base->iclken1_core);
257 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
258 /* PBIAS config needed for MMC1 only */
259 if (mmc_get_blk_desc(mmc)->devnum == 0)
260 vmmc_pbias_config(LDO_VOLT_3V0);
266 void mmc_init_stream(struct hsmmc *mmc_base)
270 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
272 writel(MMC_CMD0, &mmc_base->cmd);
273 start = get_timer(0);
274 while (!(readl(&mmc_base->stat) & CC_MASK)) {
275 if (get_timer(0) - start > MAX_RETRY_MS) {
276 printf("%s: timedout waiting for cc!\n", __func__);
280 writel(CC_MASK, &mmc_base->stat)
282 writel(MMC_CMD0, &mmc_base->cmd)
284 start = get_timer(0);
285 while (!(readl(&mmc_base->stat) & CC_MASK)) {
286 if (get_timer(0) - start > MAX_RETRY_MS) {
287 printf("%s: timedout waiting for cc2!\n", __func__);
291 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
294 #if CONFIG_IS_ENABLED(DM_MMC)
295 #ifdef CONFIG_IODELAY_RECALIBRATION
296 static void omap_hsmmc_io_recalibrate(struct mmc *mmc)
298 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
299 struct omap_hsmmc_pinctrl_state *pinctrl_state;
301 switch (priv->mode) {
303 pinctrl_state = priv->hs200_1_8v_pinctrl_state;
306 pinctrl_state = priv->sdr104_pinctrl_state;
309 pinctrl_state = priv->sdr50_pinctrl_state;
312 pinctrl_state = priv->ddr50_pinctrl_state;
315 pinctrl_state = priv->sdr25_pinctrl_state;
318 pinctrl_state = priv->sdr12_pinctrl_state;
323 pinctrl_state = priv->hs_pinctrl_state;
326 pinctrl_state = priv->ddr_1_8v_pinctrl_state;
328 pinctrl_state = priv->default_pinctrl_state;
333 pinctrl_state = priv->default_pinctrl_state;
335 if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) {
336 if (pinctrl_state->iodelay)
337 late_recalibrate_iodelay(pinctrl_state->padconf,
338 pinctrl_state->npads,
339 pinctrl_state->iodelay,
340 pinctrl_state->niodelays);
342 do_set_mux32((*ctrl)->control_padconf_core_base,
343 pinctrl_state->padconf,
344 pinctrl_state->npads);
348 static void omap_hsmmc_set_timing(struct mmc *mmc)
351 struct hsmmc *mmc_base;
352 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
354 mmc_base = priv->base_addr;
356 omap_hsmmc_stop_clock(mmc_base);
357 val = readl(&mmc_base->ac12);
358 val &= ~AC12_UHSMC_MASK;
359 priv->mode = mmc->selected_mode;
361 if (mmc_is_mode_ddr(priv->mode))
362 writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
364 writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
366 switch (priv->mode) {
369 val |= AC12_UHSMC_SDR104;
372 val |= AC12_UHSMC_SDR50;
376 val |= AC12_UHSMC_DDR50;
381 val |= AC12_UHSMC_SDR25;
387 val |= AC12_UHSMC_SDR12;
390 val |= AC12_UHSMC_RES;
393 writel(val, &mmc_base->ac12);
395 #ifdef CONFIG_IODELAY_RECALIBRATION
396 omap_hsmmc_io_recalibrate(mmc);
398 omap_hsmmc_start_clock(mmc_base);
401 static void omap_hsmmc_conf_bus_power(struct mmc *mmc)
403 struct hsmmc *mmc_base;
404 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
407 mmc_base = priv->base_addr;
409 val = readl(&mmc_base->hctl) & ~SDVS_MASK;
423 writel(val, &mmc_base->hctl);
426 static void omap_hsmmc_set_capabilities(struct mmc *mmc)
428 struct hsmmc *mmc_base;
429 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
432 mmc_base = priv->base_addr;
433 val = readl(&mmc_base->capa);
435 if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
436 val |= (VS30_3V0SUP | VS18_1V8SUP);
438 } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
448 writel(val, &mmc_base->capa);
451 #ifdef MMC_SUPPORTS_TUNING
452 static void omap_hsmmc_disable_tuning(struct mmc *mmc)
454 struct hsmmc *mmc_base;
455 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
458 mmc_base = priv->base_addr;
459 val = readl(&mmc_base->ac12);
460 val &= ~(AC12_SCLK_SEL);
461 writel(val, &mmc_base->ac12);
463 val = readl(&mmc_base->dll);
464 val &= ~(DLL_FORCE_VALUE | DLL_SWT);
465 writel(val, &mmc_base->dll);
468 static void omap_hsmmc_set_dll(struct mmc *mmc, int count)
471 struct hsmmc *mmc_base;
472 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
475 mmc_base = priv->base_addr;
476 val = readl(&mmc_base->dll);
477 val |= DLL_FORCE_VALUE;
478 val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT);
479 val |= (count << DLL_FORCE_SR_C_SHIFT);
480 writel(val, &mmc_base->dll);
483 writel(val, &mmc_base->dll);
484 for (i = 0; i < 1000; i++) {
485 if (readl(&mmc_base->dll) & DLL_CALIB)
489 writel(val, &mmc_base->dll);
492 static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode)
494 struct omap_hsmmc_data *priv = dev_get_priv(dev);
495 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
496 struct mmc *mmc = upriv->mmc;
497 struct hsmmc *mmc_base;
499 u8 cur_match, prev_match = 0;
502 u32 start_window = 0, max_window = 0;
503 u32 length = 0, max_len = 0;
505 mmc_base = priv->base_addr;
506 val = readl(&mmc_base->capa2);
508 /* clock tuning is not needed for upto 52MHz */
509 if (!((mmc->selected_mode == MMC_HS_200) ||
510 (mmc->selected_mode == UHS_SDR104) ||
511 ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50))))
514 val = readl(&mmc_base->dll);
516 writel(val, &mmc_base->dll);
517 while (phase_delay <= MAX_PHASE_DELAY) {
518 omap_hsmmc_set_dll(mmc, phase_delay);
520 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
526 start_window = phase_delay;
531 if (length > max_len) {
532 max_window = start_window;
536 prev_match = cur_match;
545 val = readl(&mmc_base->ac12);
546 if (!(val & AC12_SCLK_SEL)) {
551 phase_delay = max_window + 4 * ((3 * max_len) >> 2);
552 omap_hsmmc_set_dll(mmc, phase_delay);
554 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
555 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
561 omap_hsmmc_disable_tuning(mmc);
562 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
563 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
569 static void omap_hsmmc_send_init_stream(struct udevice *dev)
571 struct omap_hsmmc_data *priv = dev_get_priv(dev);
572 struct hsmmc *mmc_base = priv->base_addr;
574 mmc_init_stream(mmc_base);
578 static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
580 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
581 struct hsmmc *mmc_base = priv->base_addr;
582 u32 irq_mask = INT_EN_MASK;
585 * TODO: Errata i802 indicates only DCRC interrupts can occur during
586 * tuning procedure and DCRC should be disabled. But see occurences
587 * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These
588 * interrupts occur along with BRR, so the data is actually in the
589 * buffer. It has to be debugged why these interrutps occur
591 if (cmd && mmc_is_tuning_cmd(cmd->cmdidx))
592 irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC);
594 writel(irq_mask, &mmc_base->ie);
597 static int omap_hsmmc_init_setup(struct mmc *mmc)
599 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
600 struct hsmmc *mmc_base;
601 unsigned int reg_val;
605 mmc_base = priv->base_addr;
608 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
609 &mmc_base->sysconfig);
610 start = get_timer(0);
611 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
612 if (get_timer(0) - start > MAX_RETRY_MS) {
613 printf("%s: timedout waiting for cc2!\n", __func__);
617 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
618 start = get_timer(0);
619 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
620 if (get_timer(0) - start > MAX_RETRY_MS) {
621 printf("%s: timedout waiting for softresetall!\n",
626 #ifndef CONFIG_OMAP34XX
627 reg_val = readl(&mmc_base->hl_hwinfo);
628 if (reg_val & MADMA_EN)
629 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
632 #if CONFIG_IS_ENABLED(DM_MMC)
633 omap_hsmmc_set_capabilities(mmc);
634 omap_hsmmc_conf_bus_power(mmc);
636 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
637 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
641 reg_val = readl(&mmc_base->con) & RESERVED_MASK;
643 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
644 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
645 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
648 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
649 (ICE_STOP | DTO_15THDTO));
650 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
651 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
652 start = get_timer(0);
653 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
654 if (get_timer(0) - start > MAX_RETRY_MS) {
655 printf("%s: timedout waiting for ics!\n", __func__);
659 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
661 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
663 mmc_enable_irq(mmc, NULL);
665 #if !CONFIG_IS_ENABLED(DM_MMC)
666 mmc_init_stream(mmc_base);
673 * MMC controller internal finite state machine reset
675 * Used to reset command or data internal state machines, using respectively
676 * SRC or SRD bit of SYSCTL register
678 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
682 mmc_reg_out(&mmc_base->sysctl, bit, bit);
685 * CMD(DAT) lines reset procedures are slightly different
686 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
687 * According to OMAP3 TRM:
688 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
690 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
691 * procedure steps must be as follows:
692 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
693 * MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
694 * 2. Poll the SRC(SRD) bit until it is set to 0x1.
695 * 3. Wait until the SRC (SRD) bit returns to 0x0
696 * (reset procedure is completed).
698 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
699 defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
700 if (!(readl(&mmc_base->sysctl) & bit)) {
701 start = get_timer(0);
702 while (!(readl(&mmc_base->sysctl) & bit)) {
703 if (get_timer(0) - start > MMC_TIMEOUT_MS)
708 start = get_timer(0);
709 while ((readl(&mmc_base->sysctl) & bit) != 0) {
710 if (get_timer(0) - start > MAX_RETRY_MS) {
711 printf("%s: timedout waiting for sysctl %x to clear\n",
718 #ifndef CONFIG_OMAP34XX
719 static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
721 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
722 struct omap_hsmmc_adma_desc *desc;
725 desc = &priv->adma_desc_table[priv->desc_slot];
727 attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
731 attr |= ADMA_DESC_ATTR_END;
734 desc->addr = (u32)buf;
739 static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
740 struct mmc_data *data)
742 uint total_len = data->blocksize * data->blocks;
743 uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
744 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
749 priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
750 memalign(ARCH_DMA_MINALIGN, desc_count *
751 sizeof(struct omap_hsmmc_adma_desc));
753 if (data->flags & MMC_DATA_READ)
756 buf = (char *)data->src;
759 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
761 total_len -= ADMA_MAX_LEN;
764 omap_hsmmc_adma_desc(mmc, buf, total_len, true);
766 flush_dcache_range((long)priv->adma_desc_table,
767 (long)priv->adma_desc_table +
769 sizeof(struct omap_hsmmc_adma_desc),
773 static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
775 struct hsmmc *mmc_base;
776 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
780 mmc_base = priv->base_addr;
781 omap_hsmmc_prepare_adma_table(mmc, data);
783 if (data->flags & MMC_DATA_READ)
786 buf = (char *)data->src;
788 val = readl(&mmc_base->hctl);
790 writel(val, &mmc_base->hctl);
792 val = readl(&mmc_base->con);
794 writel(val, &mmc_base->con);
796 writel((u32)priv->adma_desc_table, &mmc_base->admasal);
798 flush_dcache_range((u32)buf,
800 ROUND(data->blocksize * data->blocks,
804 static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
806 struct hsmmc *mmc_base;
807 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
810 mmc_base = priv->base_addr;
812 val = readl(&mmc_base->con);
814 writel(val, &mmc_base->con);
816 val = readl(&mmc_base->hctl);
818 writel(val, &mmc_base->hctl);
820 kfree(priv->adma_desc_table);
823 #define omap_hsmmc_adma_desc
824 #define omap_hsmmc_prepare_adma_table
825 #define omap_hsmmc_prepare_data
826 #define omap_hsmmc_dma_cleanup
829 #if !CONFIG_IS_ENABLED(DM_MMC)
830 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
831 struct mmc_data *data)
833 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
835 static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
836 struct mmc_data *data)
838 struct omap_hsmmc_data *priv = dev_get_priv(dev);
839 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
840 struct mmc *mmc = upriv->mmc;
842 struct hsmmc *mmc_base;
843 unsigned int flags, mmc_stat;
846 mmc_base = priv->base_addr;
848 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
851 start = get_timer(0);
852 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
853 if (get_timer(0) - start > MAX_RETRY_MS) {
854 printf("%s: timedout waiting on cmd inhibit to clear\n",
859 writel(0xFFFFFFFF, &mmc_base->stat);
860 start = get_timer(0);
861 while (readl(&mmc_base->stat)) {
862 if (get_timer(0) - start > MAX_RETRY_MS) {
863 printf("%s: timedout waiting for STAT (%x) to clear\n",
864 __func__, readl(&mmc_base->stat));
870 * CMDIDX[13:8] : Command index
871 * DATAPRNT[5] : Data Present Select
872 * ENCMDIDX[4] : Command Index Check Enable
873 * ENCMDCRC[3] : Command CRC Check Enable
878 * 11 = Length 48 Check busy after response
880 /* Delay added before checking the status of frq change
881 * retry not supported by mmc.c(core file)
883 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
884 udelay(50000); /* wait 50 ms */
886 if (!(cmd->resp_type & MMC_RSP_PRESENT))
888 else if (cmd->resp_type & MMC_RSP_136)
889 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
890 else if (cmd->resp_type & MMC_RSP_BUSY)
891 flags = RSP_TYPE_LGHT48B;
893 flags = RSP_TYPE_LGHT48;
895 /* enable default flags */
896 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
898 flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
900 if (cmd->resp_type & MMC_RSP_CRC)
902 if (cmd->resp_type & MMC_RSP_OPCODE)
906 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
907 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
908 flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
909 data->blocksize = 512;
910 writel(data->blocksize | (data->blocks << 16),
913 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
915 if (data->flags & MMC_DATA_READ)
916 flags |= (DP_DATA | DDIR_READ);
918 flags |= (DP_DATA | DDIR_WRITE);
920 #ifndef CONFIG_OMAP34XX
921 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
922 !mmc_is_tuning_cmd(cmd->cmdidx)) {
923 omap_hsmmc_prepare_data(mmc, data);
929 mmc_enable_irq(mmc, cmd);
931 writel(cmd->cmdarg, &mmc_base->arg);
932 udelay(20); /* To fix "No status update" error on eMMC */
933 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
935 start = get_timer(0);
937 mmc_stat = readl(&mmc_base->stat);
938 if (get_timer(start) > MAX_RETRY_MS) {
939 printf("%s : timeout: No status update\n", __func__);
944 if ((mmc_stat & IE_CTO) != 0) {
945 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
947 } else if ((mmc_stat & ERRI_MASK) != 0)
950 if (mmc_stat & CC_MASK) {
951 writel(CC_MASK, &mmc_base->stat);
952 if (cmd->resp_type & MMC_RSP_PRESENT) {
953 if (cmd->resp_type & MMC_RSP_136) {
954 /* response type 2 */
955 cmd->response[3] = readl(&mmc_base->rsp10);
956 cmd->response[2] = readl(&mmc_base->rsp32);
957 cmd->response[1] = readl(&mmc_base->rsp54);
958 cmd->response[0] = readl(&mmc_base->rsp76);
960 /* response types 1, 1b, 3, 4, 5, 6 */
961 cmd->response[0] = readl(&mmc_base->rsp10);
965 #ifndef CONFIG_OMAP34XX
966 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
967 !mmc_is_tuning_cmd(cmd->cmdidx)) {
970 if (mmc_stat & IE_ADMAE) {
971 omap_hsmmc_dma_cleanup(mmc);
975 sz_mb = DIV_ROUND_UP(data->blocksize * data->blocks, 1 << 20);
976 timeout = sz_mb * DMA_TIMEOUT_PER_MB;
977 if (timeout < MAX_RETRY_MS)
978 timeout = MAX_RETRY_MS;
980 start = get_timer(0);
982 mmc_stat = readl(&mmc_base->stat);
983 if (mmc_stat & TC_MASK) {
984 writel(readl(&mmc_base->stat) | TC_MASK,
988 if (get_timer(start) > timeout) {
989 printf("%s : DMA timeout: No status update\n",
995 omap_hsmmc_dma_cleanup(mmc);
1000 if (data && (data->flags & MMC_DATA_READ)) {
1001 mmc_read_data(mmc_base, data->dest,
1002 data->blocksize * data->blocks);
1003 } else if (data && (data->flags & MMC_DATA_WRITE)) {
1004 mmc_write_data(mmc_base, data->src,
1005 data->blocksize * data->blocks);
1010 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
1012 unsigned int *output_buf = (unsigned int *)buf;
1013 unsigned int mmc_stat;
1019 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1023 ulong start = get_timer(0);
1025 mmc_stat = readl(&mmc_base->stat);
1026 if (get_timer(0) - start > MAX_RETRY_MS) {
1027 printf("%s: timedout waiting for status!\n",
1031 } while (mmc_stat == 0);
1033 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1034 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1036 if ((mmc_stat & ERRI_MASK) != 0)
1039 if (mmc_stat & BRR_MASK) {
1042 writel(readl(&mmc_base->stat) | BRR_MASK,
1044 for (k = 0; k < count; k++) {
1045 *output_buf = readl(&mmc_base->data);
1051 if (mmc_stat & BWR_MASK)
1052 writel(readl(&mmc_base->stat) | BWR_MASK,
1055 if (mmc_stat & TC_MASK) {
1056 writel(readl(&mmc_base->stat) | TC_MASK,
1064 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1067 unsigned int *input_buf = (unsigned int *)buf;
1068 unsigned int mmc_stat;
1072 * Start Polled Write
1074 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1078 ulong start = get_timer(0);
1080 mmc_stat = readl(&mmc_base->stat);
1081 if (get_timer(0) - start > MAX_RETRY_MS) {
1082 printf("%s: timedout waiting for status!\n",
1086 } while (mmc_stat == 0);
1088 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1089 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1091 if ((mmc_stat & ERRI_MASK) != 0)
1094 if (mmc_stat & BWR_MASK) {
1097 writel(readl(&mmc_base->stat) | BWR_MASK,
1099 for (k = 0; k < count; k++) {
1100 writel(*input_buf, &mmc_base->data);
1106 if (mmc_stat & BRR_MASK)
1107 writel(readl(&mmc_base->stat) | BRR_MASK,
1110 if (mmc_stat & TC_MASK) {
1111 writel(readl(&mmc_base->stat) | TC_MASK,
1119 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
1121 writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
1124 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
1126 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
1129 static void omap_hsmmc_set_clock(struct mmc *mmc)
1131 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1132 struct hsmmc *mmc_base;
1133 unsigned int dsor = 0;
1136 mmc_base = priv->base_addr;
1137 omap_hsmmc_stop_clock(mmc_base);
1139 /* TODO: Is setting DTO required here? */
1140 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
1141 (ICE_STOP | DTO_15THDTO));
1143 if (mmc->clock != 0) {
1144 dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
1145 if (dsor > CLKD_MAX)
1151 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
1152 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
1154 start = get_timer(0);
1155 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
1156 if (get_timer(0) - start > MAX_RETRY_MS) {
1157 printf("%s: timedout waiting for ics!\n", __func__);
1162 priv->clock = MMC_CLOCK_REFERENCE * 1000000 / dsor;
1163 mmc->clock = priv->clock;
1164 omap_hsmmc_start_clock(mmc_base);
1167 static void omap_hsmmc_set_bus_width(struct mmc *mmc)
1169 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1170 struct hsmmc *mmc_base;
1172 mmc_base = priv->base_addr;
1173 /* configue bus width */
1174 switch (mmc->bus_width) {
1176 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
1181 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1183 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
1189 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1191 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
1196 priv->bus_width = mmc->bus_width;
1199 #if !CONFIG_IS_ENABLED(DM_MMC)
1200 static int omap_hsmmc_set_ios(struct mmc *mmc)
1202 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1204 static int omap_hsmmc_set_ios(struct udevice *dev)
1206 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1207 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1208 struct mmc *mmc = upriv->mmc;
1211 if (priv->bus_width != mmc->bus_width)
1212 omap_hsmmc_set_bus_width(mmc);
1214 if (priv->clock != mmc->clock)
1215 omap_hsmmc_set_clock(mmc);
1217 #if CONFIG_IS_ENABLED(DM_MMC)
1218 if (priv->mode != mmc->selected_mode)
1219 omap_hsmmc_set_timing(mmc);
1224 #ifdef OMAP_HSMMC_USE_GPIO
1225 #if CONFIG_IS_ENABLED(DM_MMC)
1226 static int omap_hsmmc_getcd(struct udevice *dev)
1228 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1231 value = dm_gpio_get_value(&priv->cd_gpio);
1232 /* if no CD return as 1 */
1236 if (priv->cd_inverted)
1241 static int omap_hsmmc_getwp(struct udevice *dev)
1243 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1246 value = dm_gpio_get_value(&priv->wp_gpio);
1247 /* if no WP return as 0 */
1253 static int omap_hsmmc_getcd(struct mmc *mmc)
1255 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1258 /* if no CD return as 1 */
1259 cd_gpio = priv->cd_gpio;
1263 /* NOTE: assumes card detect signal is active-low */
1264 return !gpio_get_value(cd_gpio);
1267 static int omap_hsmmc_getwp(struct mmc *mmc)
1269 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1272 /* if no WP return as 0 */
1273 wp_gpio = priv->wp_gpio;
1277 /* NOTE: assumes write protect signal is active-high */
1278 return gpio_get_value(wp_gpio);
1283 #if CONFIG_IS_ENABLED(DM_MMC)
1284 static const struct dm_mmc_ops omap_hsmmc_ops = {
1285 .send_cmd = omap_hsmmc_send_cmd,
1286 .set_ios = omap_hsmmc_set_ios,
1287 #ifdef OMAP_HSMMC_USE_GPIO
1288 .get_cd = omap_hsmmc_getcd,
1289 .get_wp = omap_hsmmc_getwp,
1291 #ifdef MMC_SUPPORTS_TUNING
1292 .execute_tuning = omap_hsmmc_execute_tuning,
1294 .send_init_stream = omap_hsmmc_send_init_stream,
1297 static const struct mmc_ops omap_hsmmc_ops = {
1298 .send_cmd = omap_hsmmc_send_cmd,
1299 .set_ios = omap_hsmmc_set_ios,
1300 .init = omap_hsmmc_init_setup,
1301 #ifdef OMAP_HSMMC_USE_GPIO
1302 .getcd = omap_hsmmc_getcd,
1303 .getwp = omap_hsmmc_getwp,
1308 #if !CONFIG_IS_ENABLED(DM_MMC)
1309 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
1313 struct omap_hsmmc_data *priv;
1314 struct mmc_config *cfg;
1317 priv = malloc(sizeof(*priv));
1321 host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
1323 switch (dev_index) {
1325 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1327 #ifdef OMAP_HSMMC2_BASE
1329 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
1330 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
1331 defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
1332 defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
1333 defined(CONFIG_HSMMC2_8BIT)
1334 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
1335 host_caps_val |= MMC_MODE_8BIT;
1339 #ifdef OMAP_HSMMC3_BASE
1341 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
1342 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
1343 /* Enable 8-bit interface for eMMC on DRA7XX */
1344 host_caps_val |= MMC_MODE_8BIT;
1349 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1352 #ifdef OMAP_HSMMC_USE_GPIO
1353 /* on error gpio values are set to -1, which is what we want */
1354 priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
1355 priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
1360 cfg->name = "OMAP SD/MMC";
1361 cfg->ops = &omap_hsmmc_ops;
1363 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1364 cfg->host_caps = host_caps_val & ~host_caps_mask;
1366 cfg->f_min = 400000;
1371 if (cfg->host_caps & MMC_MODE_HS) {
1372 if (cfg->host_caps & MMC_MODE_HS_52MHz)
1373 cfg->f_max = 52000000;
1375 cfg->f_max = 26000000;
1377 cfg->f_max = 20000000;
1380 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1382 #if defined(CONFIG_OMAP34XX)
1384 * Silicon revs 2.1 and older do not support multiblock transfers.
1386 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
1390 mmc = mmc_create(cfg, priv);
1398 #ifdef CONFIG_IODELAY_RECALIBRATION
1399 static struct pad_conf_entry *
1400 omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count)
1403 struct pad_conf_entry *padconf;
1405 padconf = (struct pad_conf_entry *)malloc(sizeof(*padconf) * count);
1407 debug("failed to allocate memory\n");
1411 while (index < count) {
1412 padconf[index].offset = fdt32_to_cpu(pinctrl[2 * index]);
1413 padconf[index].val = fdt32_to_cpu(pinctrl[2 * index + 1]);
1420 static struct iodelay_cfg_entry *
1421 omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t *pinctrl, int count)
1424 struct iodelay_cfg_entry *iodelay;
1426 iodelay = (struct iodelay_cfg_entry *)malloc(sizeof(*iodelay) * count);
1428 debug("failed to allocate memory\n");
1432 while (index < count) {
1433 iodelay[index].offset = fdt32_to_cpu(pinctrl[3 * index]);
1434 iodelay[index].a_delay = fdt32_to_cpu(pinctrl[3 * index + 1]);
1435 iodelay[index].g_delay = fdt32_to_cpu(pinctrl[3 * index + 2]);
1442 static const fdt32_t *omap_hsmmc_get_pinctrl_entry(u32 phandle,
1443 const char *name, int *len)
1445 const void *fdt = gd->fdt_blob;
1447 const fdt32_t *pinctrl;
1449 offset = fdt_node_offset_by_phandle(fdt, phandle);
1451 debug("failed to get pinctrl node %s.\n",
1452 fdt_strerror(offset));
1456 pinctrl = fdt_getprop(fdt, offset, name, len);
1458 debug("failed to get property %s\n", name);
1465 static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc *mmc,
1468 const void *fdt = gd->fdt_blob;
1469 const __be32 *phandle;
1470 int node = dev_of_offset(mmc->dev);
1472 phandle = fdt_getprop(fdt, node, prop_name, NULL);
1474 debug("failed to get property %s\n", prop_name);
1478 return fdt32_to_cpu(*phandle);
1481 static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc *mmc,
1484 const void *fdt = gd->fdt_blob;
1485 const __be32 *phandle;
1488 int node = dev_of_offset(mmc->dev);
1490 phandle = fdt_getprop(fdt, node, prop_name, &len);
1492 debug("failed to get property %s\n", prop_name);
1496 /* No manual mode iodelay values if count < 2 */
1497 count = len / sizeof(*phandle);
1501 return fdt32_to_cpu(*(phandle + 1));
1504 static struct pad_conf_entry *
1505 omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads)
1509 struct pad_conf_entry *padconf;
1511 const fdt32_t *pinctrl;
1513 phandle = omap_hsmmc_get_pad_conf_phandle(mmc, prop_name);
1515 return ERR_PTR(-EINVAL);
1517 pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-single,pins",
1520 return ERR_PTR(-EINVAL);
1522 count = (len / sizeof(*pinctrl)) / 2;
1523 padconf = omap_hsmmc_get_pad_conf_entry(pinctrl, count);
1525 return ERR_PTR(-EINVAL);
1532 static struct iodelay_cfg_entry *
1533 omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay)
1537 struct iodelay_cfg_entry *iodelay;
1539 const fdt32_t *pinctrl;
1541 phandle = omap_hsmmc_get_iodelay_phandle(mmc, prop_name);
1542 /* Not all modes have manual mode iodelay values. So its not fatal */
1546 pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-pin-array",
1549 return ERR_PTR(-EINVAL);
1551 count = (len / sizeof(*pinctrl)) / 3;
1552 iodelay = omap_hsmmc_get_iodelay_cfg_entry(pinctrl, count);
1554 return ERR_PTR(-EINVAL);
1561 static struct omap_hsmmc_pinctrl_state *
1562 omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode)
1567 const void *fdt = gd->fdt_blob;
1568 int node = dev_of_offset(mmc->dev);
1570 struct omap_hsmmc_pinctrl_state *pinctrl_state;
1572 pinctrl_state = (struct omap_hsmmc_pinctrl_state *)
1573 malloc(sizeof(*pinctrl_state));
1574 if (!pinctrl_state) {
1575 debug("failed to allocate memory\n");
1579 index = fdt_stringlist_search(fdt, node, "pinctrl-names", mode);
1581 debug("fail to find %s mode %s\n", mode, fdt_strerror(index));
1582 goto err_pinctrl_state;
1585 sprintf(prop_name, "pinctrl-%d", index);
1587 pinctrl_state->padconf = omap_hsmmc_get_pad_conf(mmc, prop_name,
1589 if (IS_ERR(pinctrl_state->padconf))
1590 goto err_pinctrl_state;
1591 pinctrl_state->npads = npads;
1593 pinctrl_state->iodelay = omap_hsmmc_get_iodelay(mmc, prop_name,
1595 if (IS_ERR(pinctrl_state->iodelay))
1597 pinctrl_state->niodelays = niodelays;
1599 return pinctrl_state;
1602 kfree(pinctrl_state->padconf);
1605 kfree(pinctrl_state);
1609 #define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode, optional) \
1611 struct omap_hsmmc_pinctrl_state *s = NULL; \
1613 if (!(cfg->host_caps & capmask)) \
1616 if (priv->hw_rev) { \
1617 sprintf(str, "%s-%s", #mode, priv->hw_rev); \
1618 s = omap_hsmmc_get_pinctrl_by_mode(mmc, str); \
1622 s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \
1624 if (!s && !optional) { \
1625 debug("%s: no pinctrl for %s\n", \
1626 mmc->dev->name, #mode); \
1627 cfg->host_caps &= ~(capmask); \
1629 priv->mode##_pinctrl_state = s; \
1633 static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc)
1635 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1636 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
1637 struct omap_hsmmc_pinctrl_state *default_pinctrl;
1639 if (!(priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY))
1642 default_pinctrl = omap_hsmmc_get_pinctrl_by_mode(mmc, "default");
1643 if (!default_pinctrl) {
1644 printf("no pinctrl state for default mode\n");
1648 priv->default_pinctrl_state = default_pinctrl;
1650 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104, false);
1651 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50, false);
1652 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50, false);
1653 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25, false);
1654 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12, false);
1656 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v, false);
1657 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v, false);
1658 OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs, true);
1664 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1665 #ifdef CONFIG_OMAP54XX
1666 __weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
1672 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
1674 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1675 struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev);
1677 struct mmc_config *cfg = &plat->cfg;
1678 #ifdef CONFIG_OMAP54XX
1679 const struct mmc_platform_fixups *fixups;
1681 const void *fdt = gd->fdt_blob;
1682 int node = dev_of_offset(dev);
1685 plat->base_addr = map_physmem(devfdt_get_addr(dev),
1686 sizeof(struct hsmmc *),
1689 ret = mmc_of_parse(dev, cfg);
1693 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1694 cfg->f_min = 400000;
1695 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1696 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1697 if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
1698 plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1699 if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
1700 plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
1702 plat->controller_flags |= of_data->controller_flags;
1704 #ifdef CONFIG_OMAP54XX
1705 fixups = platform_fixups_mmc(devfdt_get_addr(dev));
1707 plat->hw_rev = fixups->hw_rev;
1708 cfg->host_caps &= ~fixups->unsupported_caps;
1709 cfg->f_max = fixups->max_freq;
1713 #ifdef OMAP_HSMMC_USE_GPIO
1714 plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted");
1723 static int omap_hsmmc_bind(struct udevice *dev)
1725 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1727 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1730 static int omap_hsmmc_probe(struct udevice *dev)
1732 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1733 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1734 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1735 struct mmc_config *cfg = &plat->cfg;
1737 #ifdef CONFIG_IODELAY_RECALIBRATION
1741 cfg->name = "OMAP SD/MMC";
1742 priv->base_addr = plat->base_addr;
1743 priv->controller_flags = plat->controller_flags;
1744 priv->hw_rev = plat->hw_rev;
1745 #ifdef OMAP_HSMMC_USE_GPIO
1746 priv->cd_inverted = plat->cd_inverted;
1752 mmc = mmc_create(cfg, priv);
1757 #if defined(OMAP_HSMMC_USE_GPIO) && CONFIG_IS_ENABLED(OF_CONTROL)
1758 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1759 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1765 #ifdef CONFIG_IODELAY_RECALIBRATION
1766 ret = omap_hsmmc_get_pinctrl_state(mmc);
1768 * disable high speed modes for the platforms that require IO delay
1769 * and for which we don't have this information
1772 (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) {
1773 priv->controller_flags &= ~OMAP_HSMMC_REQUIRE_IODELAY;
1774 cfg->host_caps &= ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_DDR_52) |
1779 return omap_hsmmc_init_setup(mmc);
1782 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1784 static const struct omap_mmc_of_data dra7_mmc_of_data = {
1785 .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY,
1788 static const struct udevice_id omap_hsmmc_ids[] = {
1789 { .compatible = "ti,omap3-hsmmc" },
1790 { .compatible = "ti,omap4-hsmmc" },
1791 { .compatible = "ti,am33xx-hsmmc" },
1792 { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data },
1797 U_BOOT_DRIVER(omap_hsmmc) = {
1798 .name = "omap_hsmmc",
1800 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1801 .of_match = omap_hsmmc_ids,
1802 .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
1803 .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
1806 .bind = omap_hsmmc_bind,
1808 .ops = &omap_hsmmc_ops,
1809 .probe = omap_hsmmc_probe,
1810 .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
1811 .flags = DM_FLAG_PRE_RELOC,