git.sur5r.net Git - u-boot/blob - drivers/mmc/omap_hsmmc.c

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  * Sukumar Ghorai <s-ghorai@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation's version 2 of
  12  * the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26 #include <common.h>
  27 #include <mmc.h>
  28 #include <part.h>
  29 #include <i2c.h>
  30 #include <twl4030.h>
  31 #include <twl6030.h>
  32 #include <twl6035.h>
  33 #include <asm/gpio.h>
  34 #include <asm/io.h>
  35 #include <asm/arch/mmc_host_def.h>
  36 #include <asm/arch/sys_proto.h>
  37
  38 /* common definitions for all OMAPs */
  39 #define SYSCTL_SRC      (1 << 25)
  40 #define SYSCTL_SRD      (1 << 26)
  41
  42 struct omap_hsmmc_data {
  43         struct hsmmc *base_addr;
  44         int cd_gpio;
  45         int wp_gpio;
  46 };
  47
  48 /* If we fail after 1 second wait, something is really bad */
  49 #define MAX_RETRY_MS    1000
  50
  51 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
  52 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
  53                         unsigned int siz);
  54 static struct mmc hsmmc_dev[3];
  55 static struct omap_hsmmc_data hsmmc_dev_data[3];
  56
  57 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
  58         (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
  59 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
  60 {
  61         if (!gpio_is_valid(gpio))
  62                 return -1;
  63
  64         if (gpio_request(gpio, label) < 0)
  65                 return -1;
  66
  67         if (gpio_direction_input(gpio) < 0)
  68                 return -1;
  69
  70         return gpio;
  71 }
  72
  73 static int omap_mmc_getcd(struct mmc *mmc)
  74 {
  75         int cd_gpio = ((struct omap_hsmmc_data *)mmc->priv)->cd_gpio;
  76         return gpio_get_value(cd_gpio);
  77 }
  78
  79 static int omap_mmc_getwp(struct mmc *mmc)
  80 {
  81         int wp_gpio = ((struct omap_hsmmc_data *)mmc->priv)->wp_gpio;
  82         return gpio_get_value(wp_gpio);
  83 }
  84 #else
  85 static inline int omap_mmc_setup_gpio_in(int gpio, const char *label)
  86 {
  87         return -1;
  88 }
  89
  90 #define omap_mmc_getcd NULL
  91 #define omap_mmc_getwp NULL
  92 #endif
  93
  94 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
  95 static void omap4_vmmc_pbias_config(struct mmc *mmc)
  96 {
  97         u32 value = 0;
  98         struct omap_sys_ctrl_regs *const ctrl =
  99                 (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
 100
 101
 102         value = readl(&ctrl->control_pbiaslite);
 103         value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
 104         writel(value, &ctrl->control_pbiaslite);
 105         /* set VMMC to 3V */
 106         twl6030_power_mmc_init();
 107         value = readl(&ctrl->control_pbiaslite);
 108         value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
 109         writel(value, &ctrl->control_pbiaslite);
 110 }
 111 #endif
 112
 113 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_TWL6035_POWER)
 114 static void omap5_pbias_config(struct mmc *mmc)
 115 {
 116         u32 value = 0;
 117         struct omap_sys_ctrl_regs *const ctrl =
 118                 (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
 119
 120         value = readl(&ctrl->control_pbias);
 121         value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ);
 122         value |= SDCARD_BIAS_HIZ_MODE;
 123         writel(value, &ctrl->control_pbias);
 124
 125         twl6035_mmc1_poweron_ldo();
 126
 127         value = readl(&ctrl->control_pbias);
 128         value &= ~SDCARD_BIAS_HIZ_MODE;
 129         value |= SDCARD_PBIASLITE_VMODE | SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ;
 130         writel(value, &ctrl->control_pbias);
 131
 132         value = readl(&ctrl->control_pbias);
 133         if (value & (1 << 23)) {
 134                 value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ);
 135                 value |= SDCARD_BIAS_HIZ_MODE;
 136                 writel(value, &ctrl->control_pbias);
 137         }
 138 }
 139 #endif
 140
 141 unsigned char mmc_board_init(struct mmc *mmc)
 142 {
 143 #if defined(CONFIG_OMAP34XX)
 144         t2_t *t2_base = (t2_t *)T2_BASE;
 145         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 146         u32 pbias_lite;
 147
 148         pbias_lite = readl(&t2_base->pbias_lite);
 149         pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
 150         writel(pbias_lite, &t2_base->pbias_lite);
 151 #endif
 152 #if defined(CONFIG_TWL4030_POWER)
 153         twl4030_power_mmc_init();
 154         mdelay(100);    /* ramp-up delay from Linux code */
 155 #endif
 156 #if defined(CONFIG_OMAP34XX)
 157         writel(pbias_lite | PBIASLITEPWRDNZ1 |
 158                 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
 159                 &t2_base->pbias_lite);
 160
 161         writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
 162                 &t2_base->devconf0);
 163
 164         writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
 165                 &t2_base->devconf1);
 166
 167         /* Change from default of 52MHz to 26MHz if necessary */
 168         if (!(mmc->host_caps & MMC_MODE_HS_52MHz))
 169                 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
 170                         &t2_base->ctl_prog_io1);
 171
 172         writel(readl(&prcm_base->fclken1_core) |
 173                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 174                 &prcm_base->fclken1_core);
 175
 176         writel(readl(&prcm_base->iclken1_core) |
 177                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 178                 &prcm_base->iclken1_core);
 179 #endif
 180
 181 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
 182         /* PBIAS config needed for MMC1 only */
 183         if (mmc->block_dev.dev == 0)
 184                 omap4_vmmc_pbias_config(mmc);
 185 #endif
 186 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_TWL6035_POWER)
 187         if (mmc->block_dev.dev == 0)
 188                 omap5_pbias_config(mmc);
 189 #endif
 190
 191         return 0;
 192 }
 193
 194 void mmc_init_stream(struct hsmmc *mmc_base)
 195 {
 196         ulong start;
 197
 198         writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
 199
 200         writel(MMC_CMD0, &mmc_base->cmd);
 201         start = get_timer(0);
 202         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 203                 if (get_timer(0) - start > MAX_RETRY_MS) {
 204                         printf("%s: timedout waiting for cc!\n", __func__);
 205                         return;
 206                 }
 207         }
 208         writel(CC_MASK, &mmc_base->stat)
 209                 ;
 210         writel(MMC_CMD0, &mmc_base->cmd)
 211                 ;
 212         start = get_timer(0);
 213         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 214                 if (get_timer(0) - start > MAX_RETRY_MS) {
 215                         printf("%s: timedout waiting for cc2!\n", __func__);
 216                         return;
 217                 }
 218         }
 219         writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
 220 }
 221
 222
 223 static int mmc_init_setup(struct mmc *mmc)
 224 {
 225         struct hsmmc *mmc_base;
 226         unsigned int reg_val;
 227         unsigned int dsor;
 228         ulong start;
 229
 230         mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
 231         mmc_board_init(mmc);
 232
 233         writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
 234                 &mmc_base->sysconfig);
 235         start = get_timer(0);
 236         while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
 237                 if (get_timer(0) - start > MAX_RETRY_MS) {
 238                         printf("%s: timedout waiting for cc2!\n", __func__);
 239                         return TIMEOUT;
 240                 }
 241         }
 242         writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
 243         start = get_timer(0);
 244         while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
 245                 if (get_timer(0) - start > MAX_RETRY_MS) {
 246                         printf("%s: timedout waiting for softresetall!\n",
 247                                 __func__);
 248                         return TIMEOUT;
 249                 }
 250         }
 251         writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
 252         writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
 253                 &mmc_base->capa);
 254
 255         reg_val = readl(&mmc_base->con) & RESERVED_MASK;
 256
 257         writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
 258                 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
 259                 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
 260
 261         dsor = 240;
 262         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 263                 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
 264         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 265                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 266         start = get_timer(0);
 267         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 268                 if (get_timer(0) - start > MAX_RETRY_MS) {
 269                         printf("%s: timedout waiting for ics!\n", __func__);
 270                         return TIMEOUT;
 271                 }
 272         }
 273         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 274
 275         writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
 276
 277         writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
 278                 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
 279                 &mmc_base->ie);
 280
 281         mmc_init_stream(mmc_base);
 282
 283         return 0;
 284 }
 285
 286 /*
 287  * MMC controller internal finite state machine reset
 288  *
 289  * Used to reset command or data internal state machines, using respectively
 290  * SRC or SRD bit of SYSCTL register
 291  */
 292 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
 293 {
 294         ulong start;
 295
 296         mmc_reg_out(&mmc_base->sysctl, bit, bit);
 297
 298         start = get_timer(0);
 299         while ((readl(&mmc_base->sysctl) & bit) != 0) {
 300                 if (get_timer(0) - start > MAX_RETRY_MS) {
 301                         printf("%s: timedout waiting for sysctl %x to clear\n",
 302                                 __func__, bit);
 303                         return;
 304                 }
 305         }
 306 }
 307
 308 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 309                         struct mmc_data *data)
 310 {
 311         struct hsmmc *mmc_base;
 312         unsigned int flags, mmc_stat;
 313         ulong start;
 314
 315         mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
 316         start = get_timer(0);
 317         while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
 318                 if (get_timer(0) - start > MAX_RETRY_MS) {
 319                         printf("%s: timedout waiting on cmd inhibit to clear\n",
 320                                         __func__);
 321                         return TIMEOUT;
 322                 }
 323         }
 324         writel(0xFFFFFFFF, &mmc_base->stat);
 325         start = get_timer(0);
 326         while (readl(&mmc_base->stat)) {
 327                 if (get_timer(0) - start > MAX_RETRY_MS) {
 328                         printf("%s: timedout waiting for STAT (%x) to clear\n",
 329                                 __func__, readl(&mmc_base->stat));
 330                         return TIMEOUT;
 331                 }
 332         }
 333         /*
 334          * CMDREG
 335          * CMDIDX[13:8] : Command index
 336          * DATAPRNT[5]  : Data Present Select
 337          * ENCMDIDX[4]  : Command Index Check Enable
 338          * ENCMDCRC[3]  : Command CRC Check Enable
 339          * RSPTYP[1:0]
 340          *      00 = No Response
 341          *      01 = Length 136
 342          *      10 = Length 48
 343          *      11 = Length 48 Check busy after response
 344          */
 345         /* Delay added before checking the status of frq change
 346          * retry not supported by mmc.c(core file)
 347          */
 348         if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
 349                 udelay(50000); /* wait 50 ms */
 350
 351         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 352                 flags = 0;
 353         else if (cmd->resp_type & MMC_RSP_136)
 354                 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
 355         else if (cmd->resp_type & MMC_RSP_BUSY)
 356                 flags = RSP_TYPE_LGHT48B;
 357         else
 358                 flags = RSP_TYPE_LGHT48;
 359
 360         /* enable default flags */
 361         flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
 362                         MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
 363
 364         if (cmd->resp_type & MMC_RSP_CRC)
 365                 flags |= CCCE_CHECK;
 366         if (cmd->resp_type & MMC_RSP_OPCODE)
 367                 flags |= CICE_CHECK;
 368
 369         if (data) {
 370                 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
 371                          (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
 372                         flags |= (MSBS_MULTIBLK | BCE_ENABLE);
 373                         data->blocksize = 512;
 374                         writel(data->blocksize | (data->blocks << 16),
 375                                                         &mmc_base->blk);
 376                 } else
 377                         writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
 378
 379                 if (data->flags & MMC_DATA_READ)
 380                         flags |= (DP_DATA | DDIR_READ);
 381                 else
 382                         flags |= (DP_DATA | DDIR_WRITE);
 383         }
 384
 385         writel(cmd->cmdarg, &mmc_base->arg);
 386         writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
 387
 388         start = get_timer(0);
 389         do {
 390                 mmc_stat = readl(&mmc_base->stat);
 391                 if (get_timer(0) - start > MAX_RETRY_MS) {
 392                         printf("%s : timeout: No status update\n", __func__);
 393                         return TIMEOUT;
 394                 }
 395         } while (!mmc_stat);
 396
 397         if ((mmc_stat & IE_CTO) != 0) {
 398                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 399                 return TIMEOUT;
 400         } else if ((mmc_stat & ERRI_MASK) != 0)
 401                 return -1;
 402
 403         if (mmc_stat & CC_MASK) {
 404                 writel(CC_MASK, &mmc_base->stat);
 405                 if (cmd->resp_type & MMC_RSP_PRESENT) {
 406                         if (cmd->resp_type & MMC_RSP_136) {
 407                                 /* response type 2 */
 408                                 cmd->response[3] = readl(&mmc_base->rsp10);
 409                                 cmd->response[2] = readl(&mmc_base->rsp32);
 410                                 cmd->response[1] = readl(&mmc_base->rsp54);
 411                                 cmd->response[0] = readl(&mmc_base->rsp76);
 412                         } else
 413                                 /* response types 1, 1b, 3, 4, 5, 6 */
 414                                 cmd->response[0] = readl(&mmc_base->rsp10);
 415                 }
 416         }
 417
 418         if (data && (data->flags & MMC_DATA_READ)) {
 419                 mmc_read_data(mmc_base, data->dest,
 420                                 data->blocksize * data->blocks);
 421         } else if (data && (data->flags & MMC_DATA_WRITE)) {
 422                 mmc_write_data(mmc_base, data->src,
 423                                 data->blocksize * data->blocks);
 424         }
 425         return 0;
 426 }
 427
 428 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
 429 {
 430         unsigned int *output_buf = (unsigned int *)buf;
 431         unsigned int mmc_stat;
 432         unsigned int count;
 433
 434         /*
 435          * Start Polled Read
 436          */
 437         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
 438         count /= 4;
 439
 440         while (size) {
 441                 ulong start = get_timer(0);
 442                 do {
 443                         mmc_stat = readl(&mmc_base->stat);
 444                         if (get_timer(0) - start > MAX_RETRY_MS) {
 445                                 printf("%s: timedout waiting for status!\n",
 446                                                 __func__);
 447                                 return TIMEOUT;
 448                         }
 449                 } while (mmc_stat == 0);
 450
 451                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
 452                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 453
 454                 if ((mmc_stat & ERRI_MASK) != 0)
 455                         return 1;
 456
 457                 if (mmc_stat & BRR_MASK) {
 458                         unsigned int k;
 459
 460                         writel(readl(&mmc_base->stat) | BRR_MASK,
 461                                 &mmc_base->stat);
 462                         for (k = 0; k < count; k++) {
 463                                 *output_buf = readl(&mmc_base->data);
 464                                 output_buf++;
 465                         }
 466                         size -= (count*4);
 467                 }
 468
 469                 if (mmc_stat & BWR_MASK)
 470                         writel(readl(&mmc_base->stat) | BWR_MASK,
 471                                 &mmc_base->stat);
 472
 473                 if (mmc_stat & TC_MASK) {
 474                         writel(readl(&mmc_base->stat) | TC_MASK,
 475                                 &mmc_base->stat);
 476                         break;
 477                 }
 478         }
 479         return 0;
 480 }
 481
 482 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 483                                 unsigned int size)
 484 {
 485         unsigned int *input_buf = (unsigned int *)buf;
 486         unsigned int mmc_stat;
 487         unsigned int count;
 488
 489         /*
 490          * Start Polled Read
 491          */
 492         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
 493         count /= 4;
 494
 495         while (size) {
 496                 ulong start = get_timer(0);
 497                 do {
 498                         mmc_stat = readl(&mmc_base->stat);
 499                         if (get_timer(0) - start > MAX_RETRY_MS) {
 500                                 printf("%s: timedout waiting for status!\n",
 501                                                 __func__);
 502                                 return TIMEOUT;
 503                         }
 504                 } while (mmc_stat == 0);
 505
 506                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
 507                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 508
 509                 if ((mmc_stat & ERRI_MASK) != 0)
 510                         return 1;
 511
 512                 if (mmc_stat & BWR_MASK) {
 513                         unsigned int k;
 514
 515                         writel(readl(&mmc_base->stat) | BWR_MASK,
 516                                         &mmc_base->stat);
 517                         for (k = 0; k < count; k++) {
 518                                 writel(*input_buf, &mmc_base->data);
 519                                 input_buf++;
 520                         }
 521                         size -= (count*4);
 522                 }
 523
 524                 if (mmc_stat & BRR_MASK)
 525                         writel(readl(&mmc_base->stat) | BRR_MASK,
 526                                 &mmc_base->stat);
 527
 528                 if (mmc_stat & TC_MASK) {
 529                         writel(readl(&mmc_base->stat) | TC_MASK,
 530                                 &mmc_base->stat);
 531                         break;
 532                 }
 533         }
 534         return 0;
 535 }
 536
 537 static void mmc_set_ios(struct mmc *mmc)
 538 {
 539         struct hsmmc *mmc_base;
 540         unsigned int dsor = 0;
 541         ulong start;
 542
 543         mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
 544         /* configue bus width */
 545         switch (mmc->bus_width) {
 546         case 8:
 547                 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
 548                         &mmc_base->con);
 549                 break;
 550
 551         case 4:
 552                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
 553                         &mmc_base->con);
 554                 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
 555                         &mmc_base->hctl);
 556                 break;
 557
 558         case 1:
 559         default:
 560                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
 561                         &mmc_base->con);
 562                 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
 563                         &mmc_base->hctl);
 564                 break;
 565         }
 566
 567         /* configure clock with 96Mhz system clock.
 568          */
 569         if (mmc->clock != 0) {
 570                 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
 571                 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
 572                         dsor++;
 573         }
 574
 575         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 576                                 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
 577
 578         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 579                                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 580
 581         start = get_timer(0);
 582         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 583                 if (get_timer(0) - start > MAX_RETRY_MS) {
 584                         printf("%s: timedout waiting for ics!\n", __func__);
 585                         return;
 586                 }
 587         }
 588         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 589 }
 590
 591 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
 592                 int wp_gpio)
 593 {
 594         struct mmc *mmc = &hsmmc_dev[dev_index];
 595         struct omap_hsmmc_data *priv_data = &hsmmc_dev_data[dev_index];
 596
 597         sprintf(mmc->name, "OMAP SD/MMC");
 598         mmc->send_cmd = mmc_send_cmd;
 599         mmc->set_ios = mmc_set_ios;
 600         mmc->init = mmc_init_setup;
 601         mmc->getcd = omap_mmc_getcd;
 602         mmc->getwp = omap_mmc_getwp;
 603         mmc->priv = priv_data;
 604
 605         switch (dev_index) {
 606         case 0:
 607                 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
 608                 break;
 609 #ifdef OMAP_HSMMC2_BASE
 610         case 1:
 611                 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
 612                 break;
 613 #endif
 614 #ifdef OMAP_HSMMC3_BASE
 615         case 2:
 616                 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
 617                 break;
 618 #endif
 619         default:
 620                 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
 621                 return 1;
 622         }
 623         priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
 624         priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
 625         mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 626         mmc->host_caps = (MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
 627                                 MMC_MODE_HC) & ~host_caps_mask;
 628
 629         mmc->f_min = 400000;
 630
 631         if (f_max != 0)
 632                 mmc->f_max = f_max;
 633         else {
 634                 if (mmc->host_caps & MMC_MODE_HS) {
 635                         if (mmc->host_caps & MMC_MODE_HS_52MHz)
 636                                 mmc->f_max = 52000000;
 637                         else
 638                                 mmc->f_max = 26000000;
 639                 } else
 640                         mmc->f_max = 20000000;
 641         }
 642
 643         mmc->b_max = 0;
 644
 645 #if defined(CONFIG_OMAP34XX)
 646         /*
 647          * Silicon revs 2.1 and older do not support multiblock transfers.
 648          */
 649         if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
 650                 mmc->b_max = 1;
 651 #endif
 652
 653         mmc_register(mmc);
 654
 655         return 0;
 656 }