2 * (C) Copyright 2009 SAMSUNG Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
4 * Jaehoon Chung <jh80.chung@samsung.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <asm/arch/mmc.h>
26 #ifdef DEBUG_S5P_HSMMC
27 #define dbg(x...) printf(x)
29 #define dbg(x...) do { } while (0)
32 /* support 4 mmc hosts */
33 struct mmc mmc_dev[4];
34 struct mmc_host mmc_host[4];
36 static inline struct s5p_mmc *s5p_get_base_mmc(int dev_index)
38 unsigned long offset = dev_index * sizeof(struct s5p_mmc);
41 return (struct s5p_mmc *)(S5PC100_MMC_BASE + offset);
43 return (struct s5p_mmc *)(S5PC110_MMC_BASE + offset);
46 static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data)
50 dbg("data->dest: %08x\n", (u32)data->dest);
51 writel((u32)data->dest, &host->reg->sysad);
56 * 10 = Selects 32-bit Address ADMA2
57 * 11 = Selects 64-bit Address ADMA2
59 ctrl = readb(&host->reg->hostctl);
61 writeb(ctrl, &host->reg->hostctl);
63 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
64 writew((7 << 12) | (512 << 0), &host->reg->blksize);
65 writew(data->blocks, &host->reg->blkcnt);
68 static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data)
74 * MUL1SIN0[5] : Multi/Single Block Select
75 * RD1WT0[4] : Data Transfer Direction Select
78 * ENACMD12[2] : Auto CMD12 Enable
79 * ENBLKCNT[1] : Block Count Enable
80 * ENDMA[0] : DMA Enable
82 mode = (1 << 1) | (1 << 0);
85 if (data->flags & MMC_DATA_READ)
88 writew(mode, &host->reg->trnmod);
91 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
92 struct mmc_data *data)
94 struct mmc_host *host = (struct mmc_host *)mmc->priv;
98 unsigned int retry = 0x100000;
105 * CMDINHDAT[1] : Command Inhibit (DAT)
106 * CMDINHCMD[0] : Command Inhibit (CMD)
109 if ((data != NULL) || (cmd->resp_type & MMC_RSP_BUSY))
113 * We shouldn't wait for data inihibit for stop commands, even
114 * though they might use busy signaling
119 while (readl(&host->reg->prnsts) & mask) {
121 printf("%s: timeout error\n", __func__);
129 mmc_prepare_data(host, data);
131 dbg("cmd->arg: %08x\n", cmd->cmdarg);
132 writel(cmd->cmdarg, &host->reg->argument);
135 mmc_set_transfer_mode(host, data);
137 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
142 * CMDIDX[13:8] : Command index
143 * DATAPRNT[5] : Data Present Select
144 * ENCMDIDX[4] : Command Index Check Enable
145 * ENCMDCRC[3] : Command CRC Check Enable
150 * 11 = Length 48 Check busy after response
152 if (!(cmd->resp_type & MMC_RSP_PRESENT))
154 else if (cmd->resp_type & MMC_RSP_136)
156 else if (cmd->resp_type & MMC_RSP_BUSY)
161 if (cmd->resp_type & MMC_RSP_CRC)
163 if (cmd->resp_type & MMC_RSP_OPCODE)
168 dbg("cmd: %d\n", cmd->cmdidx);
170 writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg);
172 for (i = 0; i < retry; i++) {
173 mask = readl(&host->reg->norintsts);
174 /* Command Complete */
175 if (mask & (1 << 0)) {
177 writel(mask, &host->reg->norintsts);
183 printf("%s: waiting for status update\n", __func__);
187 if (mask & (1 << 16)) {
189 dbg("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
191 } else if (mask & (1 << 15)) {
192 /* Error Interrupt */
193 dbg("error: %08x cmd %d\n", mask, cmd->cmdidx);
197 if (cmd->resp_type & MMC_RSP_PRESENT) {
198 if (cmd->resp_type & MMC_RSP_136) {
199 /* CRC is stripped so we need to do some shifting. */
200 for (i = 0; i < 4; i++) {
201 unsigned int offset =
202 (unsigned int)(&host->reg->rspreg3 - i);
203 cmd->response[i] = readl(offset) << 8;
209 dbg("cmd->resp[%d]: %08x\n",
210 i, cmd->response[i]);
212 } else if (cmd->resp_type & MMC_RSP_BUSY) {
213 for (i = 0; i < retry; i++) {
214 /* PRNTDATA[23:20] : DAT[3:0] Line Signal */
215 if (readl(&host->reg->prnsts)
216 & (1 << 20)) /* DAT[0] */
221 printf("%s: card is still busy\n", __func__);
225 cmd->response[0] = readl(&host->reg->rspreg0);
226 dbg("cmd->resp[0]: %08x\n", cmd->response[0]);
228 cmd->response[0] = readl(&host->reg->rspreg0);
229 dbg("cmd->resp[0]: %08x\n", cmd->response[0]);
235 mask = readl(&host->reg->norintsts);
237 if (mask & (1 << 15)) {
238 /* Error Interrupt */
239 writel(mask, &host->reg->norintsts);
240 printf("%s: error during transfer: 0x%08x\n",
243 } else if (mask & (1 << 3)) {
247 } else if (mask & (1 << 1)) {
248 /* Transfer Complete */
249 dbg("r/w is done\n");
253 writel(mask, &host->reg->norintsts);
260 static void mmc_change_clock(struct mmc_host *host, uint clock)
264 unsigned long timeout;
271 * 11 = XTI or XEXTCLK
273 ctrl2 = readl(&host->reg->control2);
276 writel(ctrl2, &host->reg->control2);
278 writew(0, &host->reg->clkcon);
280 /* XXX: we assume that clock is between 40MHz and 50MHz */
283 else if (clock <= 400000)
285 else if (clock <= 20000000)
287 else if (clock <= 26000000)
291 dbg("div: %d\n", div);
296 * SELFREQ[15:8] : base clock divied by value
297 * ENSDCLK[2] : SD Clock Enable
298 * STBLINTCLK[1] : Internal Clock Stable
299 * ENINTCLK[0] : Internal Clock Enable
301 clk = (div << 8) | (1 << 0);
302 writew(clk, &host->reg->clkcon);
306 while (!(readw(&host->reg->clkcon) & (1 << 1))) {
308 printf("%s: timeout error\n", __func__);
316 writew(clk, &host->reg->clkcon);
322 static void mmc_set_ios(struct mmc *mmc)
324 struct mmc_host *host = mmc->priv;
328 dbg("set_ios: bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
337 writel(0x3 << 16, &host->reg->control4);
339 val = readl(&host->reg->control2);
342 val |= (1 << 31) | /* write status clear async mode enable */
343 (1 << 30) | /* command conflict mask enable */
344 (1 << 14) | /* Feedback Clock Enable for Rx Clock */
345 (1 << 8); /* SDCLK hold enable */
347 writel(val, &host->reg->control2);
350 * FCSEL1[15] FCSEL0[7]
351 * FCSel[1:0] : Rx Feedback Clock Delay Control
352 * Inverter delay means10ns delay if SDCLK 50MHz setting
353 * 01 = Delay1 (basic delay)
354 * 11 = Delay2 (basic delay + 2ns)
355 * 00 = Delay3 (inverter delay)
356 * 10 = Delay4 (inverter delay + 2ns)
358 writel(0x8080, &host->reg->control3);
360 mmc_change_clock(host, mmc->clock);
362 ctrl = readb(&host->reg->hostctl);
369 if (mmc->bus_width == 4)
376 * 1 = Riging edge output
377 * 0 = Falling edge output
381 writeb(ctrl, &host->reg->hostctl);
384 static void mmc_reset(struct mmc_host *host)
386 unsigned int timeout;
389 * RSTALL[0] : Software reset for all
393 writeb((1 << 0), &host->reg->swrst);
397 /* Wait max 100 ms */
400 /* hw clears the bit when it's done */
401 while (readb(&host->reg->swrst) & (1 << 0)) {
403 printf("%s: timeout error\n", __func__);
411 static int mmc_core_init(struct mmc *mmc)
413 struct mmc_host *host = (struct mmc_host *)mmc->priv;
418 host->version = readw(&host->reg->hcver);
421 writel(0xffffffff, &host->reg->norintstsen);
422 writel(0xffffffff, &host->reg->norintsigen);
424 writeb(0xe, &host->reg->timeoutcon); /* TMCLK * 2^27 */
427 * NORMAL Interrupt Status Enable Register init
428 * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
429 * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
430 * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
431 * [0] ENSTACMDCMPLT : Command Complete Status Enable
433 mask = readl(&host->reg->norintstsen);
435 mask |= (1 << 5) | (1 << 4) | (1 << 1) | (1 << 0);
436 writel(mask, &host->reg->norintstsen);
439 * NORMAL Interrupt Signal Enable Register init
440 * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
442 mask = readl(&host->reg->norintsigen);
445 writel(mask, &host->reg->norintsigen);
450 static int s5p_mmc_initialize(int dev_index)
454 mmc = &mmc_dev[dev_index];
456 sprintf(mmc->name, "SAMSUNG SD/MMC");
457 mmc->priv = &mmc_host[dev_index];
458 mmc->send_cmd = mmc_send_cmd;
459 mmc->set_ios = mmc_set_ios;
460 mmc->init = mmc_core_init;
462 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
463 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
466 mmc->f_max = 52000000;
468 mmc_host[dev_index].clock = 0;
469 mmc_host[dev_index].reg = s5p_get_base_mmc(dev_index);
475 int s5p_mmc_init(int dev_index)
477 return s5p_mmc_initialize(dev_index);