2 * (C) Copyright 2009 SAMSUNG Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
4 * Jaehoon Chung <jh80.chung@samsung.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <asm/arch/mmc.h>
25 #include <asm/arch/clk.h>
27 /* support 4 mmc hosts */
28 struct mmc mmc_dev[4];
29 struct mmc_host mmc_host[4];
31 static inline struct s5p_mmc *s5p_get_base_mmc(int dev_index)
33 unsigned long offset = dev_index * sizeof(struct s5p_mmc);
34 return (struct s5p_mmc *)(samsung_get_base_mmc() + offset);
37 static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data)
41 debug("data->dest: %08x\n", (u32)data->dest);
42 writel((u32)data->dest, &host->reg->sysad);
47 * 10 = Selects 32-bit Address ADMA2
48 * 11 = Selects 64-bit Address ADMA2
50 ctrl = readb(&host->reg->hostctl);
52 writeb(ctrl, &host->reg->hostctl);
54 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
55 writew((7 << 12) | (data->blocksize & 0xFFF), &host->reg->blksize);
56 writew(data->blocks, &host->reg->blkcnt);
59 static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data)
65 * MUL1SIN0[5] : Multi/Single Block Select
66 * RD1WT0[4] : Data Transfer Direction Select
69 * ENACMD12[2] : Auto CMD12 Enable
70 * ENBLKCNT[1] : Block Count Enable
71 * ENDMA[0] : DMA Enable
73 mode = (1 << 1) | (1 << 0);
76 if (data->flags & MMC_DATA_READ)
79 writew(mode, &host->reg->trnmod);
82 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
83 struct mmc_data *data)
85 struct mmc_host *host = (struct mmc_host *)mmc->priv;
89 unsigned int retry = 0x100000;
96 * CMDINHDAT[1] : Command Inhibit (DAT)
97 * CMDINHCMD[0] : Command Inhibit (CMD)
100 if ((data != NULL) || (cmd->resp_type & MMC_RSP_BUSY))
104 * We shouldn't wait for data inihibit for stop commands, even
105 * though they might use busy signaling
110 while (readl(&host->reg->prnsts) & mask) {
112 printf("%s: timeout error\n", __func__);
120 mmc_prepare_data(host, data);
122 debug("cmd->arg: %08x\n", cmd->cmdarg);
123 writel(cmd->cmdarg, &host->reg->argument);
126 mmc_set_transfer_mode(host, data);
128 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
133 * CMDIDX[13:8] : Command index
134 * DATAPRNT[5] : Data Present Select
135 * ENCMDIDX[4] : Command Index Check Enable
136 * ENCMDCRC[3] : Command CRC Check Enable
141 * 11 = Length 48 Check busy after response
143 if (!(cmd->resp_type & MMC_RSP_PRESENT))
145 else if (cmd->resp_type & MMC_RSP_136)
147 else if (cmd->resp_type & MMC_RSP_BUSY)
152 if (cmd->resp_type & MMC_RSP_CRC)
154 if (cmd->resp_type & MMC_RSP_OPCODE)
159 debug("cmd: %d\n", cmd->cmdidx);
161 writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg);
163 for (i = 0; i < retry; i++) {
164 mask = readl(&host->reg->norintsts);
165 /* Command Complete */
166 if (mask & (1 << 0)) {
168 writel(mask, &host->reg->norintsts);
174 printf("%s: waiting for status update\n", __func__);
178 if (mask & (1 << 16)) {
180 debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
182 } else if (mask & (1 << 15)) {
183 /* Error Interrupt */
184 debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
188 if (cmd->resp_type & MMC_RSP_PRESENT) {
189 if (cmd->resp_type & MMC_RSP_136) {
190 /* CRC is stripped so we need to do some shifting. */
191 for (i = 0; i < 4; i++) {
192 unsigned int offset =
193 (unsigned int)(&host->reg->rspreg3 - i);
194 cmd->response[i] = readl(offset) << 8;
200 debug("cmd->resp[%d]: %08x\n",
201 i, cmd->response[i]);
203 } else if (cmd->resp_type & MMC_RSP_BUSY) {
204 for (i = 0; i < retry; i++) {
205 /* PRNTDATA[23:20] : DAT[3:0] Line Signal */
206 if (readl(&host->reg->prnsts)
207 & (1 << 20)) /* DAT[0] */
212 printf("%s: card is still busy\n", __func__);
216 cmd->response[0] = readl(&host->reg->rspreg0);
217 debug("cmd->resp[0]: %08x\n", cmd->response[0]);
219 cmd->response[0] = readl(&host->reg->rspreg0);
220 debug("cmd->resp[0]: %08x\n", cmd->response[0]);
226 mask = readl(&host->reg->norintsts);
228 if (mask & (1 << 15)) {
229 /* Error Interrupt */
230 writel(mask, &host->reg->norintsts);
231 printf("%s: error during transfer: 0x%08x\n",
234 } else if (mask & (1 << 3)) {
238 } else if (mask & (1 << 1)) {
239 /* Transfer Complete */
240 debug("r/w is done\n");
244 writel(mask, &host->reg->norintsts);
251 static void mmc_change_clock(struct mmc_host *host, uint clock)
255 unsigned long timeout;
262 * 11 = XTI or XEXTCLK
264 ctrl2 = readl(&host->reg->control2);
267 writel(ctrl2, &host->reg->control2);
269 writew(0, &host->reg->clkcon);
271 /* XXX: we assume that clock is between 40MHz and 50MHz */
274 else if (clock <= 400000)
276 else if (clock <= 20000000)
278 else if (clock <= 26000000)
282 debug("div: %d\n", div);
287 * SELFREQ[15:8] : base clock divied by value
288 * ENSDCLK[2] : SD Clock Enable
289 * STBLINTCLK[1] : Internal Clock Stable
290 * ENINTCLK[0] : Internal Clock Enable
292 clk = (div << 8) | (1 << 0);
293 writew(clk, &host->reg->clkcon);
295 set_mmc_clk(host->dev_index, div);
299 while (!(readw(&host->reg->clkcon) & (1 << 1))) {
301 printf("%s: timeout error\n", __func__);
309 writew(clk, &host->reg->clkcon);
315 static void mmc_set_ios(struct mmc *mmc)
317 struct mmc_host *host = mmc->priv;
321 debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
330 writel(0x3 << 16, &host->reg->control4);
332 val = readl(&host->reg->control2);
335 val |= (1 << 31) | /* write status clear async mode enable */
336 (1 << 30) | /* command conflict mask enable */
337 (1 << 14) | /* Feedback Clock Enable for Rx Clock */
338 (1 << 8); /* SDCLK hold enable */
340 writel(val, &host->reg->control2);
343 * FCSEL1[15] FCSEL0[7]
344 * FCSel[1:0] : Rx Feedback Clock Delay Control
345 * Inverter delay means10ns delay if SDCLK 50MHz setting
346 * 01 = Delay1 (basic delay)
347 * 11 = Delay2 (basic delay + 2ns)
348 * 00 = Delay3 (inverter delay)
349 * 10 = Delay4 (inverter delay + 2ns)
351 writel(0x8080, &host->reg->control3);
353 mmc_change_clock(host, mmc->clock);
355 ctrl = readb(&host->reg->hostctl);
359 * 0 = Depend on WIDE4
365 if (mmc->bus_width == 8)
367 else if (mmc->bus_width == 4)
374 * 1 = Riging edge output
375 * 0 = Falling edge output
379 writeb(ctrl, &host->reg->hostctl);
382 static void mmc_reset(struct mmc_host *host)
384 unsigned int timeout;
387 * RSTALL[0] : Software reset for all
391 writeb((1 << 0), &host->reg->swrst);
395 /* Wait max 100 ms */
398 /* hw clears the bit when it's done */
399 while (readb(&host->reg->swrst) & (1 << 0)) {
401 printf("%s: timeout error\n", __func__);
409 static int mmc_core_init(struct mmc *mmc)
411 struct mmc_host *host = (struct mmc_host *)mmc->priv;
416 host->version = readw(&host->reg->hcver);
419 writel(0xffffffff, &host->reg->norintstsen);
420 writel(0xffffffff, &host->reg->norintsigen);
422 writeb(0xe, &host->reg->timeoutcon); /* TMCLK * 2^27 */
425 * NORMAL Interrupt Status Enable Register init
426 * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
427 * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
428 * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
429 * [0] ENSTACMDCMPLT : Command Complete Status Enable
431 mask = readl(&host->reg->norintstsen);
433 mask |= (1 << 5) | (1 << 4) | (1 << 1) | (1 << 0);
434 writel(mask, &host->reg->norintstsen);
437 * NORMAL Interrupt Signal Enable Register init
438 * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
440 mask = readl(&host->reg->norintsigen);
443 writel(mask, &host->reg->norintsigen);
448 static int s5p_mmc_initialize(int dev_index, int bus_width)
452 mmc = &mmc_dev[dev_index];
454 sprintf(mmc->name, "SAMSUNG SD/MMC");
455 mmc->priv = &mmc_host[dev_index];
456 mmc->send_cmd = mmc_send_cmd;
457 mmc->set_ios = mmc_set_ios;
458 mmc->init = mmc_core_init;
460 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
462 mmc->host_caps = MMC_MODE_8BIT;
464 mmc->host_caps = MMC_MODE_4BIT;
465 mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
468 mmc->f_max = 52000000;
470 mmc_host[dev_index].dev_index = dev_index;
471 mmc_host[dev_index].clock = 0;
472 mmc_host[dev_index].reg = s5p_get_base_mmc(dev_index);
479 int s5p_mmc_init(int dev_index, int bus_width)
481 return s5p_mmc_initialize(dev_index, bus_width);