]> git.sur5r.net Git - u-boot/blob - drivers/mmc/sdhci.c
Merge branch 'master' of git://git.denx.de/u-boot-cfi-flash
[u-boot] / drivers / mmc / sdhci.c
1 /*
2  * Copyright 2011, Marvell Semiconductor Inc.
3  * Lei Wen <leiwen@marvell.com>
4  *
5  * See file CREDITS for list of people who contributed to this
6  * project.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of
11  * the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21  * MA 02111-1307 USA
22  *
23  * Back ported to the 8xx platform (from the 8260 platform) by
24  * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
25  */
26
27 #include <common.h>
28 #include <malloc.h>
29 #include <mmc.h>
30 #include <sdhci.h>
31
32 void *aligned_buffer;
33
34 static void sdhci_reset(struct sdhci_host *host, u8 mask)
35 {
36         unsigned long timeout;
37
38         /* Wait max 100 ms */
39         timeout = 100;
40         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
41         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
42                 if (timeout == 0) {
43                         printf("Reset 0x%x never completed.\n", (int)mask);
44                         return;
45                 }
46                 timeout--;
47                 udelay(1000);
48         }
49 }
50
51 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
52 {
53         int i;
54         if (cmd->resp_type & MMC_RSP_136) {
55                 /* CRC is stripped so we need to do some shifting. */
56                 for (i = 0; i < 4; i++) {
57                         cmd->response[i] = sdhci_readl(host,
58                                         SDHCI_RESPONSE + (3-i)*4) << 8;
59                         if (i != 3)
60                                 cmd->response[i] |= sdhci_readb(host,
61                                                 SDHCI_RESPONSE + (3-i)*4-1);
62                 }
63         } else {
64                 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
65         }
66 }
67
68 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
69 {
70         int i;
71         char *offs;
72         for (i = 0; i < data->blocksize; i += 4) {
73                 offs = data->dest + i;
74                 if (data->flags == MMC_DATA_READ)
75                         *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
76                 else
77                         sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
78         }
79 }
80
81 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
82                                 unsigned int start_addr)
83 {
84         unsigned int stat, rdy, mask, timeout, block = 0;
85
86         timeout = 10000;
87         rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
88         mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
89         do {
90                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
91                 if (stat & SDHCI_INT_ERROR) {
92                         printf("Error detected in status(0x%X)!\n", stat);
93                         return -1;
94                 }
95                 if (stat & rdy) {
96                         if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
97                                 continue;
98                         sdhci_writel(host, rdy, SDHCI_INT_STATUS);
99                         sdhci_transfer_pio(host, data);
100                         data->dest += data->blocksize;
101                         if (++block >= data->blocks)
102                                 break;
103                 }
104 #ifdef CONFIG_MMC_SDMA
105                 if (stat & SDHCI_INT_DMA_END) {
106                         sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
107                         start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
108                         start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
109                         sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
110                 }
111 #endif
112                 if (timeout-- > 0)
113                         udelay(10);
114                 else {
115                         printf("Transfer data timeout\n");
116                         return -1;
117                 }
118         } while (!(stat & SDHCI_INT_DATA_END));
119         return 0;
120 }
121
122 int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
123                        struct mmc_data *data)
124 {
125         struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
126         unsigned int stat = 0;
127         int ret = 0;
128         int trans_bytes = 0, is_aligned = 1;
129         u32 mask, flags, mode;
130         unsigned int timeout, start_addr = 0;
131         unsigned int retry = 10000;
132
133         /* Wait max 10 ms */
134         timeout = 10;
135
136         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
137         mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
138
139         /* We shouldn't wait for data inihibit for stop commands, even
140            though they might use busy signaling */
141         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
142                 mask &= ~SDHCI_DATA_INHIBIT;
143
144         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
145                 if (timeout == 0) {
146                         printf("Controller never released inhibit bit(s).\n");
147                         return COMM_ERR;
148                 }
149                 timeout--;
150                 udelay(1000);
151         }
152
153         mask = SDHCI_INT_RESPONSE;
154         if (!(cmd->resp_type & MMC_RSP_PRESENT))
155                 flags = SDHCI_CMD_RESP_NONE;
156         else if (cmd->resp_type & MMC_RSP_136)
157                 flags = SDHCI_CMD_RESP_LONG;
158         else if (cmd->resp_type & MMC_RSP_BUSY) {
159                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
160                 mask |= SDHCI_INT_DATA_END;
161         } else
162                 flags = SDHCI_CMD_RESP_SHORT;
163
164         if (cmd->resp_type & MMC_RSP_CRC)
165                 flags |= SDHCI_CMD_CRC;
166         if (cmd->resp_type & MMC_RSP_OPCODE)
167                 flags |= SDHCI_CMD_INDEX;
168         if (data)
169                 flags |= SDHCI_CMD_DATA;
170
171         /*Set Transfer mode regarding to data flag*/
172         if (data != 0) {
173                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
174                 mode = SDHCI_TRNS_BLK_CNT_EN;
175                 trans_bytes = data->blocks * data->blocksize;
176                 if (data->blocks > 1)
177                         mode |= SDHCI_TRNS_MULTI;
178
179                 if (data->flags == MMC_DATA_READ)
180                         mode |= SDHCI_TRNS_READ;
181
182 #ifdef CONFIG_MMC_SDMA
183                 if (data->flags == MMC_DATA_READ)
184                         start_addr = (unsigned int)data->dest;
185                 else
186                         start_addr = (unsigned int)data->src;
187                 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
188                                 (start_addr & 0x7) != 0x0) {
189                         is_aligned = 0;
190                         start_addr = (unsigned int)aligned_buffer;
191                         if (data->flags != MMC_DATA_READ)
192                                 memcpy(aligned_buffer, data->src, trans_bytes);
193                 }
194
195                 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
196                 mode |= SDHCI_TRNS_DMA;
197 #endif
198                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
199                                 data->blocksize),
200                                 SDHCI_BLOCK_SIZE);
201                 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
202                 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
203         }
204
205         sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
206 #ifdef CONFIG_MMC_SDMA
207         flush_cache(start_addr, trans_bytes);
208 #endif
209         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
210         do {
211                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
212                 if (stat & SDHCI_INT_ERROR)
213                         break;
214                 if (--retry == 0)
215                         break;
216         } while ((stat & mask) != mask);
217
218         if (retry == 0) {
219                 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B)
220                         return 0;
221                 else {
222                         printf("Timeout for status update!\n");
223                         return TIMEOUT;
224                 }
225         }
226
227         if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
228                 sdhci_cmd_done(host, cmd);
229                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
230         } else
231                 ret = -1;
232
233         if (!ret && data)
234                 ret = sdhci_transfer_data(host, data, start_addr);
235
236         stat = sdhci_readl(host, SDHCI_INT_STATUS);
237         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
238         if (!ret) {
239                 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
240                                 !is_aligned && (data->flags == MMC_DATA_READ))
241                         memcpy(data->dest, aligned_buffer, trans_bytes);
242                 return 0;
243         }
244
245         sdhci_reset(host, SDHCI_RESET_CMD);
246         sdhci_reset(host, SDHCI_RESET_DATA);
247         if (stat & SDHCI_INT_TIMEOUT)
248                 return TIMEOUT;
249         else
250                 return COMM_ERR;
251 }
252
253 static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
254 {
255         struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
256         unsigned int div, clk, timeout;
257
258         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
259
260         if (clock == 0)
261                 return 0;
262
263         if (host->version >= SDHCI_SPEC_300) {
264                 /* Version 3.00 divisors must be a multiple of 2. */
265                 if (mmc->f_max <= clock)
266                         div = 1;
267                 else {
268                         for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
269                                 if ((mmc->f_max / div) <= clock)
270                                         break;
271                         }
272                 }
273         } else {
274                 /* Version 2.00 divisors must be a power of 2. */
275                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
276                         if ((mmc->f_max / div) <= clock)
277                                 break;
278                 }
279         }
280         div >>= 1;
281
282         clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
283         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
284                 << SDHCI_DIVIDER_HI_SHIFT;
285         clk |= SDHCI_CLOCK_INT_EN;
286         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
287
288         /* Wait max 20 ms */
289         timeout = 20;
290         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
291                 & SDHCI_CLOCK_INT_STABLE)) {
292                 if (timeout == 0) {
293                         printf("Internal clock never stabilised.\n");
294                         return -1;
295                 }
296                 timeout--;
297                 udelay(1000);
298         }
299
300         clk |= SDHCI_CLOCK_CARD_EN;
301         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
302         return 0;
303 }
304
305 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
306 {
307         u8 pwr = 0;
308
309         if (power != (unsigned short)-1) {
310                 switch (1 << power) {
311                 case MMC_VDD_165_195:
312                         pwr = SDHCI_POWER_180;
313                         break;
314                 case MMC_VDD_29_30:
315                 case MMC_VDD_30_31:
316                         pwr = SDHCI_POWER_300;
317                         break;
318                 case MMC_VDD_32_33:
319                 case MMC_VDD_33_34:
320                         pwr = SDHCI_POWER_330;
321                         break;
322                 }
323         }
324
325         if (pwr == 0) {
326                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
327                 return;
328         }
329
330         pwr |= SDHCI_POWER_ON;
331
332         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
333 }
334
335 void sdhci_set_ios(struct mmc *mmc)
336 {
337         u32 ctrl;
338         struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
339
340         if (host->set_control_reg)
341                 host->set_control_reg(host);
342
343         if (mmc->clock != host->clock)
344                 sdhci_set_clock(mmc, mmc->clock);
345
346         /* Set bus width */
347         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
348         if (mmc->bus_width == 8) {
349                 ctrl &= ~SDHCI_CTRL_4BITBUS;
350                 if (host->version >= SDHCI_SPEC_300)
351                         ctrl |= SDHCI_CTRL_8BITBUS;
352         } else {
353                 if (host->version >= SDHCI_SPEC_300)
354                         ctrl &= ~SDHCI_CTRL_8BITBUS;
355                 if (mmc->bus_width == 4)
356                         ctrl |= SDHCI_CTRL_4BITBUS;
357                 else
358                         ctrl &= ~SDHCI_CTRL_4BITBUS;
359         }
360
361         if (mmc->clock > 26000000)
362                 ctrl |= SDHCI_CTRL_HISPD;
363         else
364                 ctrl &= ~SDHCI_CTRL_HISPD;
365
366         if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
367                 ctrl &= ~SDHCI_CTRL_HISPD;
368
369         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
370 }
371
372 int sdhci_init(struct mmc *mmc)
373 {
374         struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
375
376         if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
377                 aligned_buffer = memalign(8, 512*1024);
378                 if (!aligned_buffer) {
379                         printf("Aligned buffer alloc failed!!!");
380                         return -1;
381                 }
382         }
383
384         /* Eable all state */
385         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_ENABLE);
386         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_SIGNAL_ENABLE);
387
388         sdhci_set_power(host, fls(mmc->voltages) - 1);
389
390         return 0;
391 }
392
393 int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
394 {
395         struct mmc *mmc;
396         unsigned int caps;
397
398         mmc = malloc(sizeof(struct mmc));
399         if (!mmc) {
400                 printf("mmc malloc fail!\n");
401                 return -1;
402         }
403
404         mmc->priv = host;
405         host->mmc = mmc;
406
407         sprintf(mmc->name, "%s", host->name);
408         mmc->send_cmd = sdhci_send_command;
409         mmc->set_ios = sdhci_set_ios;
410         mmc->init = sdhci_init;
411         mmc->getcd = NULL;
412
413         caps = sdhci_readl(host, SDHCI_CAPABILITIES);
414 #ifdef CONFIG_MMC_SDMA
415         if (!(caps & SDHCI_CAN_DO_SDMA)) {
416                 printf("Your controller don't support sdma!!\n");
417                 return -1;
418         }
419 #endif
420
421         if (max_clk)
422                 mmc->f_max = max_clk;
423         else {
424                 if (host->version >= SDHCI_SPEC_300)
425                         mmc->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK)
426                                 >> SDHCI_CLOCK_BASE_SHIFT;
427                 else
428                         mmc->f_max = (caps & SDHCI_CLOCK_BASE_MASK)
429                                 >> SDHCI_CLOCK_BASE_SHIFT;
430                 mmc->f_max *= 1000000;
431         }
432         if (mmc->f_max == 0) {
433                 printf("Hardware doesn't specify base clock frequency\n");
434                 return -1;
435         }
436         if (min_clk)
437                 mmc->f_min = min_clk;
438         else {
439                 if (host->version >= SDHCI_SPEC_300)
440                         mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_300;
441                 else
442                         mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_200;
443         }
444
445         mmc->voltages = 0;
446         if (caps & SDHCI_CAN_VDD_330)
447                 mmc->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
448         if (caps & SDHCI_CAN_VDD_300)
449                 mmc->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
450         if (caps & SDHCI_CAN_VDD_180)
451                 mmc->voltages |= MMC_VDD_165_195;
452
453         if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
454                 mmc->voltages |= host->voltages;
455
456         mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
457         if (caps & SDHCI_CAN_DO_8BIT)
458                 mmc->host_caps |= MMC_MODE_8BIT;
459         if (host->host_caps)
460                 mmc->host_caps |= host->host_caps;
461
462         sdhci_reset(host, SDHCI_RESET_ALL);
463         mmc_register(mmc);
464
465         return 0;
466 }