2 * Copyright 2011, Marvell Semiconductor Inc.
3 * Lei Wen <leiwen@marvell.com>
5 * SPDX-License-Identifier: GPL-2.0+
7 * Back ported to the 8xx platform (from the 8260 platform) by
8 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
18 static void sdhci_reset(struct sdhci_host *host, u8 mask)
20 unsigned long timeout;
24 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
25 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
27 printf("Reset 0x%x never completed.\n", (int)mask);
35 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
38 if (cmd->resp_type & MMC_RSP_136) {
39 /* CRC is stripped so we need to do some shifting. */
40 for (i = 0; i < 4; i++) {
41 cmd->response[i] = sdhci_readl(host,
42 SDHCI_RESPONSE + (3-i)*4) << 8;
44 cmd->response[i] |= sdhci_readb(host,
45 SDHCI_RESPONSE + (3-i)*4-1);
48 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
52 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
56 for (i = 0; i < data->blocksize; i += 4) {
57 offs = data->dest + i;
58 if (data->flags == MMC_DATA_READ)
59 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
61 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
65 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
66 unsigned int start_addr)
68 unsigned int stat, rdy, mask, timeout, block = 0;
69 #ifdef CONFIG_MMC_SDMA
71 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
72 ctrl &= ~SDHCI_CTRL_DMA_MASK;
73 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
77 rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
78 mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
80 stat = sdhci_readl(host, SDHCI_INT_STATUS);
81 if (stat & SDHCI_INT_ERROR) {
82 printf("Error detected in status(0x%X)!\n", stat);
86 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
88 sdhci_writel(host, rdy, SDHCI_INT_STATUS);
89 sdhci_transfer_pio(host, data);
90 data->dest += data->blocksize;
91 if (++block >= data->blocks)
94 #ifdef CONFIG_MMC_SDMA
95 if (stat & SDHCI_INT_DMA_END) {
96 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
97 start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
98 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
99 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
105 printf("Transfer data timeout\n");
108 } while (!(stat & SDHCI_INT_DATA_END));
113 * No command will be sent by driver if card is busy, so driver must wait
114 * for card ready state.
115 * Every time when card is busy after timeout then (last) timeout value will be
116 * increased twice but only if it doesn't exceed global defined maximum.
117 * Each function call will use last timeout value. Max timeout can be redefined
118 * in board config file.
120 #ifndef CONFIG_SDHCI_CMD_MAX_TIMEOUT
121 #define CONFIG_SDHCI_CMD_MAX_TIMEOUT 3200
123 #define CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT 100
125 int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
126 struct mmc_data *data)
128 struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
129 unsigned int stat = 0;
131 int trans_bytes = 0, is_aligned = 1;
132 u32 mask, flags, mode;
133 unsigned int time = 0, start_addr = 0;
134 unsigned int retry = 10000;
135 int mmc_dev = mmc->block_dev.dev;
137 /* Timeout unit - ms */
138 static unsigned int cmd_timeout = CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT;
140 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
141 mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
143 /* We shouldn't wait for data inihibit for stop commands, even
144 though they might use busy signaling */
145 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
146 mask &= ~SDHCI_DATA_INHIBIT;
148 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
149 if (time >= cmd_timeout) {
150 printf("MMC: %d busy ", mmc_dev);
151 if (2 * cmd_timeout <= CONFIG_SDHCI_CMD_MAX_TIMEOUT) {
152 cmd_timeout += cmd_timeout;
153 printf("timeout increasing to: %u ms.\n",
164 mask = SDHCI_INT_RESPONSE;
165 if (!(cmd->resp_type & MMC_RSP_PRESENT))
166 flags = SDHCI_CMD_RESP_NONE;
167 else if (cmd->resp_type & MMC_RSP_136)
168 flags = SDHCI_CMD_RESP_LONG;
169 else if (cmd->resp_type & MMC_RSP_BUSY) {
170 flags = SDHCI_CMD_RESP_SHORT_BUSY;
171 mask |= SDHCI_INT_DATA_END;
173 flags = SDHCI_CMD_RESP_SHORT;
175 if (cmd->resp_type & MMC_RSP_CRC)
176 flags |= SDHCI_CMD_CRC;
177 if (cmd->resp_type & MMC_RSP_OPCODE)
178 flags |= SDHCI_CMD_INDEX;
180 flags |= SDHCI_CMD_DATA;
182 /*Set Transfer mode regarding to data flag*/
184 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
185 mode = SDHCI_TRNS_BLK_CNT_EN;
186 trans_bytes = data->blocks * data->blocksize;
187 if (data->blocks > 1)
188 mode |= SDHCI_TRNS_MULTI;
190 if (data->flags == MMC_DATA_READ)
191 mode |= SDHCI_TRNS_READ;
193 #ifdef CONFIG_MMC_SDMA
194 if (data->flags == MMC_DATA_READ)
195 start_addr = (unsigned int)data->dest;
197 start_addr = (unsigned int)data->src;
198 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
199 (start_addr & 0x7) != 0x0) {
201 start_addr = (unsigned int)aligned_buffer;
202 if (data->flags != MMC_DATA_READ)
203 memcpy(aligned_buffer, data->src, trans_bytes);
206 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
207 mode |= SDHCI_TRNS_DMA;
209 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
212 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
213 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
216 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
217 #ifdef CONFIG_MMC_SDMA
218 flush_cache(start_addr, trans_bytes);
220 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
222 stat = sdhci_readl(host, SDHCI_INT_STATUS);
223 if (stat & SDHCI_INT_ERROR)
227 } while ((stat & mask) != mask);
230 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B)
233 printf("Timeout for status update!\n");
238 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
239 sdhci_cmd_done(host, cmd);
240 sdhci_writel(host, mask, SDHCI_INT_STATUS);
245 ret = sdhci_transfer_data(host, data, start_addr);
247 if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
250 stat = sdhci_readl(host, SDHCI_INT_STATUS);
251 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
253 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
254 !is_aligned && (data->flags == MMC_DATA_READ))
255 memcpy(data->dest, aligned_buffer, trans_bytes);
259 sdhci_reset(host, SDHCI_RESET_CMD);
260 sdhci_reset(host, SDHCI_RESET_DATA);
261 if (stat & SDHCI_INT_TIMEOUT)
267 static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
269 struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
270 unsigned int div, clk, timeout;
272 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
277 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
278 /* Version 3.00 divisors must be a multiple of 2. */
279 if (mmc->f_max <= clock)
282 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
283 if ((mmc->f_max / div) <= clock)
288 /* Version 2.00 divisors must be a power of 2. */
289 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
290 if ((mmc->f_max / div) <= clock)
297 host->set_clock(host->index, div);
299 clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
300 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
301 << SDHCI_DIVIDER_HI_SHIFT;
302 clk |= SDHCI_CLOCK_INT_EN;
303 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
307 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
308 & SDHCI_CLOCK_INT_STABLE)) {
310 printf("Internal clock never stabilised.\n");
317 clk |= SDHCI_CLOCK_CARD_EN;
318 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
322 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
326 if (power != (unsigned short)-1) {
327 switch (1 << power) {
328 case MMC_VDD_165_195:
329 pwr = SDHCI_POWER_180;
333 pwr = SDHCI_POWER_300;
337 pwr = SDHCI_POWER_330;
343 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
347 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
348 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
350 pwr |= SDHCI_POWER_ON;
352 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
355 void sdhci_set_ios(struct mmc *mmc)
358 struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
360 if (host->set_control_reg)
361 host->set_control_reg(host);
363 if (mmc->clock != host->clock)
364 sdhci_set_clock(mmc, mmc->clock);
367 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
368 if (mmc->bus_width == 8) {
369 ctrl &= ~SDHCI_CTRL_4BITBUS;
370 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
371 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
372 ctrl |= SDHCI_CTRL_8BITBUS;
374 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
375 ctrl &= ~SDHCI_CTRL_8BITBUS;
376 if (mmc->bus_width == 4)
377 ctrl |= SDHCI_CTRL_4BITBUS;
379 ctrl &= ~SDHCI_CTRL_4BITBUS;
382 if (mmc->clock > 26000000)
383 ctrl |= SDHCI_CTRL_HISPD;
385 ctrl &= ~SDHCI_CTRL_HISPD;
387 if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
388 ctrl &= ~SDHCI_CTRL_HISPD;
390 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
393 int sdhci_init(struct mmc *mmc)
395 struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
397 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
398 aligned_buffer = memalign(8, 512*1024);
399 if (!aligned_buffer) {
400 printf("Aligned buffer alloc failed!!!");
405 sdhci_set_power(host, fls(mmc->voltages) - 1);
407 if (host->quirks & SDHCI_QUIRK_NO_CD) {
410 sdhci_writel(host, SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST,
413 status = sdhci_readl(host, SDHCI_PRESENT_STATE);
414 while ((!(status & SDHCI_CARD_PRESENT)) ||
415 (!(status & SDHCI_CARD_STATE_STABLE)) ||
416 (!(status & SDHCI_CARD_DETECT_PIN_LEVEL)))
417 status = sdhci_readl(host, SDHCI_PRESENT_STATE);
420 /* Enable only interrupts served by the SD controller */
421 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK
423 /* Mask all sdhci interrupt sources */
424 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
429 int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
434 mmc = malloc(sizeof(struct mmc));
436 printf("mmc malloc fail!\n");
443 sprintf(mmc->name, "%s", host->name);
444 mmc->send_cmd = sdhci_send_command;
445 mmc->set_ios = sdhci_set_ios;
446 mmc->init = sdhci_init;
450 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
451 #ifdef CONFIG_MMC_SDMA
452 if (!(caps & SDHCI_CAN_DO_SDMA)) {
453 printf("Your controller don't support sdma!!\n");
459 mmc->f_max = max_clk;
461 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
462 mmc->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK)
463 >> SDHCI_CLOCK_BASE_SHIFT;
465 mmc->f_max = (caps & SDHCI_CLOCK_BASE_MASK)
466 >> SDHCI_CLOCK_BASE_SHIFT;
467 mmc->f_max *= 1000000;
469 if (mmc->f_max == 0) {
470 printf("Hardware doesn't specify base clock frequency\n");
474 mmc->f_min = min_clk;
476 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
477 mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_300;
479 mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_200;
483 if (caps & SDHCI_CAN_VDD_330)
484 mmc->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
485 if (caps & SDHCI_CAN_VDD_300)
486 mmc->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
487 if (caps & SDHCI_CAN_VDD_180)
488 mmc->voltages |= MMC_VDD_165_195;
490 if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
491 mmc->voltages |= host->voltages;
493 mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
494 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
495 if (caps & SDHCI_CAN_DO_8BIT)
496 mmc->host_caps |= MMC_MODE_8BIT;
499 mmc->host_caps |= host->host_caps;
501 sdhci_reset(host, SDHCI_RESET_ALL);