git.sur5r.net Git - u-boot/blob - drivers/mmc/sdhci.c

   1 /*
   2  * Copyright 2011, Marvell Semiconductor Inc.
   3  * Lei Wen <leiwen@marvell.com>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  *
  23  * Back ported to the 8xx platform (from the 8260 platform) by
  24  * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
  25  */
  26
  27 #include <common.h>
  28 #include <malloc.h>
  29 #include <mmc.h>
  30 #include <sdhci.h>
  31
  32 void *aligned_buffer;
  33
  34 static void sdhci_reset(struct sdhci_host *host, u8 mask)
  35 {
  36         unsigned long timeout;
  37
  38         /* Wait max 100 ms */
  39         timeout = 100;
  40         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
  41         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
  42                 if (timeout == 0) {
  43                         printf("Reset 0x%x never completed.\n", (int)mask);
  44                         return;
  45                 }
  46                 timeout--;
  47                 udelay(1000);
  48         }
  49 }
  50
  51 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
  52 {
  53         int i;
  54         if (cmd->resp_type & MMC_RSP_136) {
  55                 /* CRC is stripped so we need to do some shifting. */
  56                 for (i = 0; i < 4; i++) {
  57                         cmd->response[i] = sdhci_readl(host,
  58                                         SDHCI_RESPONSE + (3-i)*4) << 8;
  59                         if (i != 3)
  60                                 cmd->response[i] |= sdhci_readb(host,
  61                                                 SDHCI_RESPONSE + (3-i)*4-1);
  62                 }
  63         } else {
  64                 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
  65         }
  66 }
  67
  68 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
  69 {
  70         int i;
  71         char *offs;
  72         for (i = 0; i < data->blocksize; i += 4) {
  73                 offs = data->dest + i;
  74                 if (data->flags == MMC_DATA_READ)
  75                         *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
  76                 else
  77                         sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
  78         }
  79 }
  80
  81 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
  82                                 unsigned int start_addr)
  83 {
  84         unsigned int stat, rdy, mask, block = 0;
  85
  86         rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
  87         mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
  88         do {
  89                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
  90                 if (stat & SDHCI_INT_ERROR) {
  91                         printf("Error detected in status(0x%X)!\n", stat);
  92                         return -1;
  93                 }
  94                 if (stat & rdy) {
  95                         if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
  96                                 continue;
  97                         sdhci_writel(host, rdy, SDHCI_INT_STATUS);
  98                         sdhci_transfer_pio(host, data);
  99                         data->dest += data->blocksize;
 100                         if (++block >= data->blocks)
 101                                 break;
 102                 }
 103 #ifdef CONFIG_MMC_SDMA
 104                 if (stat & SDHCI_INT_DMA_END) {
 105                         sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
 106                         start_addr &= SDHCI_DEFAULT_BOUNDARY_SIZE - 1;
 107                         start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
 108                         sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
 109                 }
 110 #endif
 111         } while (!(stat & SDHCI_INT_DATA_END));
 112         return 0;
 113 }
 114
 115 int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 116                        struct mmc_data *data)
 117 {
 118         struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
 119         unsigned int stat = 0;
 120         int ret = 0;
 121         int trans_bytes = 0, is_aligned = 1;
 122         u32 mask, flags, mode;
 123         unsigned int timeout, start_addr = 0;
 124
 125         /* Wait max 10 ms */
 126         timeout = 10;
 127
 128         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 129         mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
 130
 131         /* We shouldn't wait for data inihibit for stop commands, even
 132            though they might use busy signaling */
 133         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 134                 mask &= ~SDHCI_DATA_INHIBIT;
 135
 136         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 137                 if (timeout == 0) {
 138                         printf("Controller never released inhibit bit(s).\n");
 139                         return COMM_ERR;
 140                 }
 141                 timeout--;
 142                 udelay(1000);
 143         }
 144
 145         mask = SDHCI_INT_RESPONSE;
 146         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 147                 flags = SDHCI_CMD_RESP_NONE;
 148         else if (cmd->resp_type & MMC_RSP_136)
 149                 flags = SDHCI_CMD_RESP_LONG;
 150         else if (cmd->resp_type & MMC_RSP_BUSY) {
 151                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 152                 mask |= SDHCI_INT_DATA_END;
 153         } else
 154                 flags = SDHCI_CMD_RESP_SHORT;
 155
 156         if (cmd->resp_type & MMC_RSP_CRC)
 157                 flags |= SDHCI_CMD_CRC;
 158         if (cmd->resp_type & MMC_RSP_OPCODE)
 159                 flags |= SDHCI_CMD_INDEX;
 160         if (data)
 161                 flags |= SDHCI_CMD_DATA;
 162
 163         /*Set Transfer mode regarding to data flag*/
 164         if (data != 0) {
 165                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 166                 mode = SDHCI_TRNS_BLK_CNT_EN;
 167                 trans_bytes = data->blocks * data->blocksize;
 168                 if (data->blocks > 1)
 169                         mode |= SDHCI_TRNS_MULTI;
 170
 171                 if (data->flags == MMC_DATA_READ)
 172                         mode |= SDHCI_TRNS_READ;
 173
 174 #ifdef CONFIG_MMC_SDMA
 175                 if (data->flags == MMC_DATA_READ)
 176                         start_addr = (unsigned int)data->dest;
 177                 else
 178                         start_addr = (unsigned int)data->src;
 179                 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
 180                                 (start_addr & 0x7) != 0x0) {
 181                         is_aligned = 0;
 182                         start_addr = (unsigned int)aligned_buffer;
 183                         if (data->flags != MMC_DATA_READ)
 184                                 memcpy(aligned_buffer, data->src, trans_bytes);
 185                 }
 186
 187                 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
 188                 mode |= SDHCI_TRNS_DMA;
 189 #endif
 190                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 191                                 data->blocksize),
 192                                 SDHCI_BLOCK_SIZE);
 193                 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 194                 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 195         }
 196
 197         sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
 198 #ifdef CONFIG_MMC_SDMA
 199         flush_cache(start_addr, trans_bytes);
 200 #endif
 201         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
 202         do {
 203                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
 204                 if (stat & SDHCI_INT_ERROR)
 205                         break;
 206         } while ((stat & mask) != mask);
 207
 208         if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
 209                 sdhci_cmd_done(host, cmd);
 210                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
 211         } else
 212                 ret = -1;
 213
 214         if (!ret && data)
 215                 ret = sdhci_transfer_data(host, data, start_addr);
 216
 217         stat = sdhci_readl(host, SDHCI_INT_STATUS);
 218         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 219         if (!ret) {
 220                 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
 221                                 !is_aligned && (data->flags == MMC_DATA_READ))
 222                         memcpy(data->dest, aligned_buffer, trans_bytes);
 223                 return 0;
 224         }
 225
 226         sdhci_reset(host, SDHCI_RESET_CMD);
 227         sdhci_reset(host, SDHCI_RESET_DATA);
 228         if (stat & SDHCI_INT_TIMEOUT)
 229                 return TIMEOUT;
 230         else
 231                 return COMM_ERR;
 232 }
 233
 234 static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
 235 {
 236         struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
 237         unsigned int div, clk, timeout;
 238
 239         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 240
 241         if (clock == 0)
 242                 return 0;
 243
 244         if (host->version >= SDHCI_SPEC_300) {
 245                 /* Version 3.00 divisors must be a multiple of 2. */
 246                 if (mmc->f_max <= clock)
 247                         div = 1;
 248                 else {
 249                         for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
 250                                 if ((mmc->f_max / div) <= clock)
 251                                         break;
 252                         }
 253                 }
 254         } else {
 255                 /* Version 2.00 divisors must be a power of 2. */
 256                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
 257                         if ((mmc->f_max / div) <= clock)
 258                                 break;
 259                 }
 260         }
 261         div >>= 1;
 262
 263         clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
 264         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
 265                 << SDHCI_DIVIDER_HI_SHIFT;
 266         clk |= SDHCI_CLOCK_INT_EN;
 267         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 268
 269         /* Wait max 20 ms */
 270         timeout = 20;
 271         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
 272                 & SDHCI_CLOCK_INT_STABLE)) {
 273                 if (timeout == 0) {
 274                         printf("Internal clock never stabilised.\n");
 275                         return -1;
 276                 }
 277                 timeout--;
 278                 udelay(1000);
 279         }
 280
 281         clk |= SDHCI_CLOCK_CARD_EN;
 282         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 283         return 0;
 284 }
 285
 286 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 287 {
 288         u8 pwr = 0;
 289
 290         if (power != (unsigned short)-1) {
 291                 switch (1 << power) {
 292                 case MMC_VDD_165_195:
 293                         pwr = SDHCI_POWER_180;
 294                         break;
 295                 case MMC_VDD_29_30:
 296                 case MMC_VDD_30_31:
 297                         pwr = SDHCI_POWER_300;
 298                         break;
 299                 case MMC_VDD_32_33:
 300                 case MMC_VDD_33_34:
 301                         pwr = SDHCI_POWER_330;
 302                         break;
 303                 }
 304         }
 305
 306         if (pwr == 0) {
 307                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
 308                 return;
 309         }
 310
 311         pwr |= SDHCI_POWER_ON;
 312
 313         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
 314 }
 315
 316 void sdhci_set_ios(struct mmc *mmc)
 317 {
 318         u32 ctrl;
 319         struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
 320
 321         if (mmc->clock != host->clock)
 322                 sdhci_set_clock(mmc, mmc->clock);
 323
 324         /* Set bus width */
 325         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 326         if (mmc->bus_width == 8) {
 327                 ctrl &= ~SDHCI_CTRL_4BITBUS;
 328                 if (host->version >= SDHCI_SPEC_300)
 329                         ctrl |= SDHCI_CTRL_8BITBUS;
 330         } else {
 331                 if (host->version >= SDHCI_SPEC_300)
 332                         ctrl &= ~SDHCI_CTRL_8BITBUS;
 333                 if (mmc->bus_width == 4)
 334                         ctrl |= SDHCI_CTRL_4BITBUS;
 335                 else
 336                         ctrl &= ~SDHCI_CTRL_4BITBUS;
 337         }
 338
 339         if (mmc->clock > 26000000)
 340                 ctrl |= SDHCI_CTRL_HISPD;
 341         else
 342                 ctrl &= ~SDHCI_CTRL_HISPD;
 343
 344         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 345 }
 346
 347 int sdhci_init(struct mmc *mmc)
 348 {
 349         struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
 350
 351         if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
 352                 aligned_buffer = memalign(8, 512*1024);
 353                 if (!aligned_buffer) {
 354                         printf("Aligned buffer alloc failed!!!");
 355                         return -1;
 356                 }
 357         }
 358
 359         /* Eable all state */
 360         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_ENABLE);
 361         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_SIGNAL_ENABLE);
 362
 363         sdhci_set_power(host, fls(mmc->voltages) - 1);
 364
 365         return 0;
 366 }
 367
 368 int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
 369 {
 370         struct mmc *mmc;
 371         unsigned int caps;
 372
 373         mmc = malloc(sizeof(struct mmc));
 374         if (!mmc) {
 375                 printf("mmc malloc fail!\n");
 376                 return -1;
 377         }
 378
 379         mmc->priv = host;
 380
 381         sprintf(mmc->name, "%s", host->name);
 382         mmc->send_cmd = sdhci_send_command;
 383         mmc->set_ios = sdhci_set_ios;
 384         mmc->init = sdhci_init;
 385
 386         caps = sdhci_readl(host, SDHCI_CAPABILITIES);
 387 #ifdef CONFIG_MMC_SDMA
 388         if (!(caps & SDHCI_CAN_DO_SDMA)) {
 389                 printf("Your controller don't support sdma!!\n");
 390                 return -1;
 391         }
 392 #endif
 393
 394         if (max_clk)
 395                 mmc->f_max = max_clk;
 396         else {
 397                 if (host->version >= SDHCI_SPEC_300)
 398                         mmc->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK)
 399                                 >> SDHCI_CLOCK_BASE_SHIFT;
 400                 else
 401                         mmc->f_max = (caps & SDHCI_CLOCK_BASE_MASK)
 402                                 >> SDHCI_CLOCK_BASE_SHIFT;
 403                 mmc->f_max *= 1000000;
 404         }
 405         if (mmc->f_max == 0) {
 406                 printf("Hardware doesn't specify base clock frequency\n");
 407                 return -1;
 408         }
 409         if (min_clk)
 410                 mmc->f_min = min_clk;
 411         else {
 412                 if (host->version >= SDHCI_SPEC_300)
 413                         mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_300;
 414                 else
 415                         mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_200;
 416         }
 417
 418         mmc->voltages = 0;
 419         if (caps & SDHCI_CAN_VDD_330)
 420                 mmc->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
 421         if (caps & SDHCI_CAN_VDD_300)
 422                 mmc->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
 423         if (caps & SDHCI_CAN_VDD_180)
 424                 mmc->voltages |= MMC_VDD_165_195;
 425         mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
 426         if (caps & SDHCI_CAN_DO_8BIT)
 427                 mmc->host_caps |= MMC_MODE_8BIT;
 428
 429         sdhci_reset(host, SDHCI_RESET_ALL);
 430         mmc_register(mmc);
 431
 432         return 0;
 433 }