git.sur5r.net Git - u-boot/blob - drivers/mmc/sdhci.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2011, Marvell Semiconductor Inc.
   4  * Lei Wen <leiwen@marvell.com>
   5  *
   6  * Back ported to the 8xx platform (from the 8260 platform) by
   7  * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
   8  */
   9
  10 #include <common.h>
  11 #include <errno.h>
  12 #include <malloc.h>
  13 #include <mmc.h>
  14 #include <sdhci.h>
  15
  16 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
  17 void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
  18 #else
  19 void *aligned_buffer;
  20 #endif
  21
  22 static void sdhci_reset(struct sdhci_host *host, u8 mask)
  23 {
  24         unsigned long timeout;
  25
  26         /* Wait max 100 ms */
  27         timeout = 100;
  28         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
  29         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
  30                 if (timeout == 0) {
  31                         printf("%s: Reset 0x%x never completed.\n",
  32                                __func__, (int)mask);
  33                         return;
  34                 }
  35                 timeout--;
  36                 udelay(1000);
  37         }
  38 }
  39
  40 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
  41 {
  42         int i;
  43         if (cmd->resp_type & MMC_RSP_136) {
  44                 /* CRC is stripped so we need to do some shifting. */
  45                 for (i = 0; i < 4; i++) {
  46                         cmd->response[i] = sdhci_readl(host,
  47                                         SDHCI_RESPONSE + (3-i)*4) << 8;
  48                         if (i != 3)
  49                                 cmd->response[i] |= sdhci_readb(host,
  50                                                 SDHCI_RESPONSE + (3-i)*4-1);
  51                 }
  52         } else {
  53                 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
  54         }
  55 }
  56
  57 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
  58 {
  59         int i;
  60         char *offs;
  61         for (i = 0; i < data->blocksize; i += 4) {
  62                 offs = data->dest + i;
  63                 if (data->flags == MMC_DATA_READ)
  64                         *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
  65                 else
  66                         sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
  67         }
  68 }
  69
  70 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
  71                                 unsigned int start_addr)
  72 {
  73         unsigned int stat, rdy, mask, timeout, block = 0;
  74         bool transfer_done = false;
  75 #ifdef CONFIG_MMC_SDHCI_SDMA
  76         unsigned char ctrl;
  77         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
  78         ctrl &= ~SDHCI_CTRL_DMA_MASK;
  79         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
  80 #endif
  81
  82         timeout = 1000000;
  83         rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
  84         mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
  85         do {
  86                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
  87                 if (stat & SDHCI_INT_ERROR) {
  88                         pr_debug("%s: Error detected in status(0x%X)!\n",
  89                                  __func__, stat);
  90                         return -EIO;
  91                 }
  92                 if (!transfer_done && (stat & rdy)) {
  93                         if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
  94                                 continue;
  95                         sdhci_writel(host, rdy, SDHCI_INT_STATUS);
  96                         sdhci_transfer_pio(host, data);
  97                         data->dest += data->blocksize;
  98                         if (++block >= data->blocks) {
  99                                 /* Keep looping until the SDHCI_INT_DATA_END is
 100                                  * cleared, even if we finished sending all the
 101                                  * blocks.
 102                                  */
 103                                 transfer_done = true;
 104                                 continue;
 105                         }
 106                 }
 107 #ifdef CONFIG_MMC_SDHCI_SDMA
 108                 if (!transfer_done && (stat & SDHCI_INT_DMA_END)) {
 109                         sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
 110                         start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
 111                         start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
 112                         sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
 113                 }
 114 #endif
 115                 if (timeout-- > 0)
 116                         udelay(10);
 117                 else {
 118                         printf("%s: Transfer data timeout\n", __func__);
 119                         return -ETIMEDOUT;
 120                 }
 121         } while (!(stat & SDHCI_INT_DATA_END));
 122         return 0;
 123 }
 124
 125 /*
 126  * No command will be sent by driver if card is busy, so driver must wait
 127  * for card ready state.
 128  * Every time when card is busy after timeout then (last) timeout value will be
 129  * increased twice but only if it doesn't exceed global defined maximum.
 130  * Each function call will use last timeout value.
 131  */
 132 #define SDHCI_CMD_MAX_TIMEOUT                   3200
 133 #define SDHCI_CMD_DEFAULT_TIMEOUT               100
 134 #define SDHCI_READ_STATUS_TIMEOUT               1000
 135
 136 #ifdef CONFIG_DM_MMC
 137 static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
 138                               struct mmc_data *data)
 139 {
 140         struct mmc *mmc = mmc_get_mmc_dev(dev);
 141
 142 #else
 143 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 144                               struct mmc_data *data)
 145 {
 146 #endif
 147         struct sdhci_host *host = mmc->priv;
 148         unsigned int stat = 0;
 149         int ret = 0;
 150         int trans_bytes = 0, is_aligned = 1;
 151         u32 mask, flags, mode;
 152         unsigned int time = 0, start_addr = 0;
 153         int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
 154         unsigned start = get_timer(0);
 155
 156         /* Timeout unit - ms */
 157         static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
 158
 159         mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
 160
 161         /* We shouldn't wait for data inihibit for stop commands, even
 162            though they might use busy signaling */
 163         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 164                 mask &= ~SDHCI_DATA_INHIBIT;
 165
 166         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 167                 if (time >= cmd_timeout) {
 168                         printf("%s: MMC: %d busy ", __func__, mmc_dev);
 169                         if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
 170                                 cmd_timeout += cmd_timeout;
 171                                 printf("timeout increasing to: %u ms.\n",
 172                                        cmd_timeout);
 173                         } else {
 174                                 puts("timeout.\n");
 175                                 return -ECOMM;
 176                         }
 177                 }
 178                 time++;
 179                 udelay(1000);
 180         }
 181
 182         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 183
 184         mask = SDHCI_INT_RESPONSE;
 185         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 186                 flags = SDHCI_CMD_RESP_NONE;
 187         else if (cmd->resp_type & MMC_RSP_136)
 188                 flags = SDHCI_CMD_RESP_LONG;
 189         else if (cmd->resp_type & MMC_RSP_BUSY) {
 190                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 191                 if (data)
 192                         mask |= SDHCI_INT_DATA_END;
 193         } else
 194                 flags = SDHCI_CMD_RESP_SHORT;
 195
 196         if (cmd->resp_type & MMC_RSP_CRC)
 197                 flags |= SDHCI_CMD_CRC;
 198         if (cmd->resp_type & MMC_RSP_OPCODE)
 199                 flags |= SDHCI_CMD_INDEX;
 200         if (data)
 201                 flags |= SDHCI_CMD_DATA;
 202
 203         /* Set Transfer mode regarding to data flag */
 204         if (data) {
 205                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 206                 mode = SDHCI_TRNS_BLK_CNT_EN;
 207                 trans_bytes = data->blocks * data->blocksize;
 208                 if (data->blocks > 1)
 209                         mode |= SDHCI_TRNS_MULTI;
 210
 211                 if (data->flags == MMC_DATA_READ)
 212                         mode |= SDHCI_TRNS_READ;
 213
 214 #ifdef CONFIG_MMC_SDHCI_SDMA
 215                 if (data->flags == MMC_DATA_READ)
 216                         start_addr = (unsigned long)data->dest;
 217                 else
 218                         start_addr = (unsigned long)data->src;
 219                 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
 220                                 (start_addr & 0x7) != 0x0) {
 221                         is_aligned = 0;
 222                         start_addr = (unsigned long)aligned_buffer;
 223                         if (data->flags != MMC_DATA_READ)
 224                                 memcpy(aligned_buffer, data->src, trans_bytes);
 225                 }
 226
 227 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
 228                 /*
 229                  * Always use this bounce-buffer when
 230                  * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
 231                  */
 232                 is_aligned = 0;
 233                 start_addr = (unsigned long)aligned_buffer;
 234                 if (data->flags != MMC_DATA_READ)
 235                         memcpy(aligned_buffer, data->src, trans_bytes);
 236 #endif
 237
 238                 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
 239                 mode |= SDHCI_TRNS_DMA;
 240 #endif
 241                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 242                                 data->blocksize),
 243                                 SDHCI_BLOCK_SIZE);
 244                 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 245                 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 246         } else if (cmd->resp_type & MMC_RSP_BUSY) {
 247                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 248         }
 249
 250         sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
 251 #ifdef CONFIG_MMC_SDHCI_SDMA
 252         if (data) {
 253                 trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE);
 254                 flush_cache(start_addr, trans_bytes);
 255         }
 256 #endif
 257         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
 258         start = get_timer(0);
 259         do {
 260                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
 261                 if (stat & SDHCI_INT_ERROR)
 262                         break;
 263
 264                 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
 265                         if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
 266                                 return 0;
 267                         } else {
 268                                 printf("%s: Timeout for status update!\n",
 269                                        __func__);
 270                                 return -ETIMEDOUT;
 271                         }
 272                 }
 273         } while ((stat & mask) != mask);
 274
 275         if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
 276                 sdhci_cmd_done(host, cmd);
 277                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
 278         } else
 279                 ret = -1;
 280
 281         if (!ret && data)
 282                 ret = sdhci_transfer_data(host, data, start_addr);
 283
 284         if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
 285                 udelay(1000);
 286
 287         stat = sdhci_readl(host, SDHCI_INT_STATUS);
 288         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 289         if (!ret) {
 290                 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
 291                                 !is_aligned && (data->flags == MMC_DATA_READ))
 292                         memcpy(data->dest, aligned_buffer, trans_bytes);
 293                 return 0;
 294         }
 295
 296         sdhci_reset(host, SDHCI_RESET_CMD);
 297         sdhci_reset(host, SDHCI_RESET_DATA);
 298         if (stat & SDHCI_INT_TIMEOUT)
 299                 return -ETIMEDOUT;
 300         else
 301                 return -ECOMM;
 302 }
 303
 304 static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
 305 {
 306         struct sdhci_host *host = mmc->priv;
 307         unsigned int div, clk = 0, timeout;
 308
 309         /* Wait max 20 ms */
 310         timeout = 200;
 311         while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
 312                            (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
 313                 if (timeout == 0) {
 314                         printf("%s: Timeout to wait cmd & data inhibit\n",
 315                                __func__);
 316                         return -EBUSY;
 317                 }
 318
 319                 timeout--;
 320                 udelay(100);
 321         }
 322
 323         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 324
 325         if (clock == 0)
 326                 return 0;
 327
 328         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 329                 /*
 330                  * Check if the Host Controller supports Programmable Clock
 331                  * Mode.
 332                  */
 333                 if (host->clk_mul) {
 334                         for (div = 1; div <= 1024; div++) {
 335                                 if ((host->max_clk / div) <= clock)
 336                                         break;
 337                         }
 338
 339                         /*
 340                          * Set Programmable Clock Mode in the Clock
 341                          * Control register.
 342                          */
 343                         clk = SDHCI_PROG_CLOCK_MODE;
 344                         div--;
 345                 } else {
 346                         /* Version 3.00 divisors must be a multiple of 2. */
 347                         if (host->max_clk <= clock) {
 348                                 div = 1;
 349                         } else {
 350                                 for (div = 2;
 351                                      div < SDHCI_MAX_DIV_SPEC_300;
 352                                      div += 2) {
 353                                         if ((host->max_clk / div) <= clock)
 354                                                 break;
 355                                 }
 356                         }
 357                         div >>= 1;
 358                 }
 359         } else {
 360                 /* Version 2.00 divisors must be a power of 2. */
 361                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
 362                         if ((host->max_clk / div) <= clock)
 363                                 break;
 364                 }
 365                 div >>= 1;
 366         }
 367
 368         if (host->ops && host->ops->set_clock)
 369                 host->ops->set_clock(host, div);
 370
 371         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
 372         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
 373                 << SDHCI_DIVIDER_HI_SHIFT;
 374         clk |= SDHCI_CLOCK_INT_EN;
 375         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 376
 377         /* Wait max 20 ms */
 378         timeout = 20;
 379         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
 380                 & SDHCI_CLOCK_INT_STABLE)) {
 381                 if (timeout == 0) {
 382                         printf("%s: Internal clock never stabilised.\n",
 383                                __func__);
 384                         return -EBUSY;
 385                 }
 386                 timeout--;
 387                 udelay(1000);
 388         }
 389
 390         clk |= SDHCI_CLOCK_CARD_EN;
 391         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 392         return 0;
 393 }
 394
 395 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 396 {
 397         u8 pwr = 0;
 398
 399         if (power != (unsigned short)-1) {
 400                 switch (1 << power) {
 401                 case MMC_VDD_165_195:
 402                         pwr = SDHCI_POWER_180;
 403                         break;
 404                 case MMC_VDD_29_30:
 405                 case MMC_VDD_30_31:
 406                         pwr = SDHCI_POWER_300;
 407                         break;
 408                 case MMC_VDD_32_33:
 409                 case MMC_VDD_33_34:
 410                         pwr = SDHCI_POWER_330;
 411                         break;
 412                 }
 413         }
 414
 415         if (pwr == 0) {
 416                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
 417                 return;
 418         }
 419
 420         pwr |= SDHCI_POWER_ON;
 421
 422         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
 423 }
 424
 425 #ifdef CONFIG_DM_MMC
 426 static int sdhci_set_ios(struct udevice *dev)
 427 {
 428         struct mmc *mmc = mmc_get_mmc_dev(dev);
 429 #else
 430 static int sdhci_set_ios(struct mmc *mmc)
 431 {
 432 #endif
 433         u32 ctrl;
 434         struct sdhci_host *host = mmc->priv;
 435
 436         if (host->ops && host->ops->set_control_reg)
 437                 host->ops->set_control_reg(host);
 438
 439         if (mmc->clock != host->clock)
 440                 sdhci_set_clock(mmc, mmc->clock);
 441
 442         /* Set bus width */
 443         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 444         if (mmc->bus_width == 8) {
 445                 ctrl &= ~SDHCI_CTRL_4BITBUS;
 446                 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
 447                                 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
 448                         ctrl |= SDHCI_CTRL_8BITBUS;
 449         } else {
 450                 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
 451                                 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
 452                         ctrl &= ~SDHCI_CTRL_8BITBUS;
 453                 if (mmc->bus_width == 4)
 454                         ctrl |= SDHCI_CTRL_4BITBUS;
 455                 else
 456                         ctrl &= ~SDHCI_CTRL_4BITBUS;
 457         }
 458
 459         if (mmc->clock > 26000000)
 460                 ctrl |= SDHCI_CTRL_HISPD;
 461         else
 462                 ctrl &= ~SDHCI_CTRL_HISPD;
 463
 464         if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
 465             (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE))
 466                 ctrl &= ~SDHCI_CTRL_HISPD;
 467
 468         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 469
 470         /* If available, call the driver specific "post" set_ios() function */
 471         if (host->ops && host->ops->set_ios_post)
 472                 host->ops->set_ios_post(host);
 473
 474         return 0;
 475 }
 476
 477 static int sdhci_init(struct mmc *mmc)
 478 {
 479         struct sdhci_host *host = mmc->priv;
 480
 481         sdhci_reset(host, SDHCI_RESET_ALL);
 482
 483         if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
 484                 aligned_buffer = memalign(8, 512*1024);
 485                 if (!aligned_buffer) {
 486                         printf("%s: Aligned buffer alloc failed!!!\n",
 487                                __func__);
 488                         return -ENOMEM;
 489                 }
 490         }
 491
 492         sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
 493
 494         if (host->ops && host->ops->get_cd)
 495                 host->ops->get_cd(host);
 496
 497         /* Enable only interrupts served by the SD controller */
 498         sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
 499                      SDHCI_INT_ENABLE);
 500         /* Mask all sdhci interrupt sources */
 501         sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
 502
 503         return 0;
 504 }
 505
 506 #ifdef CONFIG_DM_MMC
 507 int sdhci_probe(struct udevice *dev)
 508 {
 509         struct mmc *mmc = mmc_get_mmc_dev(dev);
 510
 511         return sdhci_init(mmc);
 512 }
 513
 514 const struct dm_mmc_ops sdhci_ops = {
 515         .send_cmd       = sdhci_send_command,
 516         .set_ios        = sdhci_set_ios,
 517 };
 518 #else
 519 static const struct mmc_ops sdhci_ops = {
 520         .send_cmd       = sdhci_send_command,
 521         .set_ios        = sdhci_set_ios,
 522         .init           = sdhci_init,
 523 };
 524 #endif
 525
 526 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
 527                 u32 f_max, u32 f_min)
 528 {
 529         u32 caps, caps_1;
 530
 531         caps = sdhci_readl(host, SDHCI_CAPABILITIES);
 532
 533 #ifdef CONFIG_MMC_SDHCI_SDMA
 534         if (!(caps & SDHCI_CAN_DO_SDMA)) {
 535                 printf("%s: Your controller doesn't support SDMA!!\n",
 536                        __func__);
 537                 return -EINVAL;
 538         }
 539 #endif
 540         if (host->quirks & SDHCI_QUIRK_REG32_RW)
 541                 host->version =
 542                         sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
 543         else
 544                 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
 545
 546         cfg->name = host->name;
 547 #ifndef CONFIG_DM_MMC
 548         cfg->ops = &sdhci_ops;
 549 #endif
 550
 551         /* Check whether the clock multiplier is supported or not */
 552         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 553                 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
 554                 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
 555                                 SDHCI_CLOCK_MUL_SHIFT;
 556         }
 557
 558         if (host->max_clk == 0) {
 559                 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 560                         host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
 561                                 SDHCI_CLOCK_BASE_SHIFT;
 562                 else
 563                         host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
 564                                 SDHCI_CLOCK_BASE_SHIFT;
 565                 host->max_clk *= 1000000;
 566                 if (host->clk_mul)
 567                         host->max_clk *= host->clk_mul;
 568         }
 569         if (host->max_clk == 0) {
 570                 printf("%s: Hardware doesn't specify base clock frequency\n",
 571                        __func__);
 572                 return -EINVAL;
 573         }
 574         if (f_max && (f_max < host->max_clk))
 575                 cfg->f_max = f_max;
 576         else
 577                 cfg->f_max = host->max_clk;
 578         if (f_min)
 579                 cfg->f_min = f_min;
 580         else {
 581                 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 582                         cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
 583                 else
 584                         cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
 585         }
 586         cfg->voltages = 0;
 587         if (caps & SDHCI_CAN_VDD_330)
 588                 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
 589         if (caps & SDHCI_CAN_VDD_300)
 590                 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
 591         if (caps & SDHCI_CAN_VDD_180)
 592                 cfg->voltages |= MMC_VDD_165_195;
 593
 594         if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
 595                 cfg->voltages |= host->voltages;
 596
 597         cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
 598
 599         /* Since Host Controller Version3.0 */
 600         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 601                 if (!(caps & SDHCI_CAN_DO_8BIT))
 602                         cfg->host_caps &= ~MMC_MODE_8BIT;
 603         }
 604
 605         if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
 606                 cfg->host_caps &= ~MMC_MODE_HS;
 607                 cfg->host_caps &= ~MMC_MODE_HS_52MHz;
 608         }
 609
 610         if (host->host_caps)
 611                 cfg->host_caps |= host->host_caps;
 612
 613         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 614
 615         return 0;
 616 }
 617
 618 #ifdef CONFIG_BLK
 619 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
 620 {
 621         return mmc_bind(dev, mmc, cfg);
 622 }
 623 #else
 624 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
 625 {
 626         int ret;
 627
 628         ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
 629         if (ret)
 630                 return ret;
 631
 632         host->mmc = mmc_create(&host->cfg, host);
 633         if (host->mmc == NULL) {
 634                 printf("%s: mmc create fail!\n", __func__);
 635                 return -ENOMEM;
 636         }
 637
 638         return 0;
 639 }
 640 #endif