2 * (C) Copyright 2013 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/dwmmc.h>
11 #include <asm/arch/clock_manager.h>
12 #include <asm/arch/system_manager.h>
14 static const struct socfpga_clock_manager *clock_manager_base =
15 (void *)SOCFPGA_CLKMGR_ADDRESS;
16 static const struct socfpga_system_manager *system_manager_base =
17 (void *)SOCFPGA_SYSMGR_ADDRESS;
19 static void socfpga_dwmci_clksel(struct dwmci_host *host)
24 /* Disable SDMMC clock. */
25 clrbits_le32(&clock_manager_base->per_pll.en,
26 CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
28 /* Configures drv_sel and smpl_sel */
29 drvsel = CONFIG_SOCFPGA_DWMMC_DRVSEL;
30 smplsel = CONFIG_SOCFPGA_DWMMC_SMPSEL;
32 debug("%s: drvsel %d smplsel %d\n", __func__, drvsel, smplsel);
33 writel(SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel),
34 &system_manager_base->sdmmcgrp_ctrl);
36 debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
37 readl(&system_manager_base->sdmmcgrp_ctrl));
39 /* Enable SDMMC clock */
40 setbits_le32(&clock_manager_base->per_pll.en,
41 CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
44 int socfpga_dwmmc_init(u32 regbase, int bus_width, int index)
46 struct dwmci_host *host;
48 /* calloc for zero init */
49 host = calloc(sizeof(struct dwmci_host), 1);
51 printf("dwmci_host calloc fail!\n");
55 host->name = "SOCFPGA DWMMC";
56 host->ioaddr = (void *)regbase;
57 host->buswidth = bus_width;
58 host->clksel = socfpga_dwmci_clksel;
59 host->dev_index = index;
60 /* fixed clock divide by 4 which due to the SDMMC wrapper */
61 host->bus_hz = CONFIG_SOCFPGA_DWMMC_BUS_HZ;
62 host->fifoth_val = MSIZE(0x2) |
63 RX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2 - 1) |
64 TX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2);
66 return add_dwmci(host, host->bus_hz, 400000);