2 * (C) Copyright 2013 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/dwmmc.h>
14 #include <asm/arch/clock_manager.h>
15 #include <asm/arch/system_manager.h>
17 static const struct socfpga_clock_manager *clock_manager_base =
18 (void *)SOCFPGA_CLKMGR_ADDRESS;
19 static const struct socfpga_system_manager *system_manager_base =
20 (void *)SOCFPGA_SYSMGR_ADDRESS;
22 /* socfpga implmentation specific drver private data */
23 struct dwmci_socfpga_priv_data {
28 static void socfpga_dwmci_clksel(struct dwmci_host *host)
30 struct dwmci_socfpga_priv_data *priv = host->priv;
32 /* Disable SDMMC clock. */
33 clrbits_le32(&clock_manager_base->per_pll.en,
34 CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
36 debug("%s: drvsel %d smplsel %d\n", __func__,
37 priv->drvsel, priv->smplsel);
38 writel(SYSMGR_SDMMC_CTRL_SET(priv->smplsel, priv->drvsel),
39 &system_manager_base->sdmmcgrp_ctrl);
41 debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
42 readl(&system_manager_base->sdmmcgrp_ctrl));
44 /* Enable SDMMC clock */
45 setbits_le32(&clock_manager_base->per_pll.en,
46 CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
49 static int socfpga_dwmci_of_probe(const void *blob, int node, const int idx)
51 /* FIXME: probe from DT eventually too/ */
52 const unsigned long clk = cm_get_mmc_controller_clk_hz();
54 struct dwmci_host *host;
55 struct dwmci_socfpga_priv_data *priv;
57 int bus_width, fifo_depth;
60 printf("DWMMC%d: MMC clock is zero!", idx);
64 /* Get the register address from the device node */
65 reg_base = fdtdec_get_addr(blob, node, "reg");
67 printf("DWMMC%d: Can't get base address\n", idx);
71 /* Get the bus width from the device node */
72 bus_width = fdtdec_get_int(blob, node, "bus-width", 0);
74 printf("DWMMC%d: Can't get bus-width\n", idx);
78 fifo_depth = fdtdec_get_int(blob, node, "fifo-depth", 0);
80 printf("DWMMC%d: Can't get FIFO depth\n", idx);
84 /* Allocate the host */
85 host = calloc(1, sizeof(*host));
89 /* Allocate the priv */
90 priv = calloc(1, sizeof(*priv));
96 host->name = "SOCFPGA DWMMC";
97 host->ioaddr = (void *)reg_base;
98 host->buswidth = bus_width;
99 host->clksel = socfpga_dwmci_clksel;
100 host->dev_index = idx;
101 /* Fixed clock divide by 4 which due to the SDMMC wrapper */
103 host->fifoth_val = MSIZE(0x2) |
104 RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
105 priv->drvsel = fdtdec_get_uint(blob, node, "drvsel", 3);
106 priv->smplsel = fdtdec_get_uint(blob, node, "smplsel", 0);
109 return add_dwmci(host, host->bus_hz, 400000);
112 static int socfpga_dwmci_process_node(const void *blob, int nodes[],
117 for (i = 0; i < count; i++) {
122 ret = socfpga_dwmci_of_probe(blob, node, i);
124 printf("%s: failed to decode dev %d\n", __func__, i);
131 int socfpga_dwmmc_init(const void *blob)
133 int nodes[2]; /* Max. two controllers. */
136 count = fdtdec_find_aliases_for_id(blob, "mmc",
137 COMPAT_ALTERA_SOCFPGA_DWMMC,
138 nodes, ARRAY_SIZE(nodes));
140 ret = socfpga_dwmci_process_node(blob, nodes, count);