git.sur5r.net Git - u-boot/blob - drivers/mmc/stm32_sdmmc2.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   4  * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <dm.h>
  10 #include <fdtdec.h>
  11 #include <linux/libfdt.h>
  12 #include <mmc.h>
  13 #include <reset.h>
  14 #include <asm/io.h>
  15 #include <asm/gpio.h>
  16 #include <linux/iopoll.h>
  17
  18 struct stm32_sdmmc2_plat {
  19         struct mmc_config cfg;
  20         struct mmc mmc;
  21 };
  22
  23 struct stm32_sdmmc2_priv {
  24         fdt_addr_t base;
  25         struct clk clk;
  26         struct reset_ctl reset_ctl;
  27         struct gpio_desc cd_gpio;
  28         u32 clk_reg_msk;
  29         u32 pwr_reg_msk;
  30 };
  31
  32 struct stm32_sdmmc2_ctx {
  33         u32 cache_start;
  34         u32 cache_end;
  35         u32 data_length;
  36         bool dpsm_abort;
  37 };
  38
  39 /* SDMMC REGISTERS OFFSET */
  40 #define SDMMC_POWER             0x00    /* SDMMC power control             */
  41 #define SDMMC_CLKCR             0x04    /* SDMMC clock control             */
  42 #define SDMMC_ARG               0x08    /* SDMMC argument                  */
  43 #define SDMMC_CMD               0x0C    /* SDMMC command                   */
  44 #define SDMMC_RESP1             0x14    /* SDMMC response 1                */
  45 #define SDMMC_RESP2             0x18    /* SDMMC response 2                */
  46 #define SDMMC_RESP3             0x1C    /* SDMMC response 3                */
  47 #define SDMMC_RESP4             0x20    /* SDMMC response 4                */
  48 #define SDMMC_DTIMER            0x24    /* SDMMC data timer                */
  49 #define SDMMC_DLEN              0x28    /* SDMMC data length               */
  50 #define SDMMC_DCTRL             0x2C    /* SDMMC data control              */
  51 #define SDMMC_DCOUNT            0x30    /* SDMMC data counter              */
  52 #define SDMMC_STA               0x34    /* SDMMC status                    */
  53 #define SDMMC_ICR               0x38    /* SDMMC interrupt clear           */
  54 #define SDMMC_MASK              0x3C    /* SDMMC mask                      */
  55 #define SDMMC_IDMACTRL          0x50    /* SDMMC DMA control               */
  56 #define SDMMC_IDMABASE0         0x58    /* SDMMC DMA buffer 0 base address */
  57
  58 /* SDMMC_POWER register */
  59 #define SDMMC_POWER_PWRCTRL             GENMASK(1, 0)
  60 #define SDMMC_POWER_VSWITCH             BIT(2)
  61 #define SDMMC_POWER_VSWITCHEN           BIT(3)
  62 #define SDMMC_POWER_DIRPOL              BIT(4)
  63
  64 /* SDMMC_CLKCR register */
  65 #define SDMMC_CLKCR_CLKDIV              GENMASK(9, 0)
  66 #define SDMMC_CLKCR_CLKDIV_MAX          SDMMC_CLKCR_CLKDIV
  67 #define SDMMC_CLKCR_PWRSAV              BIT(12)
  68 #define SDMMC_CLKCR_WIDBUS_4            BIT(14)
  69 #define SDMMC_CLKCR_WIDBUS_8            BIT(15)
  70 #define SDMMC_CLKCR_NEGEDGE             BIT(16)
  71 #define SDMMC_CLKCR_HWFC_EN             BIT(17)
  72 #define SDMMC_CLKCR_DDR                 BIT(18)
  73 #define SDMMC_CLKCR_BUSSPEED            BIT(19)
  74 #define SDMMC_CLKCR_SELCLKRX_MASK       GENMASK(21, 20)
  75 #define SDMMC_CLKCR_SELCLKRX_CK         0
  76 #define SDMMC_CLKCR_SELCLKRX_CKIN       BIT(20)
  77 #define SDMMC_CLKCR_SELCLKRX_FBCK       BIT(21)
  78
  79 /* SDMMC_CMD register */
  80 #define SDMMC_CMD_CMDINDEX              GENMASK(5, 0)
  81 #define SDMMC_CMD_CMDTRANS              BIT(6)
  82 #define SDMMC_CMD_CMDSTOP               BIT(7)
  83 #define SDMMC_CMD_WAITRESP              GENMASK(9, 8)
  84 #define SDMMC_CMD_WAITRESP_0            BIT(8)
  85 #define SDMMC_CMD_WAITRESP_1            BIT(9)
  86 #define SDMMC_CMD_WAITINT               BIT(10)
  87 #define SDMMC_CMD_WAITPEND              BIT(11)
  88 #define SDMMC_CMD_CPSMEN                BIT(12)
  89 #define SDMMC_CMD_DTHOLD                BIT(13)
  90 #define SDMMC_CMD_BOOTMODE              BIT(14)
  91 #define SDMMC_CMD_BOOTEN                BIT(15)
  92 #define SDMMC_CMD_CMDSUSPEND            BIT(16)
  93
  94 /* SDMMC_DCTRL register */
  95 #define SDMMC_DCTRL_DTEN                BIT(0)
  96 #define SDMMC_DCTRL_DTDIR               BIT(1)
  97 #define SDMMC_DCTRL_DTMODE              GENMASK(3, 2)
  98 #define SDMMC_DCTRL_DBLOCKSIZE          GENMASK(7, 4)
  99 #define SDMMC_DCTRL_DBLOCKSIZE_SHIFT    4
 100 #define SDMMC_DCTRL_RWSTART             BIT(8)
 101 #define SDMMC_DCTRL_RWSTOP              BIT(9)
 102 #define SDMMC_DCTRL_RWMOD               BIT(10)
 103 #define SDMMC_DCTRL_SDMMCEN             BIT(11)
 104 #define SDMMC_DCTRL_BOOTACKEN           BIT(12)
 105 #define SDMMC_DCTRL_FIFORST             BIT(13)
 106
 107 /* SDMMC_STA register */
 108 #define SDMMC_STA_CCRCFAIL              BIT(0)
 109 #define SDMMC_STA_DCRCFAIL              BIT(1)
 110 #define SDMMC_STA_CTIMEOUT              BIT(2)
 111 #define SDMMC_STA_DTIMEOUT              BIT(3)
 112 #define SDMMC_STA_TXUNDERR              BIT(4)
 113 #define SDMMC_STA_RXOVERR               BIT(5)
 114 #define SDMMC_STA_CMDREND               BIT(6)
 115 #define SDMMC_STA_CMDSENT               BIT(7)
 116 #define SDMMC_STA_DATAEND               BIT(8)
 117 #define SDMMC_STA_DHOLD                 BIT(9)
 118 #define SDMMC_STA_DBCKEND               BIT(10)
 119 #define SDMMC_STA_DABORT                BIT(11)
 120 #define SDMMC_STA_DPSMACT               BIT(12)
 121 #define SDMMC_STA_CPSMACT               BIT(13)
 122 #define SDMMC_STA_TXFIFOHE              BIT(14)
 123 #define SDMMC_STA_RXFIFOHF              BIT(15)
 124 #define SDMMC_STA_TXFIFOF               BIT(16)
 125 #define SDMMC_STA_RXFIFOF               BIT(17)
 126 #define SDMMC_STA_TXFIFOE               BIT(18)
 127 #define SDMMC_STA_RXFIFOE               BIT(19)
 128 #define SDMMC_STA_BUSYD0                BIT(20)
 129 #define SDMMC_STA_BUSYD0END             BIT(21)
 130 #define SDMMC_STA_SDMMCIT               BIT(22)
 131 #define SDMMC_STA_ACKFAIL               BIT(23)
 132 #define SDMMC_STA_ACKTIMEOUT            BIT(24)
 133 #define SDMMC_STA_VSWEND                BIT(25)
 134 #define SDMMC_STA_CKSTOP                BIT(26)
 135 #define SDMMC_STA_IDMATE                BIT(27)
 136 #define SDMMC_STA_IDMABTC               BIT(28)
 137
 138 /* SDMMC_ICR register */
 139 #define SDMMC_ICR_CCRCFAILC             BIT(0)
 140 #define SDMMC_ICR_DCRCFAILC             BIT(1)
 141 #define SDMMC_ICR_CTIMEOUTC             BIT(2)
 142 #define SDMMC_ICR_DTIMEOUTC             BIT(3)
 143 #define SDMMC_ICR_TXUNDERRC             BIT(4)
 144 #define SDMMC_ICR_RXOVERRC              BIT(5)
 145 #define SDMMC_ICR_CMDRENDC              BIT(6)
 146 #define SDMMC_ICR_CMDSENTC              BIT(7)
 147 #define SDMMC_ICR_DATAENDC              BIT(8)
 148 #define SDMMC_ICR_DHOLDC                BIT(9)
 149 #define SDMMC_ICR_DBCKENDC              BIT(10)
 150 #define SDMMC_ICR_DABORTC               BIT(11)
 151 #define SDMMC_ICR_BUSYD0ENDC            BIT(21)
 152 #define SDMMC_ICR_SDMMCITC              BIT(22)
 153 #define SDMMC_ICR_ACKFAILC              BIT(23)
 154 #define SDMMC_ICR_ACKTIMEOUTC           BIT(24)
 155 #define SDMMC_ICR_VSWENDC               BIT(25)
 156 #define SDMMC_ICR_CKSTOPC               BIT(26)
 157 #define SDMMC_ICR_IDMATEC               BIT(27)
 158 #define SDMMC_ICR_IDMABTCC              BIT(28)
 159 #define SDMMC_ICR_STATIC_FLAGS          ((GENMASK(28, 21)) | (GENMASK(11, 0)))
 160
 161 /* SDMMC_MASK register */
 162 #define SDMMC_MASK_CCRCFAILIE           BIT(0)
 163 #define SDMMC_MASK_DCRCFAILIE           BIT(1)
 164 #define SDMMC_MASK_CTIMEOUTIE           BIT(2)
 165 #define SDMMC_MASK_DTIMEOUTIE           BIT(3)
 166 #define SDMMC_MASK_TXUNDERRIE           BIT(4)
 167 #define SDMMC_MASK_RXOVERRIE            BIT(5)
 168 #define SDMMC_MASK_CMDRENDIE            BIT(6)
 169 #define SDMMC_MASK_CMDSENTIE            BIT(7)
 170 #define SDMMC_MASK_DATAENDIE            BIT(8)
 171 #define SDMMC_MASK_DHOLDIE              BIT(9)
 172 #define SDMMC_MASK_DBCKENDIE            BIT(10)
 173 #define SDMMC_MASK_DABORTIE             BIT(11)
 174 #define SDMMC_MASK_TXFIFOHEIE           BIT(14)
 175 #define SDMMC_MASK_RXFIFOHFIE           BIT(15)
 176 #define SDMMC_MASK_RXFIFOFIE            BIT(17)
 177 #define SDMMC_MASK_TXFIFOEIE            BIT(18)
 178 #define SDMMC_MASK_BUSYD0ENDIE          BIT(21)
 179 #define SDMMC_MASK_SDMMCITIE            BIT(22)
 180 #define SDMMC_MASK_ACKFAILIE            BIT(23)
 181 #define SDMMC_MASK_ACKTIMEOUTIE         BIT(24)
 182 #define SDMMC_MASK_VSWENDIE             BIT(25)
 183 #define SDMMC_MASK_CKSTOPIE             BIT(26)
 184 #define SDMMC_MASK_IDMABTCIE            BIT(28)
 185
 186 /* SDMMC_IDMACTRL register */
 187 #define SDMMC_IDMACTRL_IDMAEN           BIT(0)
 188
 189 #define SDMMC_CMD_TIMEOUT               0xFFFFFFFF
 190
 191 static void stm32_sdmmc2_start_data(struct stm32_sdmmc2_priv *priv,
 192                                     struct mmc_data *data,
 193                                     struct stm32_sdmmc2_ctx *ctx)
 194 {
 195         u32 data_ctrl, idmabase0;
 196
 197         /* Configure the SDMMC DPSM (Data Path State Machine) */
 198         data_ctrl = (__ilog2(data->blocksize) <<
 199                      SDMMC_DCTRL_DBLOCKSIZE_SHIFT) &
 200                     SDMMC_DCTRL_DBLOCKSIZE;
 201
 202         if (data->flags & MMC_DATA_READ) {
 203                 data_ctrl |= SDMMC_DCTRL_DTDIR;
 204                 idmabase0 = (u32)data->dest;
 205         } else {
 206                 idmabase0 = (u32)data->src;
 207         }
 208
 209         /* Set the SDMMC Data TimeOut value */
 210         writel(SDMMC_CMD_TIMEOUT, priv->base + SDMMC_DTIMER);
 211
 212         /* Set the SDMMC DataLength value */
 213         writel(ctx->data_length, priv->base + SDMMC_DLEN);
 214
 215         /* Write to SDMMC DCTRL */
 216         writel(data_ctrl, priv->base + SDMMC_DCTRL);
 217
 218         /* Cache align */
 219         ctx->cache_start = rounddown(idmabase0, ARCH_DMA_MINALIGN);
 220         ctx->cache_end = roundup(idmabase0 + ctx->data_length,
 221                                  ARCH_DMA_MINALIGN);
 222
 223         /*
 224          * Flush data cache before DMA start (clean and invalidate)
 225          * Clean also needed for read
 226          * Avoid issue on buffer not cached-aligned
 227          */
 228         flush_dcache_range(ctx->cache_start, ctx->cache_end);
 229
 230         /* Enable internal DMA */
 231         writel(idmabase0, priv->base + SDMMC_IDMABASE0);
 232         writel(SDMMC_IDMACTRL_IDMAEN, priv->base + SDMMC_IDMACTRL);
 233 }
 234
 235 static void stm32_sdmmc2_start_cmd(struct stm32_sdmmc2_priv *priv,
 236                                    struct mmc_cmd *cmd, u32 cmd_param)
 237 {
 238         if (readl(priv->base + SDMMC_CMD) & SDMMC_CMD_CPSMEN)
 239                 writel(0, priv->base + SDMMC_CMD);
 240
 241         cmd_param |= cmd->cmdidx | SDMMC_CMD_CPSMEN;
 242         if (cmd->resp_type & MMC_RSP_PRESENT) {
 243                 if (cmd->resp_type & MMC_RSP_136)
 244                         cmd_param |= SDMMC_CMD_WAITRESP;
 245                 else if (cmd->resp_type & MMC_RSP_CRC)
 246                         cmd_param |= SDMMC_CMD_WAITRESP_0;
 247                 else
 248                         cmd_param |= SDMMC_CMD_WAITRESP_1;
 249         }
 250
 251         /* Clear flags */
 252         writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
 253
 254         /* Set SDMMC argument value */
 255         writel(cmd->cmdarg, priv->base + SDMMC_ARG);
 256
 257         /* Set SDMMC command parameters */
 258         writel(cmd_param, priv->base + SDMMC_CMD);
 259 }
 260
 261 static int stm32_sdmmc2_end_cmd(struct stm32_sdmmc2_priv *priv,
 262                                 struct mmc_cmd *cmd,
 263                                 struct stm32_sdmmc2_ctx *ctx)
 264 {
 265         u32 mask = SDMMC_STA_CTIMEOUT;
 266         u32 status;
 267         int ret;
 268
 269         if (cmd->resp_type & MMC_RSP_PRESENT) {
 270                 mask |= SDMMC_STA_CMDREND;
 271                 if (cmd->resp_type & MMC_RSP_CRC)
 272                         mask |= SDMMC_STA_CCRCFAIL;
 273         } else {
 274                 mask |= SDMMC_STA_CMDSENT;
 275         }
 276
 277         /* Polling status register */
 278         ret = readl_poll_timeout(priv->base + SDMMC_STA, status, status & mask,
 279                                  10000);
 280
 281         if (ret < 0) {
 282                 debug("%s: timeout reading SDMMC_STA register\n", __func__);
 283                 ctx->dpsm_abort = true;
 284                 return ret;
 285         }
 286
 287         /* Check status */
 288         if (status & SDMMC_STA_CTIMEOUT) {
 289                 debug("%s: error SDMMC_STA_CTIMEOUT (0x%x) for cmd %d\n",
 290                       __func__, status, cmd->cmdidx);
 291                 ctx->dpsm_abort = true;
 292                 return -ETIMEDOUT;
 293         }
 294
 295         if (status & SDMMC_STA_CCRCFAIL && cmd->resp_type & MMC_RSP_CRC) {
 296                 debug("%s: error SDMMC_STA_CCRCFAIL (0x%x) for cmd %d\n",
 297                       __func__, status, cmd->cmdidx);
 298                 ctx->dpsm_abort = true;
 299                 return -EILSEQ;
 300         }
 301
 302         if (status & SDMMC_STA_CMDREND && cmd->resp_type & MMC_RSP_PRESENT) {
 303                 cmd->response[0] = readl(priv->base + SDMMC_RESP1);
 304                 if (cmd->resp_type & MMC_RSP_136) {
 305                         cmd->response[1] = readl(priv->base + SDMMC_RESP2);
 306                         cmd->response[2] = readl(priv->base + SDMMC_RESP3);
 307                         cmd->response[3] = readl(priv->base + SDMMC_RESP4);
 308                 }
 309         }
 310
 311         return 0;
 312 }
 313
 314 static int stm32_sdmmc2_end_data(struct stm32_sdmmc2_priv *priv,
 315                                  struct mmc_cmd *cmd,
 316                                  struct mmc_data *data,
 317                                  struct stm32_sdmmc2_ctx *ctx)
 318 {
 319         u32 mask = SDMMC_STA_DCRCFAIL | SDMMC_STA_DTIMEOUT |
 320                    SDMMC_STA_IDMATE | SDMMC_STA_DATAEND;
 321         u32 status;
 322
 323         if (data->flags & MMC_DATA_READ)
 324                 mask |= SDMMC_STA_RXOVERR;
 325         else
 326                 mask |= SDMMC_STA_TXUNDERR;
 327
 328         status = readl(priv->base + SDMMC_STA);
 329         while (!(status & mask))
 330                 status = readl(priv->base + SDMMC_STA);
 331
 332         /*
 333          * Need invalidate the dcache again to avoid any
 334          * cache-refill during the DMA operations (pre-fetching)
 335          */
 336         if (data->flags & MMC_DATA_READ)
 337                 invalidate_dcache_range(ctx->cache_start, ctx->cache_end);
 338
 339         if (status & SDMMC_STA_DCRCFAIL) {
 340                 debug("%s: error SDMMC_STA_DCRCFAIL (0x%x) for cmd %d\n",
 341                       __func__, status, cmd->cmdidx);
 342                 if (readl(priv->base + SDMMC_DCOUNT))
 343                         ctx->dpsm_abort = true;
 344                 return -EILSEQ;
 345         }
 346
 347         if (status & SDMMC_STA_DTIMEOUT) {
 348                 debug("%s: error SDMMC_STA_DTIMEOUT (0x%x) for cmd %d\n",
 349                       __func__, status, cmd->cmdidx);
 350                 ctx->dpsm_abort = true;
 351                 return -ETIMEDOUT;
 352         }
 353
 354         if (status & SDMMC_STA_TXUNDERR) {
 355                 debug("%s: error SDMMC_STA_TXUNDERR (0x%x) for cmd %d\n",
 356                       __func__, status, cmd->cmdidx);
 357                 ctx->dpsm_abort = true;
 358                 return -EIO;
 359         }
 360
 361         if (status & SDMMC_STA_RXOVERR) {
 362                 debug("%s: error SDMMC_STA_RXOVERR (0x%x) for cmd %d\n",
 363                       __func__, status, cmd->cmdidx);
 364                 ctx->dpsm_abort = true;
 365                 return -EIO;
 366         }
 367
 368         if (status & SDMMC_STA_IDMATE) {
 369                 debug("%s: error SDMMC_STA_IDMATE (0x%x) for cmd %d\n",
 370                       __func__, status, cmd->cmdidx);
 371                 ctx->dpsm_abort = true;
 372                 return -EIO;
 373         }
 374
 375         return 0;
 376 }
 377
 378 static int stm32_sdmmc2_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 379                                  struct mmc_data *data)
 380 {
 381         struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
 382         struct stm32_sdmmc2_ctx ctx;
 383         u32 cmdat = data ? SDMMC_CMD_CMDTRANS : 0;
 384         int ret, retry = 3;
 385
 386 retry_cmd:
 387         ctx.data_length = 0;
 388         ctx.dpsm_abort = false;
 389
 390         if (data) {
 391                 ctx.data_length = data->blocks * data->blocksize;
 392                 stm32_sdmmc2_start_data(priv, data, &ctx);
 393         }
 394
 395         stm32_sdmmc2_start_cmd(priv, cmd, cmdat);
 396
 397         debug("%s: send cmd %d data: 0x%x @ 0x%x\n",
 398               __func__, cmd->cmdidx,
 399               data ? ctx.data_length : 0, (unsigned int)data);
 400
 401         ret = stm32_sdmmc2_end_cmd(priv, cmd, &ctx);
 402
 403         if (data && !ret)
 404                 ret = stm32_sdmmc2_end_data(priv, cmd, data, &ctx);
 405
 406         /* Clear flags */
 407         writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
 408         if (data)
 409                 writel(0x0, priv->base + SDMMC_IDMACTRL);
 410
 411         /*
 412          * To stop Data Path State Machine, a stop_transmission command
 413          * shall be send on cmd or data errors.
 414          */
 415         if (ctx.dpsm_abort && (cmd->cmdidx != MMC_CMD_STOP_TRANSMISSION)) {
 416                 struct mmc_cmd stop_cmd;
 417
 418                 stop_cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
 419                 stop_cmd.cmdarg = 0;
 420                 stop_cmd.resp_type = MMC_RSP_R1b;
 421
 422                 debug("%s: send STOP command to abort dpsm treatments\n",
 423                       __func__);
 424
 425                 stm32_sdmmc2_start_cmd(priv, &stop_cmd, SDMMC_CMD_CMDSTOP);
 426                 stm32_sdmmc2_end_cmd(priv, &stop_cmd, &ctx);
 427
 428                 writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
 429         }
 430
 431         if ((ret != -ETIMEDOUT) && (ret != 0) && retry) {
 432                 printf("%s: cmd %d failed, retrying ...\n",
 433                        __func__, cmd->cmdidx);
 434                 retry--;
 435                 goto retry_cmd;
 436         }
 437
 438         debug("%s: end for CMD %d, ret = %d\n", __func__, cmd->cmdidx, ret);
 439
 440         return ret;
 441 }
 442
 443 static void stm32_sdmmc2_pwron(struct stm32_sdmmc2_priv *priv)
 444 {
 445         /* Reset */
 446         reset_assert(&priv->reset_ctl);
 447         udelay(2);
 448         reset_deassert(&priv->reset_ctl);
 449
 450         udelay(1000);
 451
 452         /* Set Power State to ON */
 453         writel(SDMMC_POWER_PWRCTRL | priv->pwr_reg_msk, priv->base + SDMMC_POWER);
 454
 455         /*
 456          * 1ms: required power up waiting time before starting the
 457          * SD initialization sequence
 458          */
 459         udelay(1000);
 460 }
 461
 462 #define IS_RISING_EDGE(reg) (reg & SDMMC_CLKCR_NEGEDGE ? 0 : 1)
 463 static int stm32_sdmmc2_set_ios(struct udevice *dev)
 464 {
 465         struct mmc *mmc = mmc_get_mmc_dev(dev);
 466         struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
 467         struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
 468         struct mmc_config *cfg = &plat->cfg;
 469         u32 desired = mmc->clock;
 470         u32 sys_clock = clk_get_rate(&priv->clk);
 471         u32 clk = 0;
 472
 473         debug("%s: bus_with = %d, clock = %d\n", __func__,
 474               mmc->bus_width, mmc->clock);
 475
 476         if ((mmc->bus_width == 1) && (desired == cfg->f_min))
 477                 stm32_sdmmc2_pwron(priv);
 478
 479         /*
 480          * clk_div = 0 => command and data generated on SDMMCCLK falling edge
 481          * clk_div > 0 and NEGEDGE = 0 => command and data generated on
 482          * SDMMCCLK rising edge
 483          * clk_div > 0 and NEGEDGE = 1 => command and data generated on
 484          * SDMMCCLK falling edge
 485          */
 486         if (desired && ((sys_clock > desired) ||
 487                         IS_RISING_EDGE(priv->clk_reg_msk))) {
 488                 clk = DIV_ROUND_UP(sys_clock, 2 * desired);
 489                 if (clk > SDMMC_CLKCR_CLKDIV_MAX)
 490                         clk = SDMMC_CLKCR_CLKDIV_MAX;
 491         }
 492
 493         if (mmc->bus_width == 4)
 494                 clk |= SDMMC_CLKCR_WIDBUS_4;
 495         if (mmc->bus_width == 8)
 496                 clk |= SDMMC_CLKCR_WIDBUS_8;
 497
 498         writel(clk | priv->clk_reg_msk | SDMMC_CLKCR_HWFC_EN,
 499                priv->base + SDMMC_CLKCR);
 500
 501         return 0;
 502 }
 503
 504 static int stm32_sdmmc2_getcd(struct udevice *dev)
 505 {
 506         struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
 507
 508         debug("stm32_sdmmc2_getcd called\n");
 509
 510         if (dm_gpio_is_valid(&priv->cd_gpio))
 511                 return dm_gpio_get_value(&priv->cd_gpio);
 512
 513         return 1;
 514 }
 515
 516 static const struct dm_mmc_ops stm32_sdmmc2_ops = {
 517         .send_cmd = stm32_sdmmc2_send_cmd,
 518         .set_ios = stm32_sdmmc2_set_ios,
 519         .get_cd = stm32_sdmmc2_getcd,
 520 };
 521
 522 static int stm32_sdmmc2_probe(struct udevice *dev)
 523 {
 524         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 525         struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
 526         struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
 527         struct mmc_config *cfg = &plat->cfg;
 528         int ret;
 529
 530         priv->base = dev_read_addr(dev);
 531         if (priv->base == FDT_ADDR_T_NONE)
 532                 return -EINVAL;
 533
 534         if (dev_read_bool(dev, "st,negedge"))
 535                 priv->clk_reg_msk |= SDMMC_CLKCR_NEGEDGE;
 536         if (dev_read_bool(dev, "st,dirpol"))
 537                 priv->pwr_reg_msk |= SDMMC_POWER_DIRPOL;
 538         if (dev_read_bool(dev, "st,pin-ckin"))
 539                 priv->clk_reg_msk |= SDMMC_CLKCR_SELCLKRX_CKIN;
 540
 541         ret = clk_get_by_index(dev, 0, &priv->clk);
 542         if (ret)
 543                 return ret;
 544
 545         ret = clk_enable(&priv->clk);
 546         if (ret)
 547                 goto clk_free;
 548
 549         ret = reset_get_by_index(dev, 0, &priv->reset_ctl);
 550         if (ret)
 551                 goto clk_disable;
 552
 553         gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
 554                              GPIOD_IS_IN);
 555
 556         cfg->f_min = 400000;
 557         cfg->f_max = dev_read_u32_default(dev, "max-frequency", 52000000);
 558         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 559         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 560         cfg->name = "STM32 SDMMC2";
 561
 562         cfg->host_caps = 0;
 563         if (cfg->f_max > 25000000)
 564                 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 565
 566         switch (dev_read_u32_default(dev, "bus-width", 1)) {
 567         case 8:
 568                 cfg->host_caps |= MMC_MODE_8BIT;
 569         case 4:
 570                 cfg->host_caps |= MMC_MODE_4BIT;
 571                 break;
 572         case 1:
 573                 break;
 574         default:
 575                 pr_err("invalid \"bus-width\" property, force to 1\n");
 576         }
 577
 578         upriv->mmc = &plat->mmc;
 579
 580         return 0;
 581
 582 clk_disable:
 583         clk_disable(&priv->clk);
 584 clk_free:
 585         clk_free(&priv->clk);
 586
 587         return ret;
 588 }
 589
 590 int stm32_sdmmc_bind(struct udevice *dev)
 591 {
 592         struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
 593
 594         return mmc_bind(dev, &plat->mmc, &plat->cfg);
 595 }
 596
 597 static const struct udevice_id stm32_sdmmc2_ids[] = {
 598         { .compatible = "st,stm32-sdmmc2" },
 599         { }
 600 };
 601
 602 U_BOOT_DRIVER(stm32_sdmmc2) = {
 603         .name = "stm32_sdmmc2",
 604         .id = UCLASS_MMC,
 605         .of_match = stm32_sdmmc2_ids,
 606         .ops = &stm32_sdmmc2_ops,
 607         .probe = stm32_sdmmc2_probe,
 608         .bind = stm32_sdmmc_bind,
 609         .priv_auto_alloc_size = sizeof(struct stm32_sdmmc2_priv),
 610         .platdata_auto_alloc_size = sizeof(struct stm32_sdmmc2_plat),
 611 };