2 * (C) Copyright 2007-2011
3 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
4 * Aaron <leafy.myeh@allwinnertech.com>
6 * MMC driver for allwinner sunxi platform.
8 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/clock.h>
16 #include <asm/arch/cpu.h>
17 #include <asm/arch/mmc.h>
19 struct sunxi_mmc_host {
25 struct sunxi_mmc *reg;
26 struct mmc_config cfg;
29 /* support 4 mmc hosts */
30 struct sunxi_mmc_host mmc_host[4];
32 static int mmc_resource_init(int sdc_no)
34 struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
35 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
37 debug("init mmc %d resource\n", sdc_no);
41 mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
42 mmchost->mclkreg = &ccm->sd0_clk_cfg;
45 mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
46 mmchost->mclkreg = &ccm->sd1_clk_cfg;
49 mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
50 mmchost->mclkreg = &ccm->sd2_clk_cfg;
53 mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
54 mmchost->mclkreg = &ccm->sd3_clk_cfg;
57 printf("Wrong mmc number %d\n", sdc_no);
60 mmchost->database = (unsigned int)mmchost->reg + 0x100;
61 mmchost->mmc_no = sdc_no;
66 static int mmc_clk_io_on(int sdc_no)
70 struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
71 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
73 debug("init mmc %d clock and io\n", sdc_no);
75 /* config ahb clock */
76 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
78 /* config mod clock */
79 pll_clk = clock_get_pll6();
80 /* should be close to 100 MHz but no more, so round up */
81 divider = ((pll_clk + 99999999) / 100000000) - 1;
82 writel(CCM_MMC_CTRL_ENABLE | CCM_MMC_CTRL_PLL6 | divider,
84 mmchost->mod_clk = pll_clk / (divider + 1);
89 static int mmc_update_clk(struct mmc *mmc)
91 struct sunxi_mmc_host *mmchost = mmc->priv;
93 unsigned timeout_msecs = 2000;
95 cmd = SUNXI_MMC_CMD_START |
96 SUNXI_MMC_CMD_UPCLK_ONLY |
97 SUNXI_MMC_CMD_WAIT_PRE_OVER;
98 writel(cmd, &mmchost->reg->cmd);
99 while (readl(&mmchost->reg->cmd) & SUNXI_MMC_CMD_START) {
100 if (!timeout_msecs--)
105 /* clock update sets various irq status bits, clear these */
106 writel(readl(&mmchost->reg->rint), &mmchost->reg->rint);
111 static int mmc_config_clock(struct mmc *mmc, unsigned div)
113 struct sunxi_mmc_host *mmchost = mmc->priv;
114 unsigned rval = readl(&mmchost->reg->clkcr);
117 rval &= ~SUNXI_MMC_CLK_ENABLE;
118 writel(rval, &mmchost->reg->clkcr);
119 if (mmc_update_clk(mmc))
122 /* Change Divider Factor */
123 rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
125 writel(rval, &mmchost->reg->clkcr);
126 if (mmc_update_clk(mmc))
128 /* Re-enable Clock */
129 rval |= SUNXI_MMC_CLK_ENABLE;
130 writel(rval, &mmchost->reg->clkcr);
132 if (mmc_update_clk(mmc))
138 static void mmc_set_ios(struct mmc *mmc)
140 struct sunxi_mmc_host *mmchost = mmc->priv;
141 unsigned int clkdiv = 0;
143 debug("set ios: bus_width: %x, clock: %d, mod_clk: %d\n",
144 mmc->bus_width, mmc->clock, mmchost->mod_clk);
146 /* Change clock first */
147 clkdiv = (mmchost->mod_clk + (mmc->clock >> 1)) / mmc->clock / 2;
149 if (mmc_config_clock(mmc, clkdiv)) {
150 mmchost->fatal_err = 1;
155 /* Change bus width */
156 if (mmc->bus_width == 8)
157 writel(0x2, &mmchost->reg->width);
158 else if (mmc->bus_width == 4)
159 writel(0x1, &mmchost->reg->width);
161 writel(0x0, &mmchost->reg->width);
164 static int mmc_core_init(struct mmc *mmc)
166 struct sunxi_mmc_host *mmchost = mmc->priv;
168 /* Reset controller */
169 writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
175 static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data)
177 struct sunxi_mmc_host *mmchost = mmc->priv;
178 const int reading = !!(data->flags & MMC_DATA_READ);
179 const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY :
180 SUNXI_MMC_STATUS_FIFO_FULL;
182 unsigned byte_cnt = data->blocksize * data->blocks;
183 unsigned timeout_msecs = 2000;
184 unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
186 /* Always read / write data through the CPU */
187 setbits_le32(&mmchost->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
189 for (i = 0; i < (byte_cnt >> 2); i++) {
190 while (readl(&mmchost->reg->status) & status_bit) {
191 if (!timeout_msecs--)
197 buff[i] = readl(mmchost->database);
199 writel(buff[i], mmchost->database);
205 static int mmc_rint_wait(struct mmc *mmc, unsigned int timeout_msecs,
206 unsigned int done_bit, const char *what)
208 struct sunxi_mmc_host *mmchost = mmc->priv;
212 status = readl(&mmchost->reg->rint);
213 if (!timeout_msecs-- ||
214 (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
215 debug("%s timeout %x\n", what,
216 status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
220 } while (!(status & done_bit));
225 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
226 struct mmc_data *data)
228 struct sunxi_mmc_host *mmchost = mmc->priv;
229 unsigned int cmdval = SUNXI_MMC_CMD_START;
230 unsigned int timeout_msecs;
232 unsigned int status = 0;
233 unsigned int bytecnt = 0;
235 if (mmchost->fatal_err)
237 if (cmd->resp_type & MMC_RSP_BUSY)
238 debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);
239 if (cmd->cmdidx == 12)
243 cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ;
244 if (cmd->resp_type & MMC_RSP_PRESENT)
245 cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE;
246 if (cmd->resp_type & MMC_RSP_136)
247 cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE;
248 if (cmd->resp_type & MMC_RSP_CRC)
249 cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;
252 if ((u32) data->dest & 0x3) {
257 cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER;
258 if (data->flags & MMC_DATA_WRITE)
259 cmdval |= SUNXI_MMC_CMD_WRITE;
260 if (data->blocks > 1)
261 cmdval |= SUNXI_MMC_CMD_AUTO_STOP;
262 writel(data->blocksize, &mmchost->reg->blksz);
263 writel(data->blocks * data->blocksize, &mmchost->reg->bytecnt);
266 debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", mmchost->mmc_no,
267 cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);
268 writel(cmd->cmdarg, &mmchost->reg->arg);
271 writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
274 * transfer data and check status
275 * STATREG[2] : FIFO empty
276 * STATREG[3] : FIFO full
281 bytecnt = data->blocksize * data->blocks;
282 debug("trans data %d bytes\n", bytecnt);
283 writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
284 ret = mmc_trans_data_by_cpu(mmc, data);
286 error = readl(&mmchost->reg->rint) & \
287 SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
293 error = mmc_rint_wait(mmc, 0xfffff, SUNXI_MMC_RINT_COMMAND_DONE, "cmd");
299 debug("cacl timeout %x msec\n", timeout_msecs);
300 error = mmc_rint_wait(mmc, timeout_msecs,
302 SUNXI_MMC_RINT_AUTO_COMMAND_DONE :
303 SUNXI_MMC_RINT_DATA_OVER,
309 if (cmd->resp_type & MMC_RSP_BUSY) {
310 timeout_msecs = 2000;
312 status = readl(&mmchost->reg->status);
313 if (!timeout_msecs--) {
314 debug("busy timeout\n");
319 } while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
322 if (cmd->resp_type & MMC_RSP_136) {
323 cmd->response[0] = readl(&mmchost->reg->resp3);
324 cmd->response[1] = readl(&mmchost->reg->resp2);
325 cmd->response[2] = readl(&mmchost->reg->resp1);
326 cmd->response[3] = readl(&mmchost->reg->resp0);
327 debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
328 cmd->response[3], cmd->response[2],
329 cmd->response[1], cmd->response[0]);
331 cmd->response[0] = readl(&mmchost->reg->resp0);
332 debug("mmc resp 0x%08x\n", cmd->response[0]);
336 writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
339 writel(0xffffffff, &mmchost->reg->rint);
340 writel(readl(&mmchost->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET,
341 &mmchost->reg->gctrl);
346 static const struct mmc_ops sunxi_mmc_ops = {
347 .send_cmd = mmc_send_cmd,
348 .set_ios = mmc_set_ios,
349 .init = mmc_core_init,
352 int sunxi_mmc_init(int sdc_no)
354 struct mmc_config *cfg = &mmc_host[sdc_no].cfg;
356 memset(&mmc_host[sdc_no], 0, sizeof(struct sunxi_mmc_host));
358 cfg->name = "SUNXI SD/MMC";
359 cfg->ops = &sunxi_mmc_ops;
361 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
362 cfg->host_caps = MMC_MODE_4BIT;
363 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
364 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
367 cfg->f_max = 52000000;
369 mmc_resource_init(sdc_no);
370 mmc_clk_io_on(sdc_no);
372 if (mmc_create(cfg, &mmc_host[sdc_no]) == NULL)