2 * (C) Copyright 2007-2011
3 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
4 * Aaron <leafy.myeh@allwinnertech.com>
6 * MMC driver for allwinner sunxi platform.
8 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/arch/clock.h>
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/mmc.h>
21 #include <asm-generic/gpio.h>
23 struct sunxi_mmc_plat {
24 struct mmc_config cfg;
28 struct sunxi_mmc_priv {
32 struct gpio_desc cd_gpio; /* Change Detect GPIO */
33 int cd_inverted; /* Inverted Card Detect */
34 struct sunxi_mmc *reg;
35 struct mmc_config cfg;
38 #if !CONFIG_IS_ENABLED(DM_MMC)
39 /* support 4 mmc hosts */
40 struct sunxi_mmc_priv mmc_host[4];
42 static int sunxi_mmc_getcd_gpio(int sdc_no)
45 case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN);
46 case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN);
47 case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN);
48 case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN);
53 static int mmc_resource_init(int sdc_no)
55 struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
56 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
59 debug("init mmc %d resource\n", sdc_no);
63 priv->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
64 priv->mclkreg = &ccm->sd0_clk_cfg;
67 priv->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
68 priv->mclkreg = &ccm->sd1_clk_cfg;
71 priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
72 priv->mclkreg = &ccm->sd2_clk_cfg;
75 priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
76 priv->mclkreg = &ccm->sd3_clk_cfg;
79 printf("Wrong mmc number %d\n", sdc_no);
82 priv->mmc_no = sdc_no;
84 cd_pin = sunxi_mmc_getcd_gpio(sdc_no);
86 ret = gpio_request(cd_pin, "mmc_cd");
88 sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
89 ret = gpio_direction_input(cd_pin);
97 static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
99 unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
100 bool new_mode = false;
103 if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2))
107 * The MMC clock has an extra /2 post-divider when operating in the new
113 if (hz <= 24000000) {
114 pll = CCM_MMC_CTRL_OSCM24;
117 #ifdef CONFIG_MACH_SUN9I
118 pll = CCM_MMC_CTRL_PLL_PERIPH0;
119 pll_hz = clock_get_pll4_periph0();
121 pll = CCM_MMC_CTRL_PLL6;
122 pll_hz = clock_get_pll6();
137 printf("mmc %u error cannot set clock to %u\n", priv->mmc_no,
142 /* determine delays */
146 } else if (hz <= 25000000) {
149 #ifdef CONFIG_MACH_SUN9I
150 } else if (hz <= 50000000) {
158 } else if (hz <= 50000000) {
169 #ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE
170 val = CCM_MMC_CTRL_MODE_SEL_NEW;
171 setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
174 val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
175 CCM_MMC_CTRL_SCLK_DLY(sclk_dly);
178 writel(CCM_MMC_CTRL_ENABLE| pll | CCM_MMC_CTRL_N(n) |
179 CCM_MMC_CTRL_M(div) | val, priv->mclkreg);
181 debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n",
182 priv->mmc_no, hz, pll_hz, 1u << n, div, pll_hz / (1u << n) / div);
187 static int mmc_update_clk(struct sunxi_mmc_priv *priv)
190 unsigned timeout_msecs = 2000;
192 cmd = SUNXI_MMC_CMD_START |
193 SUNXI_MMC_CMD_UPCLK_ONLY |
194 SUNXI_MMC_CMD_WAIT_PRE_OVER;
195 writel(cmd, &priv->reg->cmd);
196 while (readl(&priv->reg->cmd) & SUNXI_MMC_CMD_START) {
197 if (!timeout_msecs--)
202 /* clock update sets various irq status bits, clear these */
203 writel(readl(&priv->reg->rint), &priv->reg->rint);
208 static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc)
210 unsigned rval = readl(&priv->reg->clkcr);
213 rval &= ~SUNXI_MMC_CLK_ENABLE;
214 writel(rval, &priv->reg->clkcr);
215 if (mmc_update_clk(priv))
218 /* Set mod_clk to new rate */
219 if (mmc_set_mod_clk(priv, mmc->clock))
222 /* Clear internal divider */
223 rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
224 writel(rval, &priv->reg->clkcr);
226 /* Re-enable Clock */
227 rval |= SUNXI_MMC_CLK_ENABLE;
228 writel(rval, &priv->reg->clkcr);
229 if (mmc_update_clk(priv))
235 static int sunxi_mmc_set_ios_common(struct sunxi_mmc_priv *priv,
238 debug("set ios: bus_width: %x, clock: %d\n",
239 mmc->bus_width, mmc->clock);
241 /* Change clock first */
242 if (mmc->clock && mmc_config_clock(priv, mmc) != 0) {
247 /* Change bus width */
248 if (mmc->bus_width == 8)
249 writel(0x2, &priv->reg->width);
250 else if (mmc->bus_width == 4)
251 writel(0x1, &priv->reg->width);
253 writel(0x0, &priv->reg->width);
258 #if !CONFIG_IS_ENABLED(DM_MMC)
259 static int sunxi_mmc_core_init(struct mmc *mmc)
261 struct sunxi_mmc_priv *priv = mmc->priv;
263 /* Reset controller */
264 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
271 static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc,
272 struct mmc_data *data)
274 const int reading = !!(data->flags & MMC_DATA_READ);
275 const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY :
276 SUNXI_MMC_STATUS_FIFO_FULL;
278 unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
279 unsigned byte_cnt = data->blocksize * data->blocks;
280 unsigned timeout_usecs = (byte_cnt >> 8) * 1000;
281 if (timeout_usecs < 2000000)
282 timeout_usecs = 2000000;
284 /* Always read / write data through the CPU */
285 setbits_le32(&priv->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
287 for (i = 0; i < (byte_cnt >> 2); i++) {
288 while (readl(&priv->reg->status) & status_bit) {
289 if (!timeout_usecs--)
295 buff[i] = readl(&priv->reg->fifo);
297 writel(buff[i], &priv->reg->fifo);
303 static int mmc_rint_wait(struct sunxi_mmc_priv *priv, struct mmc *mmc,
304 uint timeout_msecs, uint done_bit, const char *what)
309 status = readl(&priv->reg->rint);
310 if (!timeout_msecs-- ||
311 (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
312 debug("%s timeout %x\n", what,
313 status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
317 } while (!(status & done_bit));
322 static int sunxi_mmc_send_cmd_common(struct sunxi_mmc_priv *priv,
323 struct mmc *mmc, struct mmc_cmd *cmd,
324 struct mmc_data *data)
326 unsigned int cmdval = SUNXI_MMC_CMD_START;
327 unsigned int timeout_msecs;
329 unsigned int status = 0;
330 unsigned int bytecnt = 0;
334 if (cmd->resp_type & MMC_RSP_BUSY)
335 debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);
336 if (cmd->cmdidx == 12)
340 cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ;
341 if (cmd->resp_type & MMC_RSP_PRESENT)
342 cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE;
343 if (cmd->resp_type & MMC_RSP_136)
344 cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE;
345 if (cmd->resp_type & MMC_RSP_CRC)
346 cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;
349 if ((u32)(long)data->dest & 0x3) {
354 cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER;
355 if (data->flags & MMC_DATA_WRITE)
356 cmdval |= SUNXI_MMC_CMD_WRITE;
357 if (data->blocks > 1)
358 cmdval |= SUNXI_MMC_CMD_AUTO_STOP;
359 writel(data->blocksize, &priv->reg->blksz);
360 writel(data->blocks * data->blocksize, &priv->reg->bytecnt);
363 debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", priv->mmc_no,
364 cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);
365 writel(cmd->cmdarg, &priv->reg->arg);
368 writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
371 * transfer data and check status
372 * STATREG[2] : FIFO empty
373 * STATREG[3] : FIFO full
378 bytecnt = data->blocksize * data->blocks;
379 debug("trans data %d bytes\n", bytecnt);
380 writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
381 ret = mmc_trans_data_by_cpu(priv, mmc, data);
383 error = readl(&priv->reg->rint) &
384 SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
390 error = mmc_rint_wait(priv, mmc, 1000, SUNXI_MMC_RINT_COMMAND_DONE,
397 debug("cacl timeout %x msec\n", timeout_msecs);
398 error = mmc_rint_wait(priv, mmc, timeout_msecs,
400 SUNXI_MMC_RINT_AUTO_COMMAND_DONE :
401 SUNXI_MMC_RINT_DATA_OVER,
407 if (cmd->resp_type & MMC_RSP_BUSY) {
408 timeout_msecs = 2000;
410 status = readl(&priv->reg->status);
411 if (!timeout_msecs--) {
412 debug("busy timeout\n");
417 } while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
420 if (cmd->resp_type & MMC_RSP_136) {
421 cmd->response[0] = readl(&priv->reg->resp3);
422 cmd->response[1] = readl(&priv->reg->resp2);
423 cmd->response[2] = readl(&priv->reg->resp1);
424 cmd->response[3] = readl(&priv->reg->resp0);
425 debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
426 cmd->response[3], cmd->response[2],
427 cmd->response[1], cmd->response[0]);
429 cmd->response[0] = readl(&priv->reg->resp0);
430 debug("mmc resp 0x%08x\n", cmd->response[0]);
434 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
435 mmc_update_clk(priv);
437 writel(0xffffffff, &priv->reg->rint);
438 writel(readl(&priv->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET,
444 #if !CONFIG_IS_ENABLED(DM_MMC)
445 static int sunxi_mmc_set_ios_legacy(struct mmc *mmc)
447 struct sunxi_mmc_priv *priv = mmc->priv;
449 return sunxi_mmc_set_ios_common(priv, mmc);
452 static int sunxi_mmc_send_cmd_legacy(struct mmc *mmc, struct mmc_cmd *cmd,
453 struct mmc_data *data)
455 struct sunxi_mmc_priv *priv = mmc->priv;
457 return sunxi_mmc_send_cmd_common(priv, mmc, cmd, data);
460 static int sunxi_mmc_getcd_legacy(struct mmc *mmc)
462 struct sunxi_mmc_priv *priv = mmc->priv;
465 cd_pin = sunxi_mmc_getcd_gpio(priv->mmc_no);
469 return !gpio_get_value(cd_pin);
472 static const struct mmc_ops sunxi_mmc_ops = {
473 .send_cmd = sunxi_mmc_send_cmd_legacy,
474 .set_ios = sunxi_mmc_set_ios_legacy,
475 .init = sunxi_mmc_core_init,
476 .getcd = sunxi_mmc_getcd_legacy,
479 struct mmc *sunxi_mmc_init(int sdc_no)
481 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
482 struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
483 struct mmc_config *cfg = &priv->cfg;
486 memset(priv, '\0', sizeof(struct sunxi_mmc_priv));
488 cfg->name = "SUNXI SD/MMC";
489 cfg->ops = &sunxi_mmc_ops;
491 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
492 cfg->host_caps = MMC_MODE_4BIT;
493 #if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I)
495 cfg->host_caps = MMC_MODE_8BIT;
497 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
498 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
501 cfg->f_max = 52000000;
503 if (mmc_resource_init(sdc_no) != 0)
506 /* config ahb clock */
507 debug("init mmc %d clock and io\n", sdc_no);
508 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
510 #ifdef CONFIG_SUNXI_GEN_SUN6I
512 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
514 #if defined(CONFIG_MACH_SUN9I)
515 /* sun9i has a mmc-common module, also set the gate and reset there */
516 writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET,
517 SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
519 ret = mmc_set_mod_clk(priv, 24000000);
523 return mmc_create(cfg, priv);
527 static int sunxi_mmc_set_ios(struct udevice *dev)
529 struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
530 struct sunxi_mmc_priv *priv = dev_get_priv(dev);
532 return sunxi_mmc_set_ios_common(priv, &plat->mmc);
535 static int sunxi_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
536 struct mmc_data *data)
538 struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
539 struct sunxi_mmc_priv *priv = dev_get_priv(dev);
541 return sunxi_mmc_send_cmd_common(priv, &plat->mmc, cmd, data);
544 static int sunxi_mmc_getcd(struct udevice *dev)
546 struct sunxi_mmc_priv *priv = dev_get_priv(dev);
548 if (dm_gpio_is_valid(&priv->cd_gpio)) {
549 int cd_state = dm_gpio_get_value(&priv->cd_gpio);
551 return cd_state ^ priv->cd_inverted;
556 static const struct dm_mmc_ops sunxi_mmc_ops = {
557 .send_cmd = sunxi_mmc_send_cmd,
558 .set_ios = sunxi_mmc_set_ios,
559 .get_cd = sunxi_mmc_getcd,
562 static int sunxi_mmc_probe(struct udevice *dev)
564 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
565 struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
566 struct sunxi_mmc_priv *priv = dev_get_priv(dev);
567 struct mmc_config *cfg = &plat->cfg;
568 struct ofnode_phandle_args args;
572 cfg->name = dev->name;
573 bus_width = dev_read_u32_default(dev, "bus-width", 1);
575 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
578 cfg->host_caps |= MMC_MODE_8BIT;
580 cfg->host_caps |= MMC_MODE_4BIT;
581 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
582 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
585 cfg->f_max = 52000000;
587 priv->reg = (void *)dev_read_addr(dev);
589 /* We don't have a sunxi clock driver so find the clock address here */
590 ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
594 priv->mclkreg = (u32 *)ofnode_get_addr(args.node);
596 ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
600 gate_reg = (u32 *)ofnode_get_addr(args.node);
601 setbits_le32(gate_reg, 1 << args.args[0]);
602 priv->mmc_no = args.args[0] - 8;
604 ret = mmc_set_mod_clk(priv, 24000000);
608 /* This GPIO is optional */
609 if (!gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
611 int cd_pin = gpio_get_number(&priv->cd_gpio);
613 sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
616 /* Check if card detect is inverted */
617 priv->cd_inverted = dev_read_bool(dev, "cd-inverted");
619 upriv->mmc = &plat->mmc;
621 /* Reset controller */
622 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
628 static int sunxi_mmc_bind(struct udevice *dev)
630 struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
632 return mmc_bind(dev, &plat->mmc, &plat->cfg);
635 static const struct udevice_id sunxi_mmc_ids[] = {
636 { .compatible = "allwinner,sun5i-a13-mmc" },
640 U_BOOT_DRIVER(sunxi_mmc_drv) = {
643 .of_match = sunxi_mmc_ids,
644 .bind = sunxi_mmc_bind,
645 .probe = sunxi_mmc_probe,
646 .ops = &sunxi_mmc_ops,
647 .platdata_auto_alloc_size = sizeof(struct sunxi_mmc_plat),
648 .priv_auto_alloc_size = sizeof(struct sunxi_mmc_priv),