git.sur5r.net Git - u-boot/blob - drivers/mmc/tegra2_mmc.c

   1 /*
   2  * (C) Copyright 2009 SAMSUNG Electronics
   3  * Minkyu Kang <mk7.kang@samsung.com>
   4  * Jaehoon Chung <jh80.chung@samsung.com>
   5  * Portions Copyright 2011 NVIDIA Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 #include <common.h>
  23 #include <mmc.h>
  24 #include <asm/gpio.h>
  25 #include <asm/io.h>
  26 #include <asm/arch/clk_rst.h>
  27 #include <asm/arch/clock.h>
  28 #include "tegra2_mmc.h"
  29
  30 /* support 4 mmc hosts */
  31 struct mmc mmc_dev[4];
  32 struct mmc_host mmc_host[4];
  33
  34
  35 /**
  36  * Get the host address and peripheral ID for a device. Devices are numbered
  37  * from 0 to 3.
  38  *
  39  * @param host          Structure to fill in (base, reg, mmc_id)
  40  * @param dev_index     Device index (0-3)
  41  */
  42 static void tegra2_get_setup(struct mmc_host *host, int dev_index)
  43 {
  44         debug("tegra2_get_base_mmc: dev_index = %d\n", dev_index);
  45
  46         switch (dev_index) {
  47         case 1:
  48                 host->base = TEGRA2_SDMMC3_BASE;
  49                 host->mmc_id = PERIPH_ID_SDMMC3;
  50                 break;
  51         case 2:
  52                 host->base = TEGRA2_SDMMC2_BASE;
  53                 host->mmc_id = PERIPH_ID_SDMMC2;
  54                 break;
  55         case 3:
  56                 host->base = TEGRA2_SDMMC1_BASE;
  57                 host->mmc_id = PERIPH_ID_SDMMC1;
  58                 break;
  59         case 0:
  60         default:
  61                 host->base = TEGRA2_SDMMC4_BASE;
  62                 host->mmc_id = PERIPH_ID_SDMMC4;
  63                 break;
  64         }
  65
  66         host->reg = (struct tegra2_mmc *)host->base;
  67 }
  68
  69 static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data)
  70 {
  71         unsigned char ctrl;
  72
  73         debug("data->dest: %08X, data->blocks: %u, data->blocksize: %u\n",
  74         (u32)data->dest, data->blocks, data->blocksize);
  75
  76         writel((u32)data->dest, &host->reg->sysad);
  77         /*
  78          * DMASEL[4:3]
  79          * 00 = Selects SDMA
  80          * 01 = Reserved
  81          * 10 = Selects 32-bit Address ADMA2
  82          * 11 = Selects 64-bit Address ADMA2
  83          */
  84         ctrl = readb(&host->reg->hostctl);
  85         ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK;
  86         ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA;
  87         writeb(ctrl, &host->reg->hostctl);
  88
  89         /* We do not handle DMA boundaries, so set it to max (512 KiB) */
  90         writew((7 << 12) | (data->blocksize & 0xFFF), &host->reg->blksize);
  91         writew(data->blocks, &host->reg->blkcnt);
  92 }
  93
  94 static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data)
  95 {
  96         unsigned short mode;
  97         debug(" mmc_set_transfer_mode called\n");
  98         /*
  99          * TRNMOD
 100          * MUL1SIN0[5]  : Multi/Single Block Select
 101          * RD1WT0[4]    : Data Transfer Direction Select
 102          *      1 = read
 103          *      0 = write
 104          * ENACMD12[2]  : Auto CMD12 Enable
 105          * ENBLKCNT[1]  : Block Count Enable
 106          * ENDMA[0]     : DMA Enable
 107          */
 108         mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE |
 109                 TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE);
 110
 111         if (data->blocks > 1)
 112                 mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT;
 113
 114         if (data->flags & MMC_DATA_READ)
 115                 mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ;
 116
 117         if (data->flags & MMC_DATA_WRITE) {
 118                 if ((uintptr_t)data->src & (ARCH_DMA_MINALIGN - 1))
 119                         printf("Warning: unaligned write to %p may fail\n",
 120                                data->src);
 121                 flush_dcache_range((ulong)data->src, (ulong)data->src +
 122                         data->blocks * data->blocksize);
 123         }
 124
 125         writew(mode, &host->reg->trnmod);
 126 }
 127
 128 static int mmc_wait_inhibit(struct mmc_host *host,
 129                             struct mmc_cmd *cmd,
 130                             struct mmc_data *data,
 131                             unsigned int timeout)
 132 {
 133         /*
 134          * PRNSTS
 135          * CMDINHDAT[1] : Command Inhibit (DAT)
 136          * CMDINHCMD[0] : Command Inhibit (CMD)
 137          */
 138         unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD;
 139
 140         /*
 141          * We shouldn't wait for data inhibit for stop commands, even
 142          * though they might use busy signaling
 143          */
 144         if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY))
 145                 mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT;
 146
 147         while (readl(&host->reg->prnsts) & mask) {
 148                 if (timeout == 0) {
 149                         printf("%s: timeout error\n", __func__);
 150                         return -1;
 151                 }
 152                 timeout--;
 153                 udelay(1000);
 154         }
 155
 156         return 0;
 157 }
 158
 159 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 160                         struct mmc_data *data)
 161 {
 162         struct mmc_host *host = (struct mmc_host *)mmc->priv;
 163         int flags, i;
 164         int result;
 165         unsigned int mask;
 166         unsigned int retry = 0x100000;
 167         debug(" mmc_send_cmd called\n");
 168
 169         result = mmc_wait_inhibit(host, cmd, data, 10 /* ms */);
 170
 171         if (result < 0)
 172                 return result;
 173
 174         if (data)
 175                 mmc_prepare_data(host, data);
 176
 177         debug("cmd->arg: %08x\n", cmd->cmdarg);
 178         writel(cmd->cmdarg, &host->reg->argument);
 179
 180         if (data)
 181                 mmc_set_transfer_mode(host, data);
 182
 183         if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
 184                 return -1;
 185
 186         /*
 187          * CMDREG
 188          * CMDIDX[13:8] : Command index
 189          * DATAPRNT[5]  : Data Present Select
 190          * ENCMDIDX[4]  : Command Index Check Enable
 191          * ENCMDCRC[3]  : Command CRC Check Enable
 192          * RSPTYP[1:0]
 193          *      00 = No Response
 194          *      01 = Length 136
 195          *      10 = Length 48
 196          *      11 = Length 48 Check busy after response
 197          */
 198         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 199                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE;
 200         else if (cmd->resp_type & MMC_RSP_136)
 201                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136;
 202         else if (cmd->resp_type & MMC_RSP_BUSY)
 203                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY;
 204         else
 205                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48;
 206
 207         if (cmd->resp_type & MMC_RSP_CRC)
 208                 flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK;
 209         if (cmd->resp_type & MMC_RSP_OPCODE)
 210                 flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK;
 211         if (data)
 212                 flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER;
 213
 214         debug("cmd: %d\n", cmd->cmdidx);
 215
 216         writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg);
 217
 218         for (i = 0; i < retry; i++) {
 219                 mask = readl(&host->reg->norintsts);
 220                 /* Command Complete */
 221                 if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) {
 222                         if (!data)
 223                                 writel(mask, &host->reg->norintsts);
 224                         break;
 225                 }
 226         }
 227
 228         if (i == retry) {
 229                 printf("%s: waiting for status update\n", __func__);
 230                 return TIMEOUT;
 231         }
 232
 233         if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) {
 234                 /* Timeout Error */
 235                 debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
 236                 return TIMEOUT;
 237         } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
 238                 /* Error Interrupt */
 239                 debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
 240                 return -1;
 241         }
 242
 243         if (cmd->resp_type & MMC_RSP_PRESENT) {
 244                 if (cmd->resp_type & MMC_RSP_136) {
 245                         /* CRC is stripped so we need to do some shifting. */
 246                         for (i = 0; i < 4; i++) {
 247                                 unsigned int offset =
 248                                         (unsigned int)(&host->reg->rspreg3 - i);
 249                                 cmd->response[i] = readl(offset) << 8;
 250
 251                                 if (i != 3) {
 252                                         cmd->response[i] |=
 253                                                 readb(offset - 1);
 254                                 }
 255                                 debug("cmd->resp[%d]: %08x\n",
 256                                                 i, cmd->response[i]);
 257                         }
 258                 } else if (cmd->resp_type & MMC_RSP_BUSY) {
 259                         for (i = 0; i < retry; i++) {
 260                                 /* PRNTDATA[23:20] : DAT[3:0] Line Signal */
 261                                 if (readl(&host->reg->prnsts)
 262                                         & (1 << 20))    /* DAT[0] */
 263                                         break;
 264                         }
 265
 266                         if (i == retry) {
 267                                 printf("%s: card is still busy\n", __func__);
 268                                 return TIMEOUT;
 269                         }
 270
 271                         cmd->response[0] = readl(&host->reg->rspreg0);
 272                         debug("cmd->resp[0]: %08x\n", cmd->response[0]);
 273                 } else {
 274                         cmd->response[0] = readl(&host->reg->rspreg0);
 275                         debug("cmd->resp[0]: %08x\n", cmd->response[0]);
 276                 }
 277         }
 278
 279         if (data) {
 280                 unsigned long   start = get_timer(0);
 281
 282                 while (1) {
 283                         mask = readl(&host->reg->norintsts);
 284
 285                         if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
 286                                 /* Error Interrupt */
 287                                 writel(mask, &host->reg->norintsts);
 288                                 printf("%s: error during transfer: 0x%08x\n",
 289                                                 __func__, mask);
 290                                 return -1;
 291                         } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) {
 292                                 /*
 293                                  * DMA Interrupt, restart the transfer where
 294                                  * it was interrupted.
 295                                  */
 296                                 unsigned int address = readl(&host->reg->sysad);
 297
 298                                 debug("DMA end\n");
 299                                 writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT,
 300                                        &host->reg->norintsts);
 301                                 writel(address, &host->reg->sysad);
 302                         } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) {
 303                                 /* Transfer Complete */
 304                                 debug("r/w is done\n");
 305                                 break;
 306                         } else if (get_timer(start) > 2000UL) {
 307                                 writel(mask, &host->reg->norintsts);
 308                                 printf("%s: MMC Timeout\n"
 309                                        "    Interrupt status        0x%08x\n"
 310                                        "    Interrupt status enable 0x%08x\n"
 311                                        "    Interrupt signal enable 0x%08x\n"
 312                                        "    Present status          0x%08x\n",
 313                                        __func__, mask,
 314                                        readl(&host->reg->norintstsen),
 315                                        readl(&host->reg->norintsigen),
 316                                        readl(&host->reg->prnsts));
 317                                 return -1;
 318                         }
 319                 }
 320                 writel(mask, &host->reg->norintsts);
 321                 if (data->flags & MMC_DATA_READ) {
 322                         if ((uintptr_t)data->dest & (ARCH_DMA_MINALIGN - 1))
 323                                 printf("Warning: unaligned read from %p "
 324                                         "may fail\n", data->dest);
 325                         invalidate_dcache_range((ulong)data->dest,
 326                                 (ulong)data->dest +
 327                                         data->blocks * data->blocksize);
 328                 }
 329         }
 330
 331         udelay(1000);
 332         return 0;
 333 }
 334
 335 static void mmc_change_clock(struct mmc_host *host, uint clock)
 336 {
 337         int div;
 338         unsigned short clk;
 339         unsigned long timeout;
 340
 341         debug(" mmc_change_clock called\n");
 342
 343         /*
 344          * Change Tegra2 SDMMCx clock divisor here. Source is 216MHz,
 345          * PLLP_OUT0
 346          */
 347         if (clock == 0)
 348                 goto out;
 349         clock_adjust_periph_pll_div(host->mmc_id, CLOCK_ID_PERIPH, clock,
 350                                     &div);
 351         debug("div = %d\n", div);
 352
 353         writew(0, &host->reg->clkcon);
 354
 355         /*
 356          * CLKCON
 357          * SELFREQ[15:8]        : base clock divided by value
 358          * ENSDCLK[2]           : SD Clock Enable
 359          * STBLINTCLK[1]        : Internal Clock Stable
 360          * ENINTCLK[0]          : Internal Clock Enable
 361          */
 362         div >>= 1;
 363         clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) |
 364                TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE);
 365         writew(clk, &host->reg->clkcon);
 366
 367         /* Wait max 10 ms */
 368         timeout = 10;
 369         while (!(readw(&host->reg->clkcon) &
 370                  TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) {
 371                 if (timeout == 0) {
 372                         printf("%s: timeout error\n", __func__);
 373                         return;
 374                 }
 375                 timeout--;
 376                 udelay(1000);
 377         }
 378
 379         clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
 380         writew(clk, &host->reg->clkcon);
 381
 382         debug("mmc_change_clock: clkcon = %08X\n", clk);
 383
 384 out:
 385         host->clock = clock;
 386 }
 387
 388 static void mmc_set_ios(struct mmc *mmc)
 389 {
 390         struct mmc_host *host = mmc->priv;
 391         unsigned char ctrl;
 392         debug(" mmc_set_ios called\n");
 393
 394         debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
 395
 396         /* Change clock first */
 397         mmc_change_clock(host, mmc->clock);
 398
 399         ctrl = readb(&host->reg->hostctl);
 400
 401         /*
 402          * WIDE8[5]
 403          * 0 = Depend on WIDE4
 404          * 1 = 8-bit mode
 405          * WIDE4[1]
 406          * 1 = 4-bit mode
 407          * 0 = 1-bit mode
 408          */
 409         if (mmc->bus_width == 8)
 410                 ctrl |= (1 << 5);
 411         else if (mmc->bus_width == 4)
 412                 ctrl |= (1 << 1);
 413         else
 414                 ctrl &= ~(1 << 1);
 415
 416         writeb(ctrl, &host->reg->hostctl);
 417         debug("mmc_set_ios: hostctl = %08X\n", ctrl);
 418 }
 419
 420 static void mmc_reset(struct mmc_host *host)
 421 {
 422         unsigned int timeout;
 423         debug(" mmc_reset called\n");
 424
 425         /*
 426          * RSTALL[0] : Software reset for all
 427          * 1 = reset
 428          * 0 = work
 429          */
 430         writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &host->reg->swrst);
 431
 432         host->clock = 0;
 433
 434         /* Wait max 100 ms */
 435         timeout = 100;
 436
 437         /* hw clears the bit when it's done */
 438         while (readb(&host->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) {
 439                 if (timeout == 0) {
 440                         printf("%s: timeout error\n", __func__);
 441                         return;
 442                 }
 443                 timeout--;
 444                 udelay(1000);
 445         }
 446 }
 447
 448 static int mmc_core_init(struct mmc *mmc)
 449 {
 450         struct mmc_host *host = (struct mmc_host *)mmc->priv;
 451         unsigned int mask;
 452         debug(" mmc_core_init called\n");
 453
 454         mmc_reset(host);
 455
 456         host->version = readw(&host->reg->hcver);
 457         debug("host version = %x\n", host->version);
 458
 459         /* mask all */
 460         writel(0xffffffff, &host->reg->norintstsen);
 461         writel(0xffffffff, &host->reg->norintsigen);
 462
 463         writeb(0xe, &host->reg->timeoutcon);    /* TMCLK * 2^27 */
 464         /*
 465          * NORMAL Interrupt Status Enable Register init
 466          * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
 467          * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
 468          * [3] ENSTADMAINT   : DMA boundary interrupt
 469          * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
 470          * [0] ENSTACMDCMPLT : Command Complete Status Enable
 471         */
 472         mask = readl(&host->reg->norintstsen);
 473         mask &= ~(0xffff);
 474         mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE |
 475                  TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE |
 476                  TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT |
 477                  TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY |
 478                  TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY);
 479         writel(mask, &host->reg->norintstsen);
 480
 481         /*
 482          * NORMAL Interrupt Signal Enable Register init
 483          * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
 484          */
 485         mask = readl(&host->reg->norintsigen);
 486         mask &= ~(0xffff);
 487         mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE;
 488         writel(mask, &host->reg->norintsigen);
 489
 490         return 0;
 491 }
 492
 493 int tegra2_mmc_getcd(struct mmc *mmc)
 494 {
 495         struct mmc_host *host = (struct mmc_host *)mmc->priv;
 496
 497         debug("tegra2_mmc_getcd called\n");
 498
 499         if (host->cd_gpio >= 0)
 500                 return !gpio_get_value(host->cd_gpio);
 501
 502         return 1;
 503 }
 504
 505 int tegra2_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
 506 {
 507         struct mmc_host *host;
 508         char gpusage[12]; /* "SD/MMCn PWR" or "SD/MMCn CD" */
 509         struct mmc *mmc;
 510
 511         debug(" tegra2_mmc_init: index %d, bus width %d "
 512                 "pwr_gpio %d cd_gpio %d\n",
 513                 dev_index, bus_width, pwr_gpio, cd_gpio);
 514
 515         host = &mmc_host[dev_index];
 516
 517         host->clock = 0;
 518         host->pwr_gpio = pwr_gpio;
 519         host->cd_gpio = cd_gpio;
 520         tegra2_get_setup(host, dev_index);
 521
 522         clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000);
 523
 524         if (host->pwr_gpio >= 0) {
 525                 sprintf(gpusage, "SD/MMC%d PWR", dev_index);
 526                 gpio_request(host->pwr_gpio, gpusage);
 527                 gpio_direction_output(host->pwr_gpio, 1);
 528         }
 529
 530         if (host->cd_gpio >= 0) {
 531                 sprintf(gpusage, "SD/MMC%d CD", dev_index);
 532                 gpio_request(host->cd_gpio, gpusage);
 533                 gpio_direction_input(host->cd_gpio);
 534         }
 535
 536         mmc = &mmc_dev[dev_index];
 537
 538         sprintf(mmc->name, "Tegra2 SD/MMC");
 539         mmc->priv = host;
 540         mmc->send_cmd = mmc_send_cmd;
 541         mmc->set_ios = mmc_set_ios;
 542         mmc->init = mmc_core_init;
 543         mmc->getcd = tegra2_mmc_getcd;
 544
 545         mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 546         if (bus_width == 8)
 547                 mmc->host_caps = MMC_MODE_8BIT;
 548         else
 549                 mmc->host_caps = MMC_MODE_4BIT;
 550         mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
 551
 552         /*
 553          * min freq is for card identification, and is the highest
 554          *  low-speed SDIO card frequency (actually 400KHz)
 555          * max freq is highest HS eMMC clock as per the SD/MMC spec
 556          *  (actually 52MHz)
 557          * Both of these are the closest equivalents w/216MHz source
 558          *  clock and Tegra2 SDMMC divisors.
 559          */
 560         mmc->f_min = 375000;
 561         mmc->f_max = 48000000;
 562
 563         mmc_register(mmc);
 564
 565         return 0;
 566 }