2 * (C) Copyright 2009 SAMSUNG Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
4 * Jaehoon Chung <jh80.chung@samsung.com>
5 * Portions Copyright 2011-2016 NVIDIA Corporation
7 * SPDX-License-Identifier: GPL-2.0+
10 #include <bouncebuf.h>
12 #include <dm/device.h>
16 #ifndef CONFIG_TEGRA186
17 #include <asm/arch/clock.h>
18 #include <asm/arch-tegra/clk_rst.h>
20 #include <asm/arch-tegra/tegra_mmc.h>
24 * FIXME: TODO: This driver contains a number of ifdef CONFIG_TEGRA186 that
25 * should not be present. These are needed because newer Tegra SoCs support
26 * only the standard clock/reset APIs, whereas older Tegra SoCs support only
27 * a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be
28 * fixed to implement the standard APIs, and all drivers converted to solely
29 * use the new standard APIs, with no ifdefs.
32 DECLARE_GLOBAL_DATA_PTR;
34 struct tegra_mmc_priv {
35 struct tegra_mmc *reg;
36 #ifdef CONFIG_TEGRA186
37 struct reset_ctl reset_ctl;
40 enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */
42 struct gpio_desc cd_gpio; /* Change Detect GPIO */
43 struct gpio_desc pwr_gpio; /* Power GPIO */
44 struct gpio_desc wp_gpio; /* Write Protect GPIO */
45 unsigned int version; /* SDHCI spec. version */
46 unsigned int clock; /* Current clock (MHz) */
47 struct mmc_config cfg; /* mmc configuration */
51 static void tegra_mmc_set_power(struct tegra_mmc_priv *priv,
55 debug("%s: power = %x\n", __func__, power);
57 if (power != (unsigned short)-1) {
60 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8;
64 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0;
68 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3;
72 debug("%s: pwr = %X\n", __func__, pwr);
74 /* Set the bus voltage first (if any) */
75 writeb(pwr, &priv->reg->pwrcon);
79 /* Now enable bus power */
80 pwr |= TEGRA_MMC_PWRCTL_SD_BUS_POWER;
81 writeb(pwr, &priv->reg->pwrcon);
84 static void tegra_mmc_prepare_data(struct tegra_mmc_priv *priv,
85 struct mmc_data *data,
86 struct bounce_buffer *bbstate)
91 debug("buf: %p (%p), data->blocks: %u, data->blocksize: %u\n",
92 bbstate->bounce_buffer, bbstate->user_buffer, data->blocks,
95 writel((u32)(unsigned long)bbstate->bounce_buffer, &priv->reg->sysad);
100 * 10 = Selects 32-bit Address ADMA2
101 * 11 = Selects 64-bit Address ADMA2
103 ctrl = readb(&priv->reg->hostctl);
104 ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK;
105 ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA;
106 writeb(ctrl, &priv->reg->hostctl);
108 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
109 writew((7 << 12) | (data->blocksize & 0xFFF), &priv->reg->blksize);
110 writew(data->blocks, &priv->reg->blkcnt);
113 static void tegra_mmc_set_transfer_mode(struct tegra_mmc_priv *priv,
114 struct mmc_data *data)
117 debug(" mmc_set_transfer_mode called\n");
120 * MUL1SIN0[5] : Multi/Single Block Select
121 * RD1WT0[4] : Data Transfer Direction Select
124 * ENACMD12[2] : Auto CMD12 Enable
125 * ENBLKCNT[1] : Block Count Enable
126 * ENDMA[0] : DMA Enable
128 mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE |
129 TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE);
131 if (data->blocks > 1)
132 mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT;
134 if (data->flags & MMC_DATA_READ)
135 mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ;
137 writew(mode, &priv->reg->trnmod);
140 static int tegra_mmc_wait_inhibit(struct tegra_mmc_priv *priv,
142 struct mmc_data *data,
143 unsigned int timeout)
147 * CMDINHDAT[1] : Command Inhibit (DAT)
148 * CMDINHCMD[0] : Command Inhibit (CMD)
150 unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD;
153 * We shouldn't wait for data inhibit for stop commands, even
154 * though they might use busy signaling
156 if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY))
157 mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT;
159 while (readl(&priv->reg->prnsts) & mask) {
161 printf("%s: timeout error\n", __func__);
171 static int tegra_mmc_send_cmd_bounced(struct mmc *mmc, struct mmc_cmd *cmd,
172 struct mmc_data *data,
173 struct bounce_buffer *bbstate)
175 struct tegra_mmc_priv *priv = mmc->priv;
178 unsigned int mask = 0;
179 unsigned int retry = 0x100000;
180 debug(" mmc_send_cmd called\n");
182 result = tegra_mmc_wait_inhibit(priv, cmd, data, 10 /* ms */);
188 tegra_mmc_prepare_data(priv, data, bbstate);
190 debug("cmd->arg: %08x\n", cmd->cmdarg);
191 writel(cmd->cmdarg, &priv->reg->argument);
194 tegra_mmc_set_transfer_mode(priv, data);
196 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
201 * CMDIDX[13:8] : Command index
202 * DATAPRNT[5] : Data Present Select
203 * ENCMDIDX[4] : Command Index Check Enable
204 * ENCMDCRC[3] : Command CRC Check Enable
209 * 11 = Length 48 Check busy after response
211 if (!(cmd->resp_type & MMC_RSP_PRESENT))
212 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE;
213 else if (cmd->resp_type & MMC_RSP_136)
214 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136;
215 else if (cmd->resp_type & MMC_RSP_BUSY)
216 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY;
218 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48;
220 if (cmd->resp_type & MMC_RSP_CRC)
221 flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK;
222 if (cmd->resp_type & MMC_RSP_OPCODE)
223 flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK;
225 flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER;
227 debug("cmd: %d\n", cmd->cmdidx);
229 writew((cmd->cmdidx << 8) | flags, &priv->reg->cmdreg);
231 for (i = 0; i < retry; i++) {
232 mask = readl(&priv->reg->norintsts);
233 /* Command Complete */
234 if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) {
236 writel(mask, &priv->reg->norintsts);
242 printf("%s: waiting for status update\n", __func__);
243 writel(mask, &priv->reg->norintsts);
247 if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) {
249 debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
250 writel(mask, &priv->reg->norintsts);
252 } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
253 /* Error Interrupt */
254 debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
255 writel(mask, &priv->reg->norintsts);
259 if (cmd->resp_type & MMC_RSP_PRESENT) {
260 if (cmd->resp_type & MMC_RSP_136) {
261 /* CRC is stripped so we need to do some shifting. */
262 for (i = 0; i < 4; i++) {
263 unsigned long offset = (unsigned long)
264 (&priv->reg->rspreg3 - i);
265 cmd->response[i] = readl(offset) << 8;
271 debug("cmd->resp[%d]: %08x\n",
272 i, cmd->response[i]);
274 } else if (cmd->resp_type & MMC_RSP_BUSY) {
275 for (i = 0; i < retry; i++) {
276 /* PRNTDATA[23:20] : DAT[3:0] Line Signal */
277 if (readl(&priv->reg->prnsts)
278 & (1 << 20)) /* DAT[0] */
283 printf("%s: card is still busy\n", __func__);
284 writel(mask, &priv->reg->norintsts);
288 cmd->response[0] = readl(&priv->reg->rspreg0);
289 debug("cmd->resp[0]: %08x\n", cmd->response[0]);
291 cmd->response[0] = readl(&priv->reg->rspreg0);
292 debug("cmd->resp[0]: %08x\n", cmd->response[0]);
297 unsigned long start = get_timer(0);
300 mask = readl(&priv->reg->norintsts);
302 if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
303 /* Error Interrupt */
304 writel(mask, &priv->reg->norintsts);
305 printf("%s: error during transfer: 0x%08x\n",
308 } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) {
310 * DMA Interrupt, restart the transfer where
311 * it was interrupted.
313 unsigned int address = readl(&priv->reg->sysad);
316 writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT,
317 &priv->reg->norintsts);
318 writel(address, &priv->reg->sysad);
319 } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) {
320 /* Transfer Complete */
321 debug("r/w is done\n");
323 } else if (get_timer(start) > 8000UL) {
324 writel(mask, &priv->reg->norintsts);
325 printf("%s: MMC Timeout\n"
326 " Interrupt status 0x%08x\n"
327 " Interrupt status enable 0x%08x\n"
328 " Interrupt signal enable 0x%08x\n"
329 " Present status 0x%08x\n",
331 readl(&priv->reg->norintstsen),
332 readl(&priv->reg->norintsigen),
333 readl(&priv->reg->prnsts));
337 writel(mask, &priv->reg->norintsts);
344 static int tegra_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
345 struct mmc_data *data)
348 unsigned int bbflags;
350 struct bounce_buffer bbstate;
354 if (data->flags & MMC_DATA_READ) {
356 bbflags = GEN_BB_WRITE;
358 buf = (void *)data->src;
359 bbflags = GEN_BB_READ;
361 len = data->blocks * data->blocksize;
363 bounce_buffer_start(&bbstate, buf, len, bbflags);
366 ret = tegra_mmc_send_cmd_bounced(mmc, cmd, data, &bbstate);
369 bounce_buffer_stop(&bbstate);
374 static void tegra_mmc_change_clock(struct tegra_mmc_priv *priv, uint clock)
378 unsigned long timeout;
380 debug(" mmc_change_clock called\n");
383 * Change Tegra SDMMCx clock divisor here. Source is PLLP_OUT0
387 #ifdef CONFIG_TEGRA186
389 ulong rate = clk_set_rate(&priv->clk, clock);
390 div = (rate + clock - 1) / clock;
393 clock_adjust_periph_pll_div(priv->mmc_id, CLOCK_ID_PERIPH, clock,
396 debug("div = %d\n", div);
398 writew(0, &priv->reg->clkcon);
402 * SELFREQ[15:8] : base clock divided by value
403 * ENSDCLK[2] : SD Clock Enable
404 * STBLINTCLK[1] : Internal Clock Stable
405 * ENINTCLK[0] : Internal Clock Enable
408 clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) |
409 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE);
410 writew(clk, &priv->reg->clkcon);
414 while (!(readw(&priv->reg->clkcon) &
415 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) {
417 printf("%s: timeout error\n", __func__);
424 clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
425 writew(clk, &priv->reg->clkcon);
427 debug("mmc_change_clock: clkcon = %08X\n", clk);
433 static void tegra_mmc_set_ios(struct mmc *mmc)
435 struct tegra_mmc_priv *priv = mmc->priv;
437 debug(" mmc_set_ios called\n");
439 debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
441 /* Change clock first */
442 tegra_mmc_change_clock(priv, mmc->clock);
444 ctrl = readb(&priv->reg->hostctl);
448 * 0 = Depend on WIDE4
454 if (mmc->bus_width == 8)
456 else if (mmc->bus_width == 4)
461 writeb(ctrl, &priv->reg->hostctl);
462 debug("mmc_set_ios: hostctl = %08X\n", ctrl);
465 static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv)
467 #if defined(CONFIG_TEGRA30)
470 debug("%s: sdmmc address = %08x\n", __func__, (unsigned int)priv->reg);
472 /* Set the pad drive strength for SDMMC1 or 3 only */
473 if (priv->reg != (void *)0x78000000 &&
474 priv->reg != (void *)0x78000400) {
475 debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
480 val = readl(&priv->reg->sdmemcmppadctl);
482 val |= MEMCOMP_PADCTRL_VREF;
483 writel(val, &priv->reg->sdmemcmppadctl);
485 val = readl(&priv->reg->autocalcfg);
487 val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
488 writel(val, &priv->reg->autocalcfg);
492 static void tegra_mmc_reset(struct tegra_mmc_priv *priv, struct mmc *mmc)
494 unsigned int timeout;
495 debug(" mmc_reset called\n");
498 * RSTALL[0] : Software reset for all
502 writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &priv->reg->swrst);
506 /* Wait max 100 ms */
509 /* hw clears the bit when it's done */
510 while (readb(&priv->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) {
512 printf("%s: timeout error\n", __func__);
519 /* Set SD bus voltage & enable bus power */
520 tegra_mmc_set_power(priv, fls(mmc->cfg->voltages) - 1);
521 debug("%s: power control = %02X, host control = %02X\n", __func__,
522 readb(&priv->reg->pwrcon), readb(&priv->reg->hostctl));
524 /* Make sure SDIO pads are set up */
525 tegra_mmc_pad_init(priv);
528 static int tegra_mmc_init(struct mmc *mmc)
530 struct tegra_mmc_priv *priv = mmc->priv;
532 debug(" tegra_mmc_init called\n");
534 tegra_mmc_reset(priv, mmc);
536 priv->version = readw(&priv->reg->hcver);
537 debug("host version = %x\n", priv->version);
540 writel(0xffffffff, &priv->reg->norintstsen);
541 writel(0xffffffff, &priv->reg->norintsigen);
543 writeb(0xe, &priv->reg->timeoutcon); /* TMCLK * 2^27 */
545 * NORMAL Interrupt Status Enable Register init
546 * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
547 * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
548 * [3] ENSTADMAINT : DMA boundary interrupt
549 * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
550 * [0] ENSTACMDCMPLT : Command Complete Status Enable
552 mask = readl(&priv->reg->norintstsen);
554 mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE |
555 TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE |
556 TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT |
557 TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY |
558 TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY);
559 writel(mask, &priv->reg->norintstsen);
562 * NORMAL Interrupt Signal Enable Register init
563 * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
565 mask = readl(&priv->reg->norintsigen);
567 mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE;
568 writel(mask, &priv->reg->norintsigen);
573 static int tegra_mmc_getcd(struct mmc *mmc)
575 struct tegra_mmc_priv *priv = mmc->priv;
577 debug("tegra_mmc_getcd called\n");
579 if (dm_gpio_is_valid(&priv->cd_gpio))
580 return dm_gpio_get_value(&priv->cd_gpio);
585 static const struct mmc_ops tegra_mmc_ops = {
586 .send_cmd = tegra_mmc_send_cmd,
587 .set_ios = tegra_mmc_set_ios,
588 .init = tegra_mmc_init,
589 .getcd = tegra_mmc_getcd,
592 static int tegra_mmc_probe(struct udevice *dev)
594 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
595 struct tegra_mmc_priv *priv = dev_get_priv(dev);
597 #ifdef CONFIG_TEGRA186
601 priv->cfg.name = "Tegra SD/MMC";
602 priv->cfg.ops = &tegra_mmc_ops;
604 bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "bus-width",
607 priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
608 priv->cfg.host_caps = 0;
610 priv->cfg.host_caps |= MMC_MODE_8BIT;
612 priv->cfg.host_caps |= MMC_MODE_4BIT;
613 priv->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
616 * min freq is for card identification, and is the highest
617 * low-speed SDIO card frequency (actually 400KHz)
618 * max freq is highest HS eMMC clock as per the SD/MMC spec
621 priv->cfg.f_min = 375000;
622 priv->cfg.f_max = 48000000;
624 priv->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
626 priv->reg = (void *)dev_get_addr(dev);
628 #ifdef CONFIG_TEGRA186
629 ret = reset_get_by_name(dev, "sdhci", &priv->reset_ctl);
631 debug("reset_get_by_name() failed: %d\n", ret);
634 ret = clk_get_by_index(dev, 0, &priv->clk);
636 debug("clk_get_by_index() failed: %d\n", ret);
640 ret = reset_assert(&priv->reset_ctl);
643 ret = clk_enable(&priv->clk);
646 ret = clk_set_rate(&priv->clk, 20000000);
647 if (IS_ERR_VALUE(ret))
649 ret = reset_deassert(&priv->reset_ctl);
653 priv->mmc_id = clock_decode_periph_id(gd->fdt_blob, dev->of_offset);
654 if (priv->mmc_id == PERIPH_ID_NONE) {
655 debug("%s: could not decode periph id\n", __func__);
656 return -FDT_ERR_NOTFOUND;
659 clock_start_periph_pll(priv->mmc_id, CLOCK_ID_PERIPH, 20000000);
662 /* These GPIOs are optional */
663 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
665 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
667 gpio_request_by_name(dev, "power-gpios", 0,
668 &priv->pwr_gpio, GPIOD_IS_OUT);
669 if (dm_gpio_is_valid(&priv->pwr_gpio))
670 dm_gpio_set_value(&priv->pwr_gpio, 1);
672 priv->mmc = mmc_create(&priv->cfg, priv);
673 if (priv->mmc == NULL)
676 priv->mmc->dev = dev;
677 upriv->mmc = priv->mmc;
682 static const struct udevice_id tegra_mmc_ids[] = {
683 { .compatible = "nvidia,tegra20-sdhci" },
684 { .compatible = "nvidia,tegra30-sdhci" },
685 { .compatible = "nvidia,tegra114-sdhci" },
686 { .compatible = "nvidia,tegra124-sdhci" },
687 { .compatible = "nvidia,tegra210-sdhci" },
688 { .compatible = "nvidia,tegra186-sdhci" },
692 U_BOOT_DRIVER(tegra_mmc_drv) = {
695 .of_match = tegra_mmc_ids,
696 .probe = tegra_mmc_probe,
697 .priv_auto_alloc_size = sizeof(struct tegra_mmc_priv),