1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2013 - 2015 Xilinx, Inc.
5 * Xilinx Zynq SD Host Controller Interface
12 #include "mmc_private.h"
13 #include <linux/libfdt.h>
16 #include <zynqmp_tap_delay.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 struct arasan_sdhci_plat {
21 struct mmc_config cfg;
26 struct arasan_sdhci_priv {
27 struct sdhci_host *host;
34 #if defined(CONFIG_ARCH_ZYNQMP)
35 static const u8 mode2timing[] = {
36 [UHS_SDR12] = UHS_SDR12_BUS_SPEED,
37 [UHS_SDR25] = UHS_SDR25_BUS_SPEED,
38 [UHS_SDR50] = UHS_SDR50_BUS_SPEED,
39 [UHS_SDR104] = UHS_SDR104_BUS_SPEED,
40 [UHS_DDR50] = UHS_DDR50_BUS_SPEED,
43 #define SDHCI_HOST_CTRL2 0x3E
44 #define SDHCI_CTRL2_MODE_MASK 0x7
45 #define SDHCI_18V_SIGNAL 0x8
46 #define SDHCI_CTRL_EXEC_TUNING 0x0040
47 #define SDHCI_CTRL_TUNED_CLK 0x80
48 #define SDHCI_TUNING_LOOP_COUNT 40
50 static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 deviceid)
53 unsigned long timeout;
55 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
56 clk &= ~(SDHCI_CLOCK_CARD_EN);
57 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
60 zynqmp_dll_reset(deviceid);
64 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
65 & SDHCI_CLOCK_INT_STABLE)) {
67 dev_err(mmc_dev(host->mmc),
68 ": Internal clock never stabilised.\n");
75 clk |= SDHCI_CLOCK_CARD_EN;
76 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
79 static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
84 struct sdhci_host *host;
85 struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
86 u8 tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
89 debug("%s\n", __func__);
92 deviceid = priv->deviceid;
94 ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2);
95 ctrl |= SDHCI_CTRL_EXEC_TUNING;
96 sdhci_writew(host, ctrl, SDHCI_HOST_CTRL2);
100 arasan_zynqmp_dll_reset(host, deviceid);
102 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
103 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
107 cmd.resp_type = MMC_RSP_R1;
112 data.flags = MMC_DATA_READ;
114 if (tuning_loop_counter-- == 0)
117 if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200 &&
119 data.blocksize = 128;
121 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
124 sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT);
125 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
127 mmc_send_cmd(mmc, &cmd, NULL);
128 ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2);
130 if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
133 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
135 if (tuning_loop_counter < 0) {
136 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
137 sdhci_writel(host, ctrl, SDHCI_HOST_CTRL2);
140 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
141 printf("%s:Tuning failed\n", __func__);
146 arasan_zynqmp_dll_reset(host, deviceid);
148 /* Enable only interrupts served by the SD controller */
149 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
151 /* Mask all sdhci interrupt sources */
152 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
157 static void arasan_sdhci_set_tapdelay(struct sdhci_host *host)
159 struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
160 struct mmc *mmc = (struct mmc *)host->mmc;
166 uhsmode = mode2timing[mmc->selected_mode];
168 if (uhsmode >= UHS_SDR25_BUS_SPEED)
169 arasan_zynqmp_set_tapdelay(priv->deviceid, uhsmode,
173 static void arasan_sdhci_set_control_reg(struct sdhci_host *host)
175 struct mmc *mmc = (struct mmc *)host->mmc;
178 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
179 reg = sdhci_readw(host, SDHCI_HOST_CTRL2);
180 reg |= SDHCI_18V_SIGNAL;
181 sdhci_writew(host, reg, SDHCI_HOST_CTRL2);
184 if (mmc->selected_mode > SD_HS &&
185 mmc->selected_mode <= UHS_DDR50) {
186 reg = sdhci_readw(host, SDHCI_HOST_CTRL2);
187 reg &= ~SDHCI_CTRL2_MODE_MASK;
188 switch (mmc->selected_mode) {
190 reg |= UHS_SDR12_BUS_SPEED;
193 reg |= UHS_SDR25_BUS_SPEED;
196 reg |= UHS_SDR50_BUS_SPEED;
199 reg |= UHS_SDR104_BUS_SPEED;
202 reg |= UHS_DDR50_BUS_SPEED;
207 sdhci_writew(host, reg, SDHCI_HOST_CTRL2);
212 #if defined(CONFIG_DM_MMC) && defined(CONFIG_ARCH_ZYNQMP)
213 const struct sdhci_ops arasan_ops = {
214 .platform_execute_tuning = &arasan_sdhci_execute_tuning,
215 .set_delay = &arasan_sdhci_set_tapdelay,
216 .set_control_reg = &arasan_sdhci_set_control_reg,
220 static int arasan_sdhci_probe(struct udevice *dev)
222 struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
223 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
224 struct arasan_sdhci_priv *priv = dev_get_priv(dev);
225 struct sdhci_host *host;
232 ret = clk_get_by_index(dev, 0, &clk);
234 dev_err(dev, "failed to get clock\n");
238 clock = clk_get_rate(&clk);
239 if (IS_ERR_VALUE(clock)) {
240 dev_err(dev, "failed to get rate\n");
244 debug("%s: CLK %ld\n", __func__, clock);
246 ret = clk_enable(&clk);
247 if (ret && ret != -ENOSYS) {
248 dev_err(dev, "failed to enable clock\n");
252 host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
253 SDHCI_QUIRK_BROKEN_R1B;
255 #ifdef CONFIG_ZYNQ_HISPD_BROKEN
256 host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE;
260 host->quirks |= SDHCI_QUIRK_NO_1_8_V;
262 host->max_clk = clock;
264 ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max,
265 CONFIG_ZYNQ_SDHCI_MIN_FREQ);
266 host->mmc = &plat->mmc;
269 host->mmc->priv = host;
270 host->mmc->dev = dev;
271 upriv->mmc = host->mmc;
273 return sdhci_probe(dev);
276 static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
278 struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
279 struct arasan_sdhci_priv *priv = dev_get_priv(dev);
281 priv->host = calloc(1, sizeof(struct sdhci_host));
285 priv->host->name = dev->name;
286 priv->host->ioaddr = (void *)devfdt_get_addr(dev);
288 priv->deviceid = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
289 "xlnx,device_id", -1);
290 priv->bank = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
291 "xlnx,mio_bank", -1);
292 if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev),
298 #if defined(CONFIG_DM_MMC) && defined(CONFIG_ARCH_ZYNQMP)
299 priv->host->ops = &arasan_ops;
302 plat->f_max = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
303 "max-frequency", CONFIG_ZYNQ_SDHCI_MAX_FREQ);
308 static int arasan_sdhci_bind(struct udevice *dev)
310 struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
312 return sdhci_bind(dev, &plat->mmc, &plat->cfg);
315 static const struct udevice_id arasan_sdhci_ids[] = {
316 { .compatible = "arasan,sdhci-8.9a" },
320 U_BOOT_DRIVER(arasan_sdhci_drv) = {
321 .name = "arasan_sdhci",
323 .of_match = arasan_sdhci_ids,
324 .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
326 .bind = arasan_sdhci_bind,
327 .probe = arasan_sdhci_probe,
328 .priv_auto_alloc_size = sizeof(struct arasan_sdhci_priv),
329 .platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),