3 * Michael Schwingen, <michael@schwingen.org>
5 * based in great part on jedec_probe.c from linux kernel:
6 * (C) 2000 Red Hat. GPL'd.
7 * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 /* The DEBUG define must be before common to enable debugging */
33 #include <asm/processor.h>
35 #include <asm/byteorder.h>
36 #include <environment.h>
38 #define P_ID_AMD_STD CFI_CMDSET_AMD_LEGACY
41 #define AM29DL800BB 0x22CB
42 #define AM29DL800BT 0x224A
44 #define AM29F400BB 0x22AB
45 #define AM29F800BB 0x2258
46 #define AM29F800BT 0x22D6
47 #define AM29LV400BB 0x22BA
48 #define AM29LV400BT 0x22B9
49 #define AM29LV800BB 0x225B
50 #define AM29LV800BT 0x22DA
51 #define AM29LV160DT 0x22C4
52 #define AM29LV160DB 0x2249
53 #define AM29F017D 0x003D
54 #define AM29F016D 0x00AD
55 #define AM29F080 0x00D5
56 #define AM29F040 0x00A4
57 #define AM29LV040B 0x004F
58 #define AM29F032B 0x0041
59 #define AM29F002T 0x00B0
62 #define SST39LF800 0x2781
63 #define SST39LF160 0x2782
64 #define SST39VF1601 0x234b
65 #define SST39LF512 0x00D4
66 #define SST39LF010 0x00D5
67 #define SST39LF020 0x00D6
68 #define SST39LF040 0x00D7
69 #define SST39SF010A 0x00B5
70 #define SST39SF020A 0x00B6
73 #define STM29F400BB 0x00D6
76 #define MX29LV040 0x004F
79 #define W39L040A 0x00D6
82 #define A29L040 0x0092
85 #define EN29LV040A 0x004F
88 * Unlock address sets for AMD command sets.
89 * Intel command sets use the MTD_UADDR_UNNECESSARY.
90 * Each identifier, except MTD_UADDR_UNNECESSARY, and
91 * MTD_UADDR_NO_SUPPORT must be defined below in unlock_addrs[].
92 * MTD_UADDR_NOT_SUPPORTED must be 0 so that structure
93 * initialization need not require initializing all of the
94 * unlock addresses for all bit widths.
97 MTD_UADDR_NOT_SUPPORTED = 0, /* data width not supported */
98 MTD_UADDR_0x0555_0x02AA,
99 MTD_UADDR_0x0555_0x0AAA,
100 MTD_UADDR_0x5555_0x2AAA,
101 MTD_UADDR_0x0AAA_0x0555,
102 MTD_UADDR_DONT_CARE, /* Requires an arbitrary address */
103 MTD_UADDR_UNNECESSARY, /* Does not require any address */
114 * I don't like the fact that the first entry in unlock_addrs[]
115 * exists, but is for MTD_UADDR_NOT_SUPPORTED - and, therefore,
116 * should not be used. The problem is that structures with
117 * initializers have extra fields initialized to 0. It is _very_
118 * desireable to have the unlock address entries for unsupported
119 * data widths automatically initialized - that means that
120 * MTD_UADDR_NOT_SUPPORTED must be 0 and the first entry here
123 static const struct unlock_addr unlock_addrs[] = {
124 [MTD_UADDR_NOT_SUPPORTED] = {
129 [MTD_UADDR_0x0555_0x02AA] = {
134 [MTD_UADDR_0x0555_0x0AAA] = {
139 [MTD_UADDR_0x5555_0x2AAA] = {
144 [MTD_UADDR_0x0AAA_0x0555] = {
149 [MTD_UADDR_DONT_CARE] = {
150 .addr1 = 0x0000, /* Doesn't matter which address */
151 .addr2 = 0x0000 /* is used - must be last entry */
154 [MTD_UADDR_UNNECESSARY] = {
161 struct amd_flash_info {
166 const int NumEraseRegions;
168 const __u8 uaddr[4]; /* unlock addrs for 8, 16, 32, 64 */
169 const ulong regions[6];
172 #define ERASEINFO(size,blocks) (size<<8)|(blocks-1)
174 #define SIZE_64KiB 16
175 #define SIZE_128KiB 17
176 #define SIZE_256KiB 18
177 #define SIZE_512KiB 19
183 static const struct amd_flash_info jedec_table[] = {
184 #ifdef CONFIG_SYS_FLASH_LEGACY_256Kx8
186 .mfr_id = (u16)SST_MANUFACT,
187 .dev_id = SST39LF020,
188 .name = "SST 39LF020",
190 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
192 .DevSize = SIZE_256KiB,
193 .CmdSet = P_ID_AMD_STD,
196 ERASEINFO(0x01000,64),
200 #ifdef CONFIG_SYS_FLASH_LEGACY_512Kx8
202 .mfr_id = (u16)AMD_MANUFACT,
203 .dev_id = AM29LV040B,
204 .name = "AMD AM29LV040B",
206 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
208 .DevSize = SIZE_512KiB,
209 .CmdSet = P_ID_AMD_STD,
212 ERASEINFO(0x10000,8),
216 .mfr_id = (u16)SST_MANUFACT,
217 .dev_id = SST39LF040,
218 .name = "SST 39LF040",
220 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
222 .DevSize = SIZE_512KiB,
223 .CmdSet = P_ID_AMD_STD,
226 ERASEINFO(0x01000,128),
230 .mfr_id = (u16)STM_MANUFACT,
231 .dev_id = STM_ID_M29W040B,
232 .name = "ST Micro M29W040B",
234 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
236 .DevSize = SIZE_512KiB,
237 .CmdSet = P_ID_AMD_STD,
240 ERASEINFO(0x10000,8),
244 .mfr_id = (u16)MX_MANUFACT,
246 .name = "MXIC MX29LV040",
248 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
250 .DevSize = SIZE_512KiB,
251 .CmdSet = P_ID_AMD_STD,
254 ERASEINFO(0x10000, 8),
258 .mfr_id = (u16)WINB_MANUFACT,
260 .name = "WINBOND W39L040A",
262 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
264 .DevSize = SIZE_512KiB,
265 .CmdSet = P_ID_AMD_STD,
268 ERASEINFO(0x10000, 8),
272 .mfr_id = (u16)AMIC_MANUFACT,
274 .name = "AMIC A29L040",
276 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
278 .DevSize = SIZE_512KiB,
279 .CmdSet = P_ID_AMD_STD,
282 ERASEINFO(0x10000, 8),
286 .mfr_id = (u16)EON_MANUFACT,
287 .dev_id = EN29LV040A,
288 .name = "EON EN29LV040A",
290 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
292 .DevSize = SIZE_512KiB,
293 .CmdSet = P_ID_AMD_STD,
296 ERASEINFO(0x10000, 8),
300 #ifdef CONFIG_SYS_FLASH_LEGACY_512Kx16
302 .mfr_id = (u16)AMD_MANUFACT,
303 .dev_id = AM29F400BB,
304 .name = "AMD AM29F400BB",
306 [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
308 .DevSize = SIZE_512KiB,
309 .CmdSet = CFI_CMDSET_AMD_LEGACY,
312 ERASEINFO(0x04000, 1),
313 ERASEINFO(0x02000, 2),
314 ERASEINFO(0x08000, 1),
315 ERASEINFO(0x10000, 7),
319 .mfr_id = (u16)AMD_MANUFACT,
320 .dev_id = AM29LV400BB,
321 .name = "AMD AM29LV400BB",
323 [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
325 .DevSize = SIZE_512KiB,
326 .CmdSet = CFI_CMDSET_AMD_LEGACY,
329 ERASEINFO(0x04000,1),
330 ERASEINFO(0x02000,2),
331 ERASEINFO(0x08000,1),
332 ERASEINFO(0x10000,7),
336 .mfr_id = (u16)AMD_MANUFACT,
337 .dev_id = AM29LV800BB,
338 .name = "AMD AM29LV800BB",
340 [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
342 .DevSize = SIZE_1MiB,
343 .CmdSet = CFI_CMDSET_AMD_LEGACY,
346 ERASEINFO(0x04000, 1),
347 ERASEINFO(0x02000, 2),
348 ERASEINFO(0x08000, 1),
349 ERASEINFO(0x10000, 15),
353 .mfr_id = (u16)STM_MANUFACT,
354 .dev_id = STM29F400BB,
355 .name = "ST Micro M29F400BB",
357 [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
359 .DevSize = SIZE_512KiB,
360 .CmdSet = CFI_CMDSET_AMD_LEGACY,
361 .NumEraseRegions = 4,
363 ERASEINFO(0x04000, 1),
364 ERASEINFO(0x02000, 2),
365 ERASEINFO(0x08000, 1),
366 ERASEINFO(0x10000, 7),
372 static inline void fill_info(flash_info_t *info, const struct amd_flash_info *jedec_entry, ulong base)
378 enum uaddr uaddr_idx;
380 size_ratio = info->portwidth / info->chipwidth;
382 debug("Found JEDEC Flash: %s\n", jedec_entry->name);
383 info->vendor = jedec_entry->CmdSet;
384 /* Todo: do we need device-specific timeouts? */
385 info->erase_blk_tout = 30000;
386 info->buffer_write_tout = 1000;
387 info->write_tout = 100;
388 info->name = jedec_entry->name;
390 /* copy unlock addresses from device table to CFI info struct. This
391 is just here because the addresses are in the table anyway - if
392 the flash is not detected due to wrong unlock addresses,
393 flash_detect_legacy would have to try all of them before we even
395 switch(info->chipwidth) {
397 uaddr_idx = jedec_entry->uaddr[0];
399 case FLASH_CFI_16BIT:
400 uaddr_idx = jedec_entry->uaddr[1];
402 case FLASH_CFI_32BIT:
403 uaddr_idx = jedec_entry->uaddr[2];
406 uaddr_idx = MTD_UADDR_NOT_SUPPORTED;
410 debug("unlock address index %d\n", uaddr_idx);
411 info->addr_unlock1 = unlock_addrs[uaddr_idx].addr1;
412 info->addr_unlock2 = unlock_addrs[uaddr_idx].addr2;
413 debug("unlock addresses are 0x%lx/0x%lx\n",
414 info->addr_unlock1, info->addr_unlock2);
418 for (i = 0; i < jedec_entry->NumEraseRegions; i++) {
419 ulong erase_region_size = jedec_entry->regions[i] >> 8;
420 ulong erase_region_count = (jedec_entry->regions[i] & 0xff) + 1;
422 total_size += erase_region_size * erase_region_count;
423 debug("erase_region_count = %ld erase_region_size = %ld\n",
424 erase_region_count, erase_region_size);
425 for (j = 0; j < erase_region_count; j++) {
426 if (sect_cnt >= CONFIG_SYS_MAX_FLASH_SECT) {
427 printf("ERROR: too many flash sectors\n");
430 info->start[sect_cnt] = base;
431 base += (erase_region_size * size_ratio);
435 info->sector_count = sect_cnt;
436 info->size = total_size * size_ratio;
439 /*-----------------------------------------------------------------------
440 * match jedec ids against table. If a match is found, fill flash_info entry
442 int jedec_flash_match(flash_info_t *info, ulong base)
447 if (info->chipwidth == 1)
450 for (i = 0; i < ARRAY_SIZE(jedec_table); i++) {
451 if ((jedec_table[i].mfr_id & mask) == (info->manufacturer_id & mask) &&
452 (jedec_table[i].dev_id & mask) == (info->device_id & mask)) {
453 fill_info(info, &jedec_table[i], base);