2 * Arasan NAND Flash Controller Driver
4 * Copyright (C) 2014 - 2015 Xilinx, Inc.
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/errno.h>
13 #include <linux/mtd/mtd.h>
14 #include <linux/mtd/rawnand.h>
15 #include <linux/mtd/partitions.h>
16 #include <linux/mtd/nand_ecc.h>
17 #include <asm/arch/hardware.h>
18 #include <asm/arch/sys_proto.h>
21 struct arasan_nand_info {
22 void __iomem *nand_base;
24 bool on_die_ecc_enabled;
58 #define arasan_nand_base ((struct nand_regs __iomem *)ARASAN_NAND_BASEADDR)
60 struct arasan_nand_command_format {
67 #define ONDIE_ECC_FEATURE_ADDR 0x90
68 #define ENABLE_ONDIE_ECC 0x08
70 #define ARASAN_PROG_RD_MASK 0x00000001
71 #define ARASAN_PROG_BLK_ERS_MASK 0x00000004
72 #define ARASAN_PROG_RD_ID_MASK 0x00000040
73 #define ARASAN_PROG_RD_STS_MASK 0x00000008
74 #define ARASAN_PROG_PG_PROG_MASK 0x00000010
75 #define ARASAN_PROG_RD_PARAM_PG_MASK 0x00000080
76 #define ARASAN_PROG_RST_MASK 0x00000100
77 #define ARASAN_PROG_GET_FTRS_MASK 0x00000200
78 #define ARASAN_PROG_SET_FTRS_MASK 0x00000400
79 #define ARASAN_PROG_CHNG_ROWADR_END_MASK 0x00400000
81 #define ARASAN_NAND_CMD_ECC_ON_MASK 0x80000000
82 #define ARASAN_NAND_CMD_CMD12_MASK 0xFFFF
83 #define ARASAN_NAND_CMD_PG_SIZE_MASK 0x3800000
84 #define ARASAN_NAND_CMD_PG_SIZE_SHIFT 23
85 #define ARASAN_NAND_CMD_CMD2_SHIFT 8
86 #define ARASAN_NAND_CMD_ADDR_CYCL_MASK 0x70000000
87 #define ARASAN_NAND_CMD_ADDR_CYCL_SHIFT 28
89 #define ARASAN_NAND_MEM_ADDR1_PAGE_MASK 0xFFFF
90 #define ARASAN_NAND_MEM_ADDR1_COL_MASK 0xFFFF
91 #define ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT 16
92 #define ARASAN_NAND_MEM_ADDR2_PAGE_MASK 0xFF
93 #define ARASAN_NAND_MEM_ADDR2_CS_MASK 0xC0000000
94 #define ARASAN_NAND_MEM_ADDR2_BCH_MASK 0xE000000
95 #define ARASAN_NAND_MEM_ADDR2_BCH_SHIFT 25
97 #define ARASAN_NAND_INT_STS_ERR_EN_MASK 0x10
98 #define ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK 0x08
99 #define ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK 0x02
100 #define ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK 0x01
101 #define ARASAN_NAND_INT_STS_XFR_CMPLT_MASK 0x04
103 #define ARASAN_NAND_PKT_REG_PKT_CNT_MASK 0xFFF000
104 #define ARASAN_NAND_PKT_REG_PKT_SIZE_MASK 0x7FF
105 #define ARASAN_NAND_PKT_REG_PKT_CNT_SHFT 12
107 #define ARASAN_NAND_ROW_ADDR_CYCL_MASK 0x0F
108 #define ARASAN_NAND_COL_ADDR_CYCL_MASK 0xF0
109 #define ARASAN_NAND_COL_ADDR_CYCL_SHIFT 4
111 #define ARASAN_NAND_ECC_SIZE_SHIFT 16
112 #define ARASAN_NAND_ECC_BCH_SHIFT 27
114 #define ARASAN_NAND_PKTSIZE_1K 1024
115 #define ARASAN_NAND_PKTSIZE_512 512
117 #define ARASAN_NAND_POLL_TIMEOUT 1000000
118 #define ARASAN_NAND_INVALID_ADDR_CYCL 0xFF
120 #define ERR_ADDR_CYCLE -1
121 #define READ_BUFF_SIZE 0x4000
123 static struct arasan_nand_command_format *curr_cmd;
133 static struct arasan_nand_command_format arasan_nand_commands[] = {
134 {NAND_CMD_READ0, NAND_CMD_READSTART, NAND_ADDR_CYCL_BOTH,
135 ARASAN_PROG_RD_MASK},
136 {NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, NAND_ADDR_CYCL_COL,
137 ARASAN_PROG_RD_MASK},
138 {NAND_CMD_READID, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE,
139 ARASAN_PROG_RD_ID_MASK},
140 {NAND_CMD_STATUS, NAND_CMD_NONE, NAND_ADDR_CYCL_NONE,
141 ARASAN_PROG_RD_STS_MASK},
142 {NAND_CMD_SEQIN, NAND_CMD_PAGEPROG, NAND_ADDR_CYCL_BOTH,
143 ARASAN_PROG_PG_PROG_MASK},
144 {NAND_CMD_RNDIN, NAND_CMD_NONE, NAND_ADDR_CYCL_COL,
145 ARASAN_PROG_CHNG_ROWADR_END_MASK},
146 {NAND_CMD_ERASE1, NAND_CMD_ERASE2, NAND_ADDR_CYCL_ROW,
147 ARASAN_PROG_BLK_ERS_MASK},
148 {NAND_CMD_RESET, NAND_CMD_NONE, NAND_ADDR_CYCL_NONE,
149 ARASAN_PROG_RST_MASK},
150 {NAND_CMD_PARAM, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE,
151 ARASAN_PROG_RD_PARAM_PG_MASK},
152 {NAND_CMD_GET_FEATURES, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE,
153 ARASAN_PROG_GET_FTRS_MASK},
154 {NAND_CMD_SET_FEATURES, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE,
155 ARASAN_PROG_SET_FTRS_MASK},
156 {NAND_CMD_NONE, NAND_CMD_NONE, NAND_ADDR_CYCL_NONE, 0},
159 struct arasan_ecc_matrix {
161 u32 ecc_codeword_size;
169 static const struct arasan_ecc_matrix ecc_matrix[] = {
170 {512, 512, 1, 0, 0, 0x20D, 0x3},
171 {512, 512, 4, 1, 3, 0x209, 0x7},
172 {512, 512, 8, 1, 2, 0x203, 0xD},
176 {2048, 512, 1, 0, 0, 0x834, 0xC},
177 {2048, 512, 4, 1, 3, 0x826, 0x1A},
178 {2048, 512, 8, 1, 2, 0x80c, 0x34},
179 {2048, 512, 12, 1, 1, 0x822, 0x4E},
180 {2048, 512, 16, 1, 0, 0x808, 0x68},
181 {2048, 1024, 24, 1, 4, 0x81c, 0x54},
185 {4096, 512, 1, 0, 0, 0x1068, 0x18},
186 {4096, 512, 4, 1, 3, 0x104c, 0x34},
187 {4096, 512, 8, 1, 2, 0x1018, 0x68},
188 {4096, 512, 12, 1, 1, 0x1044, 0x9C},
189 {4096, 512, 16, 1, 0, 0x1010, 0xD0},
190 {4096, 1024, 24, 1, 4, 0x1038, 0xA8},
194 {8192, 512, 1, 0, 0, 0x20d0, 0x30},
195 {8192, 512, 4, 1, 3, 0x2098, 0x68},
196 {8192, 512, 8, 1, 2, 0x2030, 0xD0},
197 {8192, 512, 12, 1, 1, 0x2088, 0x138},
198 {8192, 512, 16, 1, 0, 0x2020, 0x1A0},
199 {8192, 1024, 24, 1, 4, 0x2070, 0x150},
203 {16384, 512, 1, 0, 0, 0x4460, 0x60},
204 {16384, 512, 4, 1, 3, 0x43f0, 0xD0},
205 {16384, 512, 8, 1, 2, 0x4320, 0x1A0},
206 {16384, 512, 12, 1, 1, 0x4250, 0x270},
207 {16384, 512, 16, 1, 0, 0x4180, 0x340},
208 {16384, 1024, 24, 1, 4, 0x4220, 0x2A0}
211 static struct nand_ecclayout ondie_nand_oob_64 = {
215 8, 9, 10, 11, 12, 13, 14, 15,
216 24, 25, 26, 27, 28, 29, 30, 31,
217 40, 41, 42, 43, 44, 45, 46, 47,
218 56, 57, 58, 59, 60, 61, 62, 63
222 { .offset = 4, .length = 4 },
223 { .offset = 20, .length = 4 },
224 { .offset = 36, .length = 4 },
225 { .offset = 52, .length = 4 }
230 * bbt decriptors for chips with on-die ECC and
231 * chips with 64-byte OOB
233 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
234 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
236 static struct nand_bbt_descr bbt_main_descr = {
237 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
238 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
243 .pattern = bbt_pattern
246 static struct nand_bbt_descr bbt_mirror_descr = {
247 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
248 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
253 .pattern = mirror_pattern
256 static u8 buf_data[READ_BUFF_SIZE];
257 static u32 buf_index;
259 static struct nand_ecclayout nand_oob;
261 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
263 static void arasan_nand_select_chip(struct mtd_info *mtd, int chip)
267 static void arasan_nand_enable_ecc(void)
271 reg_val = readl(&arasan_nand_base->cmd_reg);
272 reg_val |= ARASAN_NAND_CMD_ECC_ON_MASK;
274 writel(reg_val, &arasan_nand_base->cmd_reg);
277 static u8 arasan_nand_get_addrcycle(struct mtd_info *mtd)
280 struct nand_chip *chip = mtd_to_nand(mtd);
282 switch (curr_cmd->addr_cycles) {
283 case NAND_ADDR_CYCL_NONE:
286 case NAND_ADDR_CYCL_ONE:
289 case NAND_ADDR_CYCL_ROW:
290 addrcycles = chip->onfi_params.addr_cycles &
291 ARASAN_NAND_ROW_ADDR_CYCL_MASK;
293 case NAND_ADDR_CYCL_COL:
294 addrcycles = (chip->onfi_params.addr_cycles &
295 ARASAN_NAND_COL_ADDR_CYCL_MASK) >>
296 ARASAN_NAND_COL_ADDR_CYCL_SHIFT;
298 case NAND_ADDR_CYCL_BOTH:
299 addrcycles = chip->onfi_params.addr_cycles &
300 ARASAN_NAND_ROW_ADDR_CYCL_MASK;
301 addrcycles += (chip->onfi_params.addr_cycles &
302 ARASAN_NAND_COL_ADDR_CYCL_MASK) >>
303 ARASAN_NAND_COL_ADDR_CYCL_SHIFT;
306 addrcycles = ARASAN_NAND_INVALID_ADDR_CYCL;
312 static int arasan_nand_read_page(struct mtd_info *mtd, u8 *buf, u32 size)
314 struct nand_chip *chip = mtd_to_nand(mtd);
315 struct arasan_nand_info *nand = nand_get_controller_data(chip);
316 u32 reg_val, i, pktsize, pktnum;
317 u32 *bufptr = (u32 *)buf;
322 if (chip->ecc_step_ds >= ARASAN_NAND_PKTSIZE_1K)
323 pktsize = ARASAN_NAND_PKTSIZE_1K;
325 pktsize = ARASAN_NAND_PKTSIZE_512;
328 pktnum = size/pktsize + 1;
330 pktnum = size/pktsize;
332 reg_val = readl(&arasan_nand_base->intsts_enr);
333 reg_val |= ARASAN_NAND_INT_STS_ERR_EN_MASK |
334 ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK;
335 writel(reg_val, &arasan_nand_base->intsts_enr);
337 reg_val = readl(&arasan_nand_base->pkt_reg);
338 reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK |
339 ARASAN_NAND_PKT_REG_PKT_SIZE_MASK);
340 reg_val |= (pktnum << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) |
342 writel(reg_val, &arasan_nand_base->pkt_reg);
344 if (!nand->on_die_ecc_enabled) {
345 arasan_nand_enable_ecc();
346 addr_cycles = arasan_nand_get_addrcycle(mtd);
347 if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL)
348 return ERR_ADDR_CYCLE;
350 writel((NAND_CMD_RNDOUTSTART << ARASAN_NAND_CMD_CMD2_SHIFT) |
351 NAND_CMD_RNDOUT | (addr_cycles <<
352 ARASAN_NAND_CMD_ADDR_CYCL_SHIFT),
353 &arasan_nand_base->ecc_sprcmd_reg);
355 writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
357 while (rdcount < pktnum) {
358 timeout = ARASAN_NAND_POLL_TIMEOUT;
359 while (!(readl(&arasan_nand_base->intsts_reg) &
360 ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK) && timeout) {
365 puts("arasan_read_page: timedout:Buff RDY\n");
371 if (pktnum == rdcount) {
372 reg_val = readl(&arasan_nand_base->intsts_enr);
373 reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK;
374 writel(reg_val, &arasan_nand_base->intsts_enr);
376 reg_val = readl(&arasan_nand_base->intsts_enr);
377 writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
378 &arasan_nand_base->intsts_enr);
380 reg_val = readl(&arasan_nand_base->intsts_reg);
381 writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
382 &arasan_nand_base->intsts_reg);
384 for (i = 0; i < pktsize/4; i++)
385 bufptr[i] = readl(&arasan_nand_base->buf_dataport);
390 if (rdcount >= pktnum)
393 writel(ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
394 &arasan_nand_base->intsts_enr);
397 timeout = ARASAN_NAND_POLL_TIMEOUT;
399 while (!(readl(&arasan_nand_base->intsts_reg) &
400 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
405 puts("arasan rd_page timedout:Xfer CMPLT\n");
409 reg_val = readl(&arasan_nand_base->intsts_enr);
410 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
411 &arasan_nand_base->intsts_enr);
412 reg_val = readl(&arasan_nand_base->intsts_reg);
413 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
414 &arasan_nand_base->intsts_reg);
416 if (!nand->on_die_ecc_enabled) {
417 if (readl(&arasan_nand_base->intsts_reg) &
418 ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK) {
419 printf("arasan rd_page:sbiterror\n");
423 if (readl(&arasan_nand_base->intsts_reg) &
424 ARASAN_NAND_INT_STS_ERR_EN_MASK) {
425 mtd->ecc_stats.failed++;
426 printf("arasan rd_page:multibiterror\n");
434 static int arasan_nand_read_page_hwecc(struct mtd_info *mtd,
435 struct nand_chip *chip, u8 *buf, int oob_required, int page)
439 status = arasan_nand_read_page(mtd, buf, (mtd->writesize));
442 chip->ecc.read_oob(mtd, chip, page);
447 static void arasan_nand_fill_tx(const u8 *buf, int len)
449 u32 __iomem *nand = &arasan_nand_base->buf_dataport;
451 if (((unsigned long)buf & 0x3) != 0) {
452 if (((unsigned long)buf & 0x1) != 0) {
460 if (((unsigned long)buf & 0x3) != 0) {
462 writew(*(u16 *)buf, nand);
470 writel(*(u32 *)buf, nand);
477 writew(*(u16 *)buf, nand);
487 static int arasan_nand_write_page_hwecc(struct mtd_info *mtd,
488 struct nand_chip *chip, const u8 *buf, int oob_required,
491 u32 reg_val, i, pktsize, pktnum;
492 const u32 *bufptr = (const u32 *)buf;
493 u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
494 u32 size = mtd->writesize;
496 u8 column_addr_cycles;
497 struct arasan_nand_info *nand = nand_get_controller_data(chip);
499 if (chip->ecc_step_ds >= ARASAN_NAND_PKTSIZE_1K)
500 pktsize = ARASAN_NAND_PKTSIZE_1K;
502 pktsize = ARASAN_NAND_PKTSIZE_512;
505 pktnum = size/pktsize + 1;
507 pktnum = size/pktsize;
509 reg_val = readl(&arasan_nand_base->pkt_reg);
510 reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK |
511 ARASAN_NAND_PKT_REG_PKT_SIZE_MASK);
512 reg_val |= (pktnum << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | pktsize;
513 writel(reg_val, &arasan_nand_base->pkt_reg);
515 if (!nand->on_die_ecc_enabled) {
516 arasan_nand_enable_ecc();
517 column_addr_cycles = (chip->onfi_params.addr_cycles &
518 ARASAN_NAND_COL_ADDR_CYCL_MASK) >>
519 ARASAN_NAND_COL_ADDR_CYCL_SHIFT;
520 writel((NAND_CMD_RNDIN | (column_addr_cycles << 28)),
521 &arasan_nand_base->ecc_sprcmd_reg);
523 writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
525 while (rdcount < pktnum) {
526 timeout = ARASAN_NAND_POLL_TIMEOUT;
527 while (!(readl(&arasan_nand_base->intsts_reg) &
528 ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK) && timeout) {
534 puts("arasan_write_page: timedout:Buff RDY\n");
540 if (pktnum == rdcount) {
541 reg_val = readl(&arasan_nand_base->intsts_enr);
542 reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK;
543 writel(reg_val, &arasan_nand_base->intsts_enr);
545 reg_val = readl(&arasan_nand_base->intsts_enr);
546 writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
547 &arasan_nand_base->intsts_enr);
550 reg_val = readl(&arasan_nand_base->intsts_reg);
551 writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
552 &arasan_nand_base->intsts_reg);
554 for (i = 0; i < pktsize/4; i++)
555 writel(bufptr[i], &arasan_nand_base->buf_dataport);
559 if (rdcount >= pktnum)
562 writel(ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
563 &arasan_nand_base->intsts_enr);
566 timeout = ARASAN_NAND_POLL_TIMEOUT;
568 while (!(readl(&arasan_nand_base->intsts_reg) &
569 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
574 puts("arasan write_page timedout:Xfer CMPLT\n");
578 reg_val = readl(&arasan_nand_base->intsts_enr);
579 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
580 &arasan_nand_base->intsts_enr);
581 reg_val = readl(&arasan_nand_base->intsts_reg);
582 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
583 &arasan_nand_base->intsts_reg);
586 chip->ecc.write_oob(mtd, chip, nand->page);
591 static int arasan_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
594 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
595 chip->read_buf(mtd, chip->oob_poi, (mtd->oobsize));
600 static int arasan_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
604 const u8 *buf = chip->oob_poi;
606 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
607 chip->write_buf(mtd, buf, mtd->oobsize);
612 static int arasan_nand_reset(struct arasan_nand_command_format *curr_cmd)
614 u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
617 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
618 &arasan_nand_base->intsts_enr);
619 cmd_reg = readl(&arasan_nand_base->cmd_reg);
620 cmd_reg &= ~ARASAN_NAND_CMD_CMD12_MASK;
622 cmd_reg |= curr_cmd->cmd1 |
623 (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT);
624 writel(cmd_reg, &arasan_nand_base->cmd_reg);
625 writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
627 while (!(readl(&arasan_nand_base->intsts_reg) &
628 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
633 printf("ERROR:%s timedout\n", __func__);
637 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
638 &arasan_nand_base->intsts_enr);
640 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
641 &arasan_nand_base->intsts_reg);
646 static u8 arasan_nand_page(struct mtd_info *mtd)
650 switch (mtd->writesize) {
670 printf("%s:Pagesize>16K\n", __func__);
677 static int arasan_nand_send_wrcmd(struct arasan_nand_command_format *curr_cmd,
678 int column, int page_addr, struct mtd_info *mtd)
681 u8 page_val, addr_cycles;
683 writel(ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
684 &arasan_nand_base->intsts_enr);
685 reg_val = readl(&arasan_nand_base->cmd_reg);
686 reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK;
687 reg_val |= curr_cmd->cmd1 |
688 (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT);
689 if (curr_cmd->cmd1 == NAND_CMD_SEQIN) {
690 reg_val &= ~ARASAN_NAND_CMD_PG_SIZE_MASK;
691 page_val = arasan_nand_page(mtd);
692 reg_val |= (page_val << ARASAN_NAND_CMD_PG_SIZE_SHIFT);
695 reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK;
696 addr_cycles = arasan_nand_get_addrcycle(mtd);
698 if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL)
699 return ERR_ADDR_CYCLE;
701 reg_val |= (addr_cycles <<
702 ARASAN_NAND_CMD_ADDR_CYCL_SHIFT);
703 writel(reg_val, &arasan_nand_base->cmd_reg);
708 page = (page_addr << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) &
709 ARASAN_NAND_MEM_ADDR1_PAGE_MASK;
710 column &= ARASAN_NAND_MEM_ADDR1_COL_MASK;
711 writel(page|column, &arasan_nand_base->memadr_reg1);
713 reg_val = readl(&arasan_nand_base->memadr_reg2);
714 reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK;
715 reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT);
716 writel(reg_val, &arasan_nand_base->memadr_reg2);
717 reg_val = readl(&arasan_nand_base->memadr_reg2);
718 reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS_MASK;
719 writel(reg_val, &arasan_nand_base->memadr_reg2);
724 static void arasan_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
727 u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
729 reg_val = readl(&arasan_nand_base->pkt_reg);
730 reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK |
731 ARASAN_NAND_PKT_REG_PKT_SIZE_MASK);
733 reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | len;
734 writel(reg_val, &arasan_nand_base->pkt_reg);
735 writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
737 while (!(readl(&arasan_nand_base->intsts_reg) &
738 ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK) && timeout) {
744 puts("ERROR:arasan_nand_write_buf timedout:Buff RDY\n");
746 reg_val = readl(&arasan_nand_base->intsts_enr);
747 reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK;
748 writel(reg_val, &arasan_nand_base->intsts_enr);
749 writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
750 &arasan_nand_base->intsts_enr);
751 reg_val = readl(&arasan_nand_base->intsts_reg);
752 writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
753 &arasan_nand_base->intsts_reg);
755 arasan_nand_fill_tx(buf, len);
757 timeout = ARASAN_NAND_POLL_TIMEOUT;
758 while (!(readl(&arasan_nand_base->intsts_reg) &
759 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
764 puts("ERROR:arasan_nand_write_buf timedout:Xfer CMPLT\n");
766 writel(readl(&arasan_nand_base->intsts_enr) |
767 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
768 &arasan_nand_base->intsts_enr);
769 writel(readl(&arasan_nand_base->intsts_reg) |
770 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
771 &arasan_nand_base->intsts_reg);
774 static int arasan_nand_erase(struct arasan_nand_command_format *curr_cmd,
775 int column, int page_addr, struct mtd_info *mtd)
778 u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
781 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
782 &arasan_nand_base->intsts_enr);
783 reg_val = readl(&arasan_nand_base->cmd_reg);
784 reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK;
785 reg_val |= curr_cmd->cmd1 |
786 (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT);
787 row_addr_cycles = arasan_nand_get_addrcycle(mtd);
789 if (row_addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL)
790 return ERR_ADDR_CYCLE;
792 reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK;
793 reg_val |= (row_addr_cycles <<
794 ARASAN_NAND_CMD_ADDR_CYCL_SHIFT);
796 writel(reg_val, &arasan_nand_base->cmd_reg);
798 page = (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) &
799 ARASAN_NAND_MEM_ADDR1_PAGE_MASK;
800 column = page_addr & ARASAN_NAND_MEM_ADDR1_COL_MASK;
801 writel(column | (page << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT),
802 &arasan_nand_base->memadr_reg1);
804 reg_val = readl(&arasan_nand_base->memadr_reg2);
805 reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK;
806 reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT);
807 writel(reg_val, &arasan_nand_base->memadr_reg2);
808 reg_val = readl(&arasan_nand_base->memadr_reg2);
809 reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS_MASK;
810 writel(reg_val, &arasan_nand_base->memadr_reg2);
811 writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
813 while (!(readl(&arasan_nand_base->intsts_reg) &
814 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
819 printf("ERROR:%s timedout:Xfer CMPLT\n", __func__);
823 reg_val = readl(&arasan_nand_base->intsts_enr);
824 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
825 &arasan_nand_base->intsts_enr);
826 reg_val = readl(&arasan_nand_base->intsts_reg);
827 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
828 &arasan_nand_base->intsts_reg);
833 static int arasan_nand_read_status(struct arasan_nand_command_format *curr_cmd,
834 int column, int page_addr, struct mtd_info *mtd)
837 u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
840 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
841 &arasan_nand_base->intsts_enr);
842 reg_val = readl(&arasan_nand_base->cmd_reg);
843 reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK;
844 reg_val |= curr_cmd->cmd1 |
845 (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT);
846 addr_cycles = arasan_nand_get_addrcycle(mtd);
848 if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL)
849 return ERR_ADDR_CYCLE;
851 reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK;
852 reg_val |= (addr_cycles <<
853 ARASAN_NAND_CMD_ADDR_CYCL_SHIFT);
855 writel(reg_val, &arasan_nand_base->cmd_reg);
857 reg_val = readl(&arasan_nand_base->pkt_reg);
858 reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK |
859 ARASAN_NAND_PKT_REG_PKT_SIZE_MASK);
860 reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | 1;
861 writel(reg_val, &arasan_nand_base->pkt_reg);
863 reg_val = readl(&arasan_nand_base->memadr_reg2);
864 reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS_MASK;
865 writel(reg_val, &arasan_nand_base->memadr_reg2);
867 writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
868 while (!(readl(&arasan_nand_base->intsts_reg) &
869 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
875 printf("ERROR:%s: timedout:Xfer CMPLT\n", __func__);
879 reg_val = readl(&arasan_nand_base->intsts_enr);
880 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
881 &arasan_nand_base->intsts_enr);
882 reg_val = readl(&arasan_nand_base->intsts_reg);
883 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
884 &arasan_nand_base->intsts_reg);
889 static int arasan_nand_send_rdcmd(struct arasan_nand_command_format *curr_cmd,
890 int column, int page_addr, struct mtd_info *mtd)
892 u32 reg_val, addr_cycles, page;
895 reg_val = readl(&arasan_nand_base->intsts_enr);
896 writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
897 &arasan_nand_base->intsts_enr);
899 reg_val = readl(&arasan_nand_base->cmd_reg);
900 reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK;
901 reg_val |= curr_cmd->cmd1 |
902 (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT);
904 if (curr_cmd->cmd1 == NAND_CMD_RNDOUT ||
905 curr_cmd->cmd1 == NAND_CMD_READ0) {
906 reg_val &= ~ARASAN_NAND_CMD_PG_SIZE_MASK;
907 page_val = arasan_nand_page(mtd);
908 reg_val |= (page_val << ARASAN_NAND_CMD_PG_SIZE_SHIFT);
911 reg_val &= ~ARASAN_NAND_CMD_ECC_ON_MASK;
913 reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK;
915 addr_cycles = arasan_nand_get_addrcycle(mtd);
917 if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL)
918 return ERR_ADDR_CYCLE;
920 reg_val |= (addr_cycles << 28);
921 writel(reg_val, &arasan_nand_base->cmd_reg);
926 page = (page_addr << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) &
927 ARASAN_NAND_MEM_ADDR1_PAGE_MASK;
928 column &= ARASAN_NAND_MEM_ADDR1_COL_MASK;
929 writel(page | column, &arasan_nand_base->memadr_reg1);
931 reg_val = readl(&arasan_nand_base->memadr_reg2);
932 reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK;
933 reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT);
934 writel(reg_val, &arasan_nand_base->memadr_reg2);
936 reg_val = readl(&arasan_nand_base->memadr_reg2);
937 reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS_MASK;
938 writel(reg_val, &arasan_nand_base->memadr_reg2);
944 static void arasan_nand_read_buf(struct mtd_info *mtd, u8 *buf, int size)
947 u32 *bufptr = (u32 *)buf;
948 u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
950 reg_val = readl(&arasan_nand_base->pkt_reg);
951 reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK |
952 ARASAN_NAND_PKT_REG_PKT_SIZE_MASK);
953 reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | size;
954 writel(reg_val, &arasan_nand_base->pkt_reg);
956 writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
958 while (!(readl(&arasan_nand_base->intsts_reg) &
959 ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK) && timeout) {
965 puts("ERROR:arasan_nand_read_buf timedout:Buff RDY\n");
967 reg_val = readl(&arasan_nand_base->intsts_enr);
968 reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK;
969 writel(reg_val, &arasan_nand_base->intsts_enr);
971 writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
972 &arasan_nand_base->intsts_enr);
973 reg_val = readl(&arasan_nand_base->intsts_reg);
974 writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
975 &arasan_nand_base->intsts_reg);
978 for (i = 0; i < size / 4; i++)
979 bufptr[i] = readl(&arasan_nand_base->buf_dataport);
982 bufptr[i] = readl(&arasan_nand_base->buf_dataport);
984 timeout = ARASAN_NAND_POLL_TIMEOUT;
986 while (!(readl(&arasan_nand_base->intsts_reg) &
987 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
993 puts("ERROR:arasan_nand_read_buf timedout:Xfer CMPLT\n");
995 reg_val = readl(&arasan_nand_base->intsts_enr);
996 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
997 &arasan_nand_base->intsts_enr);
998 reg_val = readl(&arasan_nand_base->intsts_reg);
999 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
1000 &arasan_nand_base->intsts_reg);
1003 static u8 arasan_nand_read_byte(struct mtd_info *mtd)
1005 struct nand_chip *chip = mtd_to_nand(mtd);
1008 struct nand_onfi_params *p;
1010 if (buf_index == 0) {
1011 p = &chip->onfi_params;
1012 if (curr_cmd->cmd1 == NAND_CMD_READID)
1014 else if (curr_cmd->cmd1 == NAND_CMD_PARAM)
1015 size = sizeof(struct nand_onfi_params);
1016 else if (curr_cmd->cmd1 == NAND_CMD_RNDOUT)
1017 size = le16_to_cpu(p->ext_param_page_length) * 16;
1018 else if (curr_cmd->cmd1 == NAND_CMD_GET_FEATURES)
1020 else if (curr_cmd->cmd1 == NAND_CMD_STATUS)
1021 return readb(&arasan_nand_base->flash_sts_reg);
1024 chip->read_buf(mtd, &buf_data[0], size);
1027 val = *(&buf_data[0] + buf_index);
1033 static void arasan_nand_cmd_function(struct mtd_info *mtd, unsigned int command,
1034 int column, int page_addr)
1037 struct nand_chip *chip = mtd_to_nand(mtd);
1038 struct arasan_nand_info *nand = nand_get_controller_data(chip);
1041 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
1042 &arasan_nand_base->intsts_enr);
1044 if ((command == NAND_CMD_READOOB) &&
1045 (mtd->writesize > 512)) {
1046 column += mtd->writesize;
1047 command = NAND_CMD_READ0;
1050 /* Get the command format */
1051 for (i = 0; (arasan_nand_commands[i].cmd1 != NAND_CMD_NONE ||
1052 arasan_nand_commands[i].cmd2 != NAND_CMD_NONE); i++) {
1053 if (command == arasan_nand_commands[i].cmd1) {
1054 curr_cmd = &arasan_nand_commands[i];
1059 if (curr_cmd == NULL) {
1060 printf("Unsupported Command; 0x%x\n", command);
1064 if (curr_cmd->cmd1 == NAND_CMD_RESET)
1065 ret = arasan_nand_reset(curr_cmd);
1067 if ((curr_cmd->cmd1 == NAND_CMD_READID) ||
1068 (curr_cmd->cmd1 == NAND_CMD_PARAM) ||
1069 (curr_cmd->cmd1 == NAND_CMD_RNDOUT) ||
1070 (curr_cmd->cmd1 == NAND_CMD_GET_FEATURES) ||
1071 (curr_cmd->cmd1 == NAND_CMD_READ0))
1072 ret = arasan_nand_send_rdcmd(curr_cmd, column, page_addr, mtd);
1074 if ((curr_cmd->cmd1 == NAND_CMD_SET_FEATURES) ||
1075 (curr_cmd->cmd1 == NAND_CMD_SEQIN)) {
1076 nand->page = page_addr;
1077 ret = arasan_nand_send_wrcmd(curr_cmd, column, page_addr, mtd);
1080 if (curr_cmd->cmd1 == NAND_CMD_ERASE1)
1081 ret = arasan_nand_erase(curr_cmd, column, page_addr, mtd);
1083 if (curr_cmd->cmd1 == NAND_CMD_STATUS)
1084 ret = arasan_nand_read_status(curr_cmd, column, page_addr, mtd);
1087 printf("ERROR:%s:command:0x%x\n", __func__, curr_cmd->cmd1);
1090 static void arasan_check_ondie(struct mtd_info *mtd)
1092 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1093 struct arasan_nand_info *nand = nand_get_controller_data(nand_chip);
1096 u8 set_feature[4] = {ENABLE_ONDIE_ECC, 0x00, 0x00, 0x00};
1099 /* Send the command for reading device ID */
1100 nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1101 nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0, -1);
1103 /* Read manufacturer and device IDs */
1104 maf_id = nand_chip->read_byte(mtd);
1105 dev_id = nand_chip->read_byte(mtd);
1107 if ((maf_id == NAND_MFR_MICRON) &&
1108 ((dev_id == 0xf1) || (dev_id == 0xa1) || (dev_id == 0xb1) ||
1109 (dev_id == 0xaa) || (dev_id == 0xba) || (dev_id == 0xda) ||
1110 (dev_id == 0xca) || (dev_id == 0xac) || (dev_id == 0xbc) ||
1111 (dev_id == 0xdc) || (dev_id == 0xcc) || (dev_id == 0xa3) ||
1112 (dev_id == 0xb3) || (dev_id == 0xd3) || (dev_id == 0xc3))) {
1113 nand_chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES,
1114 ONDIE_ECC_FEATURE_ADDR, -1);
1116 nand_chip->write_buf(mtd, &set_feature[0], 4);
1117 nand_chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES,
1118 ONDIE_ECC_FEATURE_ADDR, -1);
1120 for (i = 0; i < 4; i++)
1121 get_feature[i] = nand_chip->read_byte(mtd);
1123 if (get_feature[0] & ENABLE_ONDIE_ECC)
1124 nand->on_die_ecc_enabled = true;
1126 printf("%s: Unable to enable OnDie ECC\n", __func__);
1128 /* Use the BBT pattern descriptors */
1129 nand_chip->bbt_td = &bbt_main_descr;
1130 nand_chip->bbt_md = &bbt_mirror_descr;
1134 static int arasan_nand_ecc_init(struct mtd_info *mtd)
1137 u32 regval, eccpos_start, i, eccaddr;
1138 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1140 for (i = 0; i < ARRAY_SIZE(ecc_matrix); i++) {
1141 if ((ecc_matrix[i].pagesize == mtd->writesize) &&
1142 (ecc_matrix[i].ecc_codeword_size >=
1143 nand_chip->ecc_step_ds)) {
1144 if (ecc_matrix[i].eccbits >=
1145 nand_chip->ecc_strength_ds) {
1156 eccaddr = mtd->writesize + mtd->oobsize -
1157 ecc_matrix[found].eccsize;
1160 (ecc_matrix[found].eccsize << ARASAN_NAND_ECC_SIZE_SHIFT) |
1161 (ecc_matrix[found].bch << ARASAN_NAND_ECC_BCH_SHIFT);
1162 writel(regval, &arasan_nand_base->ecc_reg);
1164 if (ecc_matrix[found].bch) {
1165 regval = readl(&arasan_nand_base->memadr_reg2);
1166 regval &= ~ARASAN_NAND_MEM_ADDR2_BCH_MASK;
1167 regval |= (ecc_matrix[found].bchval <<
1168 ARASAN_NAND_MEM_ADDR2_BCH_SHIFT);
1169 writel(regval, &arasan_nand_base->memadr_reg2);
1172 nand_oob.eccbytes = ecc_matrix[found].eccsize;
1173 eccpos_start = mtd->oobsize - nand_oob.eccbytes;
1175 for (i = 0; i < nand_oob.eccbytes; i++)
1176 nand_oob.eccpos[i] = eccpos_start + i;
1178 nand_oob.oobfree[0].offset = 2;
1179 nand_oob.oobfree[0].length = eccpos_start - 2;
1181 nand_chip->ecc.size = ecc_matrix[found].ecc_codeword_size;
1182 nand_chip->ecc.strength = ecc_matrix[found].eccbits;
1183 nand_chip->ecc.bytes = ecc_matrix[found].eccsize;
1184 nand_chip->ecc.layout = &nand_oob;
1189 static int arasan_nand_init(struct nand_chip *nand_chip, int devnum)
1191 struct arasan_nand_info *nand;
1192 struct mtd_info *mtd;
1195 nand = calloc(1, sizeof(struct arasan_nand_info));
1197 printf("%s: failed to allocate\n", __func__);
1201 nand->nand_base = arasan_nand_base;
1202 mtd = nand_to_mtd(nand_chip);
1203 nand_set_controller_data(nand_chip, nand);
1205 /* Set the driver entry points for MTD */
1206 nand_chip->cmdfunc = arasan_nand_cmd_function;
1207 nand_chip->select_chip = arasan_nand_select_chip;
1208 nand_chip->read_byte = arasan_nand_read_byte;
1210 /* Buffer read/write routines */
1211 nand_chip->read_buf = arasan_nand_read_buf;
1212 nand_chip->write_buf = arasan_nand_write_buf;
1213 nand_chip->bbt_options = NAND_BBT_USE_FLASH;
1215 writel(0x0, &arasan_nand_base->cmd_reg);
1216 writel(0x0, &arasan_nand_base->pgm_reg);
1218 /* first scan to find the device and get the page size */
1219 if (nand_scan_ident(mtd, 1, NULL)) {
1220 printf("%s: nand_scan_ident failed\n", __func__);
1224 nand_chip->ecc.mode = NAND_ECC_HW;
1225 nand_chip->ecc.hwctl = NULL;
1226 nand_chip->ecc.read_page = arasan_nand_read_page_hwecc;
1227 nand_chip->ecc.write_page = arasan_nand_write_page_hwecc;
1228 nand_chip->ecc.read_oob = arasan_nand_read_oob;
1229 nand_chip->ecc.write_oob = arasan_nand_write_oob;
1231 arasan_check_ondie(mtd);
1234 * If on die supported, then give priority to on-die ecc and use
1235 * it instead of controller ecc.
1237 if (nand->on_die_ecc_enabled) {
1238 nand_chip->ecc.strength = 1;
1239 nand_chip->ecc.size = mtd->writesize;
1240 nand_chip->ecc.bytes = 0;
1241 nand_chip->ecc.layout = &ondie_nand_oob_64;
1243 if (arasan_nand_ecc_init(mtd)) {
1244 printf("%s: nand_ecc_init failed\n", __func__);
1249 if (nand_scan_tail(mtd)) {
1250 printf("%s: nand_scan_tail failed\n", __func__);
1254 if (nand_register(devnum, mtd)) {
1255 printf("Nand Register Fail\n");
1265 void board_nand_init(void)
1267 struct nand_chip *nand = &nand_chip[0];
1269 if (arasan_nand_init(nand, 0))
1270 puts("NAND init failed\n");