2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian@popies.net>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
8 * Add Programmable Multibit ECC support for various AT91 SoC
9 * (C) Copyright 2012 ATMEL, Hong Xu
11 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/gpio.h>
21 #include <linux/mtd/nand_ecc.h>
23 #ifdef CONFIG_ATMEL_NAND_HWECC
25 /* Register access macros */
26 #define ecc_readl(add, reg) \
27 readl(AT91_BASE_SYS + add + ATMEL_ECC_##reg)
28 #define ecc_writel(add, reg, value) \
29 writel((value), AT91_BASE_SYS + add + ATMEL_ECC_##reg)
31 #include "atmel_nand_ecc.h" /* Hardware ECC registers */
33 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
35 #ifdef CONFIG_SPL_BUILD
36 #undef CONFIG_SYS_NAND_ONFI_DETECTION
39 struct atmel_nand_host {
40 struct pmecc_regs __iomem *pmecc;
41 struct pmecc_errloc_regs __iomem *pmerrloc;
42 void __iomem *pmecc_rom_base;
45 u16 pmecc_sector_size;
46 u32 pmecc_index_table_offset;
48 int pmecc_bytes_per_sector;
49 int pmecc_sector_number;
50 int pmecc_degree; /* Degree of remainders */
51 int pmecc_cw_len; /* Length of codeword */
53 /* lookup table for alpha_to and index_of */
54 void __iomem *pmecc_alpha_to;
55 void __iomem *pmecc_index_of;
57 /* data for pmecc computation */
59 int16_t *pmecc_partial_syn;
61 int16_t *pmecc_lmu; /* polynomal order */
67 static struct atmel_nand_host pmecc_host;
68 static struct nand_ecclayout atmel_pmecc_oobinfo;
71 * Return number of ecc bytes per sector according to sector size and
72 * correction capability
74 * Following table shows what at91 PMECC supported:
75 * Correction Capability Sector_512_bytes Sector_1024_bytes
76 * ===================== ================ =================
77 * 2-bits 4-bytes 4-bytes
78 * 4-bits 7-bytes 7-bytes
79 * 8-bits 13-bytes 14-bytes
80 * 12-bits 20-bytes 21-bytes
81 * 24-bits 39-bytes 42-bytes
83 static int pmecc_get_ecc_bytes(int cap, int sector_size)
85 int m = 12 + sector_size / 512;
86 return (m * cap + 7) / 8;
89 static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
90 int oobsize, int ecc_len)
94 layout->eccbytes = ecc_len;
96 /* ECC will occupy the last ecc_len bytes continuously */
97 for (i = 0; i < ecc_len; i++)
98 layout->eccpos[i] = oobsize - ecc_len + i;
100 layout->oobfree[0].offset = 2;
101 layout->oobfree[0].length =
102 oobsize - ecc_len - layout->oobfree[0].offset;
105 static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
109 table_size = host->pmecc_sector_size == 512 ?
110 PMECC_INDEX_TABLE_SIZE_512 : PMECC_INDEX_TABLE_SIZE_1024;
112 /* the ALPHA lookup table is right behind the INDEX lookup table. */
113 return host->pmecc_rom_base + host->pmecc_index_table_offset +
114 table_size * sizeof(int16_t);
117 static void pmecc_data_free(struct atmel_nand_host *host)
119 free(host->pmecc_partial_syn);
120 free(host->pmecc_si);
121 free(host->pmecc_lmu);
122 free(host->pmecc_smu);
123 free(host->pmecc_mu);
124 free(host->pmecc_dmu);
125 free(host->pmecc_delta);
128 static int pmecc_data_alloc(struct atmel_nand_host *host)
130 const int cap = host->pmecc_corr_cap;
133 size = (2 * cap + 1) * sizeof(int16_t);
134 host->pmecc_partial_syn = malloc(size);
135 host->pmecc_si = malloc(size);
136 host->pmecc_lmu = malloc((cap + 1) * sizeof(int16_t));
137 host->pmecc_smu = malloc((cap + 2) * size);
139 size = (cap + 1) * sizeof(int);
140 host->pmecc_mu = malloc(size);
141 host->pmecc_dmu = malloc(size);
142 host->pmecc_delta = malloc(size);
144 if (host->pmecc_partial_syn &&
154 pmecc_data_free(host);
159 static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
161 struct nand_chip *nand_chip = mtd->priv;
162 struct atmel_nand_host *host = nand_chip->priv;
166 /* Fill odd syndromes */
167 for (i = 0; i < host->pmecc_corr_cap; i++) {
168 value = pmecc_readl(host->pmecc, rem_port[sector].rem[i / 2]);
172 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
176 static void pmecc_substitute(struct mtd_info *mtd)
178 struct nand_chip *nand_chip = mtd->priv;
179 struct atmel_nand_host *host = nand_chip->priv;
180 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
181 int16_t __iomem *index_of = host->pmecc_index_of;
182 int16_t *partial_syn = host->pmecc_partial_syn;
183 const int cap = host->pmecc_corr_cap;
187 /* si[] is a table that holds the current syndrome value,
188 * an element of that table belongs to the field
192 memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
194 /* Computation 2t syndromes based on S(x) */
196 for (i = 1; i < 2 * cap; i += 2) {
197 for (j = 0; j < host->pmecc_degree; j++) {
198 if (partial_syn[i] & (0x1 << j))
199 si[i] = readw(alpha_to + i * j) ^ si[i];
202 /* Even syndrome = (Odd syndrome) ** 2 */
203 for (i = 2, j = 1; j <= cap; i = ++j << 1) {
209 tmp = readw(index_of + si[j]);
210 tmp = (tmp * 2) % host->pmecc_cw_len;
211 si[i] = readw(alpha_to + tmp);
217 * This function defines a Berlekamp iterative procedure for
218 * finding the value of the error location polynomial.
219 * The input is si[], initialize by pmecc_substitute().
220 * The output is smu[][].
222 * This function is written according to chip datasheet Chapter:
223 * Find the Error Location Polynomial Sigma(x) of Section:
224 * Programmable Multibit ECC Control (PMECC).
226 static void pmecc_get_sigma(struct mtd_info *mtd)
228 struct nand_chip *nand_chip = mtd->priv;
229 struct atmel_nand_host *host = nand_chip->priv;
231 int16_t *lmu = host->pmecc_lmu;
232 int16_t *si = host->pmecc_si;
233 int *mu = host->pmecc_mu;
234 int *dmu = host->pmecc_dmu; /* Discrepancy */
235 int *delta = host->pmecc_delta; /* Delta order */
236 int cw_len = host->pmecc_cw_len;
237 const int16_t cap = host->pmecc_corr_cap;
238 const int num = 2 * cap + 1;
239 int16_t __iomem *index_of = host->pmecc_index_of;
240 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
242 uint32_t dmu_0_count, tmp;
243 int16_t *smu = host->pmecc_smu;
245 /* index of largest delta */
250 /* Init the Sigma(x) */
251 memset(smu, 0, sizeof(int16_t) * ARRAY_SIZE(smu));
262 /* discrepancy set to 1 */
264 /* polynom order set to 0 */
266 /* delta[0] = (mu[0] * 2 - lmu[0]) >> 1; */
273 /* Sigma(x) set to 1 */
276 /* discrepancy set to S1 */
279 /* polynom order set to 0 */
282 /* delta[1] = (mu[1] * 2 - lmu[1]) >> 1; */
285 for (i = 1; i <= cap; i++) {
287 /* Begin Computing Sigma (Mu+1) and L(mu) */
288 /* check if discrepancy is set to 0 */
292 tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
293 if ((cap - (lmu[i] >> 1) - 1) & 0x1)
298 if (dmu_0_count == tmp) {
299 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
300 smu[(cap + 1) * num + j] =
303 lmu[cap + 1] = lmu[i];
308 for (j = 0; j <= lmu[i] >> 1; j++)
309 smu[(i + 1) * num + j] = smu[i * num + j];
311 /* copy previous polynom order to the next */
316 /* find largest delta with dmu != 0 */
317 for (j = 0; j < i; j++) {
318 if ((dmu[j]) && (delta[j] > largest)) {
324 /* compute difference */
325 diff = (mu[i] - mu[ro]);
327 /* Compute degree of the new smu polynomial */
328 if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
331 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
333 /* Init smu[i+1] with 0 */
334 for (k = 0; k < num; k++)
335 smu[(i + 1) * num + k] = 0;
337 /* Compute smu[i+1] */
338 for (k = 0; k <= lmu[ro] >> 1; k++) {
341 if (!(smu[ro * num + k] && dmu[i]))
343 a = readw(index_of + dmu[i]);
344 b = readw(index_of + dmu[ro]);
345 c = readw(index_of + smu[ro * num + k]);
346 tmp = a + (cw_len - b) + c;
347 a = readw(alpha_to + tmp % cw_len);
348 smu[(i + 1) * num + (k + diff)] = a;
351 for (k = 0; k <= lmu[i] >> 1; k++)
352 smu[(i + 1) * num + k] ^= smu[i * num + k];
355 /* End Computing Sigma (Mu+1) and L(mu) */
356 /* In either case compute delta */
357 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
359 /* Do not compute discrepancy for the last iteration */
363 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
366 dmu[i + 1] = si[tmp + 3];
367 } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
370 smu[(i + 1) * num + k]);
371 b = si[2 * (i - 1) + 3 - k];
372 c = readw(index_of + b);
375 dmu[i + 1] = readw(alpha_to + tmp) ^
382 static int pmecc_err_location(struct mtd_info *mtd)
384 struct nand_chip *nand_chip = mtd->priv;
385 struct atmel_nand_host *host = nand_chip->priv;
386 const int cap = host->pmecc_corr_cap;
387 const int num = 2 * cap + 1;
388 int sector_size = host->pmecc_sector_size;
389 int err_nbr = 0; /* number of error */
390 int roots_nbr; /* number of roots */
393 int16_t *smu = host->pmecc_smu;
394 int timeout = PMECC_MAX_TIMEOUT_US;
396 pmecc_writel(host->pmerrloc, eldis, PMERRLOC_DISABLE);
398 for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
399 pmecc_writel(host->pmerrloc, sigma[i],
400 smu[(cap + 1) * num + i]);
404 val = PMERRLOC_ELCFG_NUM_ERRORS(err_nbr - 1);
405 if (sector_size == 1024)
406 val |= PMERRLOC_ELCFG_SECTOR_1024;
408 pmecc_writel(host->pmerrloc, elcfg, val);
409 pmecc_writel(host->pmerrloc, elen,
410 sector_size * 8 + host->pmecc_degree * cap);
413 if (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_CALC_DONE)
420 dev_err(host->dev, "atmel_nand : Timeout to calculate PMECC error location\n");
424 roots_nbr = (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_ERR_NUM_MASK)
426 /* Number of roots == degree of smu hence <= cap */
427 if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
430 /* Number of roots does not match the degree of smu
431 * unable to correct error */
435 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
436 int sector_num, int extra_bytes, int err_nbr)
438 struct nand_chip *nand_chip = mtd->priv;
439 struct atmel_nand_host *host = nand_chip->priv;
441 int byte_pos, bit_pos, sector_size, pos;
445 sector_size = host->pmecc_sector_size;
448 tmp = pmecc_readl(host->pmerrloc, el[i]) - 1;
452 if (byte_pos >= (sector_size + extra_bytes))
453 BUG(); /* should never happen */
455 if (byte_pos < sector_size) {
456 err_byte = *(buf + byte_pos);
457 *(buf + byte_pos) ^= (1 << bit_pos);
459 pos = sector_num * host->pmecc_sector_size + byte_pos;
460 dev_dbg(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
461 pos, bit_pos, err_byte, *(buf + byte_pos));
463 /* Bit flip in OOB area */
464 tmp = sector_num * host->pmecc_bytes_per_sector
465 + (byte_pos - sector_size);
467 ecc[tmp] ^= (1 << bit_pos);
469 pos = tmp + nand_chip->ecc.layout->eccpos[0];
470 dev_dbg(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
471 pos, bit_pos, err_byte, ecc[tmp]);
481 static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
484 struct nand_chip *nand_chip = mtd->priv;
485 struct atmel_nand_host *host = nand_chip->priv;
486 int i, err_nbr, eccbytes;
489 eccbytes = nand_chip->ecc.bytes;
490 for (i = 0; i < eccbytes; i++)
493 /* Erased page, return OK */
497 for (i = 0; i < host->pmecc_sector_number; i++) {
499 if (pmecc_stat & 0x1) {
500 buf_pos = buf + i * host->pmecc_sector_size;
502 pmecc_gen_syndrome(mtd, i);
503 pmecc_substitute(mtd);
504 pmecc_get_sigma(mtd);
506 err_nbr = pmecc_err_location(mtd);
508 dev_err(host->dev, "PMECC: Too many errors\n");
509 mtd->ecc_stats.failed++;
512 pmecc_correct_data(mtd, buf_pos, ecc, i,
513 host->pmecc_bytes_per_sector, err_nbr);
514 mtd->ecc_stats.corrected += err_nbr;
523 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
524 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
526 struct atmel_nand_host *host = chip->priv;
527 int eccsize = chip->ecc.size;
528 uint8_t *oob = chip->oob_poi;
529 uint32_t *eccpos = chip->ecc.layout->eccpos;
531 int timeout = PMECC_MAX_TIMEOUT_US;
533 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
534 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
535 pmecc_writel(host->pmecc, cfg, ((pmecc_readl(host->pmecc, cfg))
536 & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
538 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
539 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
541 chip->read_buf(mtd, buf, eccsize);
542 chip->read_buf(mtd, oob, mtd->oobsize);
545 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
552 dev_err(host->dev, "atmel_nand : Timeout to read PMECC page\n");
556 stat = pmecc_readl(host->pmecc, isr);
558 if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
564 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
565 struct nand_chip *chip, const uint8_t *buf,
568 struct atmel_nand_host *host = chip->priv;
569 uint32_t *eccpos = chip->ecc.layout->eccpos;
571 int timeout = PMECC_MAX_TIMEOUT_US;
573 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
574 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
576 pmecc_writel(host->pmecc, cfg, (pmecc_readl(host->pmecc, cfg) |
577 PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
579 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
580 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
582 chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
585 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
592 dev_err(host->dev, "atmel_nand : Timeout to read PMECC status, fail to write PMECC in oob\n");
596 for (i = 0; i < host->pmecc_sector_number; i++) {
597 for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
600 pos = i * host->pmecc_bytes_per_sector + j;
601 chip->oob_poi[eccpos[pos]] =
602 pmecc_readb(host->pmecc, ecc_port[i].ecc[j]);
605 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
610 static void atmel_pmecc_core_init(struct mtd_info *mtd)
612 struct nand_chip *nand_chip = mtd->priv;
613 struct atmel_nand_host *host = nand_chip->priv;
615 struct nand_ecclayout *ecc_layout;
617 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
618 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
620 switch (host->pmecc_corr_cap) {
622 val = PMECC_CFG_BCH_ERR2;
625 val = PMECC_CFG_BCH_ERR4;
628 val = PMECC_CFG_BCH_ERR8;
631 val = PMECC_CFG_BCH_ERR12;
634 val = PMECC_CFG_BCH_ERR24;
638 if (host->pmecc_sector_size == 512)
639 val |= PMECC_CFG_SECTOR512;
640 else if (host->pmecc_sector_size == 1024)
641 val |= PMECC_CFG_SECTOR1024;
643 switch (host->pmecc_sector_number) {
645 val |= PMECC_CFG_PAGE_1SECTOR;
648 val |= PMECC_CFG_PAGE_2SECTORS;
651 val |= PMECC_CFG_PAGE_4SECTORS;
654 val |= PMECC_CFG_PAGE_8SECTORS;
658 val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
659 | PMECC_CFG_AUTO_DISABLE);
660 pmecc_writel(host->pmecc, cfg, val);
662 ecc_layout = nand_chip->ecc.layout;
663 pmecc_writel(host->pmecc, sarea, mtd->oobsize - 1);
664 pmecc_writel(host->pmecc, saddr, ecc_layout->eccpos[0]);
665 pmecc_writel(host->pmecc, eaddr,
666 ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
667 /* See datasheet about PMECC Clock Control Register */
668 pmecc_writel(host->pmecc, clk, PMECC_CLK_133MHZ);
669 pmecc_writel(host->pmecc, idr, 0xff);
670 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
673 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
675 * get_onfi_ecc_param - Get ECC requirement from ONFI parameters
676 * @ecc_bits: store the ONFI ECC correct bits capbility
677 * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
679 * Returns -1 if ONFI parameters is not supported. In this case @ecc_bits,
680 * @sector_size are initialize to 0.
681 * Return 0 if success to get the ECC requirement.
683 static int get_onfi_ecc_param(struct nand_chip *chip,
684 int *ecc_bits, int *sector_size)
686 *ecc_bits = *sector_size = 0;
688 if (chip->onfi_params.ecc_bits == 0xff)
689 /* TODO: the sector_size and ecc_bits need to be find in
690 * extended ecc parameter, currently we don't support it.
694 *ecc_bits = chip->onfi_params.ecc_bits;
696 /* The default sector size (ecc codeword size) is 512 */
703 * pmecc_choose_ecc - Get ecc requirement from ONFI parameters. If
704 * pmecc_corr_cap or pmecc_sector_size is 0, then set it as
705 * ONFI ECC parameters.
706 * @host: point to an atmel_nand_host structure.
707 * if host->pmecc_corr_cap is 0 then set it as the ONFI ecc_bits.
708 * if host->pmecc_sector_size is 0 then set it as the ONFI sector_size.
709 * @chip: point to an nand_chip structure.
710 * @cap: store the ONFI ECC correct bits capbility
711 * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
713 * Return 0 if success. otherwise return the error code.
715 static int pmecc_choose_ecc(struct atmel_nand_host *host,
716 struct nand_chip *chip,
717 int *cap, int *sector_size)
719 /* Get ECC requirement from ONFI parameters */
720 *cap = *sector_size = 0;
721 if (chip->onfi_version) {
722 if (!get_onfi_ecc_param(chip, cap, sector_size)) {
723 MTDDEBUG(MTD_DEBUG_LEVEL1, "ONFI params, minimum required ECC: %d bits in %d bytes\n",
726 dev_info(host->dev, "NAND chip ECC reqirement is in Extended ONFI parameter, we don't support yet.\n");
729 dev_info(host->dev, "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes");
731 if (*cap == 0 && *sector_size == 0) {
732 /* Non-ONFI compliant or use extended ONFI parameters */
737 /* If head file doesn't specify then use the one in ONFI parameters */
738 if (host->pmecc_corr_cap == 0) {
739 /* use the most fitable ecc bits (the near bigger one ) */
741 host->pmecc_corr_cap = 2;
743 host->pmecc_corr_cap = 4;
745 host->pmecc_corr_cap = 8;
747 host->pmecc_corr_cap = 12;
749 host->pmecc_corr_cap = 24;
753 if (host->pmecc_sector_size == 0) {
754 /* use the most fitable sector size (the near smaller one ) */
755 if (*sector_size >= 1024)
756 host->pmecc_sector_size = 1024;
757 else if (*sector_size >= 512)
758 host->pmecc_sector_size = 512;
766 #if defined(NO_GALOIS_TABLE_IN_ROM)
767 static uint16_t *pmecc_galois_table;
768 static inline int deg(unsigned int poly)
770 /* polynomial degree is the most-significant bit index */
771 return fls(poly) - 1;
774 static int build_gf_tables(int mm, unsigned int poly,
775 int16_t *index_of, int16_t *alpha_to)
777 unsigned int i, x = 1;
778 const unsigned int k = 1 << deg(poly);
779 unsigned int nn = (1 << mm) - 1;
781 /* primitive polynomial must be of degree m */
785 for (i = 0; i < nn; i++) {
789 /* polynomial is not primitive (a^i=1 with 0<i<2^m-1) */
802 static uint16_t *create_lookup_table(int sector_size)
804 int degree = (sector_size == 512) ?
805 PMECC_GF_DIMENSION_13 :
806 PMECC_GF_DIMENSION_14;
807 unsigned int poly = (sector_size == 512) ?
808 PMECC_GF_13_PRIMITIVE_POLY :
809 PMECC_GF_14_PRIMITIVE_POLY;
810 int table_size = (sector_size == 512) ?
811 PMECC_INDEX_TABLE_SIZE_512 :
812 PMECC_INDEX_TABLE_SIZE_1024;
814 int16_t *addr = kzalloc(2 * table_size * sizeof(uint16_t), GFP_KERNEL);
815 if (addr && build_gf_tables(degree, poly, addr, addr + table_size))
818 return (uint16_t *)addr;
822 static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
823 struct mtd_info *mtd)
825 struct atmel_nand_host *host;
826 int cap, sector_size;
828 host = nand->priv = &pmecc_host;
830 nand->ecc.mode = NAND_ECC_HW;
831 nand->ecc.calculate = NULL;
832 nand->ecc.correct = NULL;
833 nand->ecc.hwctl = NULL;
835 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
836 host->pmecc_corr_cap = host->pmecc_sector_size = 0;
838 #ifdef CONFIG_PMECC_CAP
839 host->pmecc_corr_cap = CONFIG_PMECC_CAP;
841 #ifdef CONFIG_PMECC_SECTOR_SIZE
842 host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
844 /* Get ECC requirement of ONFI parameters. And if CONFIG_PMECC_CAP or
845 * CONFIG_PMECC_SECTOR_SIZE not defined, then use ecc_bits, sector_size
848 if (pmecc_choose_ecc(host, nand, &cap, §or_size)) {
849 dev_err(host->dev, "The NAND flash's ECC requirement(ecc_bits: %d, sector_size: %d) are not support!",
854 if (cap > host->pmecc_corr_cap)
855 dev_info(host->dev, "WARNING: Using different ecc correct bits(%d bit) from Nand ONFI ECC reqirement (%d bit).\n",
856 host->pmecc_corr_cap, cap);
857 if (sector_size < host->pmecc_sector_size)
858 dev_info(host->dev, "WARNING: Using different ecc correct sector size (%d bytes) from Nand ONFI ECC reqirement (%d bytes).\n",
859 host->pmecc_sector_size, sector_size);
860 #else /* CONFIG_SYS_NAND_ONFI_DETECTION */
861 host->pmecc_corr_cap = CONFIG_PMECC_CAP;
862 host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
865 cap = host->pmecc_corr_cap;
866 sector_size = host->pmecc_sector_size;
868 /* TODO: need check whether cap & sector_size is validate */
869 #if defined(NO_GALOIS_TABLE_IN_ROM)
871 * As pmecc_rom_base is the begin of the gallois field table, So the
872 * index offset just set as 0.
874 host->pmecc_index_table_offset = 0;
876 if (host->pmecc_sector_size == 512)
877 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_512;
879 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_1024;
882 MTDDEBUG(MTD_DEBUG_LEVEL1,
883 "Initialize PMECC params, cap: %d, sector: %d\n",
886 host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC;
887 host->pmerrloc = (struct pmecc_errloc_regs __iomem *)
889 #if defined(NO_GALOIS_TABLE_IN_ROM)
890 pmecc_galois_table = create_lookup_table(host->pmecc_sector_size);
891 if (!pmecc_galois_table) {
892 dev_err(host->dev, "out of memory\n");
896 host->pmecc_rom_base = (void __iomem *)pmecc_galois_table;
898 host->pmecc_rom_base = (void __iomem *) ATMEL_BASE_ROM;
901 /* ECC is calculated for the whole page (1 step) */
902 nand->ecc.size = mtd->writesize;
904 /* set ECC page size and oob layout */
905 switch (mtd->writesize) {
909 host->pmecc_degree = (sector_size == 512) ?
910 PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
911 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
912 host->pmecc_sector_number = mtd->writesize / sector_size;
913 host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
915 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
916 host->pmecc_index_of = host->pmecc_rom_base +
917 host->pmecc_index_table_offset;
920 nand->ecc.bytes = host->pmecc_bytes_per_sector *
921 host->pmecc_sector_number;
923 if (nand->ecc.bytes > MTD_MAX_ECCPOS_ENTRIES_LARGE) {
924 dev_err(host->dev, "too large eccpos entries. max support ecc.bytes is %d\n",
925 MTD_MAX_ECCPOS_ENTRIES_LARGE);
929 if (nand->ecc.bytes > mtd->oobsize - 2) {
930 dev_err(host->dev, "No room for ECC bytes\n");
933 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
936 nand->ecc.layout = &atmel_pmecc_oobinfo;
941 dev_err(host->dev, "Unsupported page size for PMECC, use Software ECC\n");
943 /* page size not handled by HW ECC */
944 /* switching back to soft ECC */
945 nand->ecc.mode = NAND_ECC_SOFT;
946 nand->ecc.read_page = NULL;
947 nand->ecc.postpad = 0;
948 nand->ecc.prepad = 0;
953 /* Allocate data for PMECC computation */
954 if (pmecc_data_alloc(host)) {
955 dev_err(host->dev, "Cannot allocate memory for PMECC computation!\n");
959 nand->options |= NAND_NO_SUBPAGE_WRITE;
960 nand->ecc.read_page = atmel_nand_pmecc_read_page;
961 nand->ecc.write_page = atmel_nand_pmecc_write_page;
962 nand->ecc.strength = cap;
964 atmel_pmecc_core_init(mtd);
971 /* oob layout for large page size
972 * bad block info is on bytes 0 and 1
973 * the bytes have to be consecutives to avoid
974 * several NAND_CMD_RNDOUT during read
976 static struct nand_ecclayout atmel_oobinfo_large = {
978 .eccpos = {60, 61, 62, 63},
984 /* oob layout for small page size
985 * bad block info is on bytes 4 and 5
986 * the bytes have to be consecutives to avoid
987 * several NAND_CMD_RNDOUT during read
989 static struct nand_ecclayout atmel_oobinfo_small = {
991 .eccpos = {0, 1, 2, 3},
1000 * function called after a write
1002 * mtd: MTD block structure
1003 * dat: raw data (unused)
1004 * ecc_code: buffer for ECC
1006 static int atmel_nand_calculate(struct mtd_info *mtd,
1007 const u_char *dat, unsigned char *ecc_code)
1009 unsigned int ecc_value;
1011 /* get the first 2 ECC bytes */
1012 ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR);
1014 ecc_code[0] = ecc_value & 0xFF;
1015 ecc_code[1] = (ecc_value >> 8) & 0xFF;
1017 /* get the last 2 ECC bytes */
1018 ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, NPR) & ATMEL_ECC_NPARITY;
1020 ecc_code[2] = ecc_value & 0xFF;
1021 ecc_code[3] = (ecc_value >> 8) & 0xFF;
1027 * HW ECC read page function
1029 * mtd: mtd info structure
1030 * chip: nand chip info structure
1031 * buf: buffer to store read data
1032 * oob_required: caller expects OOB data read to chip->oob_poi
1034 static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1035 uint8_t *buf, int oob_required, int page)
1037 int eccsize = chip->ecc.size;
1038 int eccbytes = chip->ecc.bytes;
1039 uint32_t *eccpos = chip->ecc.layout->eccpos;
1041 uint8_t *oob = chip->oob_poi;
1046 chip->read_buf(mtd, p, eccsize);
1048 /* move to ECC position if needed */
1049 if (eccpos[0] != 0) {
1050 /* This only works on large pages
1051 * because the ECC controller waits for
1052 * NAND_CMD_RNDOUTSTART after the
1054 * anyway, for small pages, the eccpos[0] == 0
1056 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1057 mtd->writesize + eccpos[0], -1);
1060 /* the ECC controller needs to read the ECC just after the data */
1061 ecc_pos = oob + eccpos[0];
1062 chip->read_buf(mtd, ecc_pos, eccbytes);
1064 /* check if there's an error */
1065 stat = chip->ecc.correct(mtd, p, oob, NULL);
1068 mtd->ecc_stats.failed++;
1070 mtd->ecc_stats.corrected += stat;
1072 /* get back to oob start (end of page) */
1073 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1076 chip->read_buf(mtd, oob, mtd->oobsize);
1084 * function called after a read
1086 * mtd: MTD block structure
1087 * dat: raw data read from the chip
1088 * read_ecc: ECC from the chip (unused)
1091 * Detect and correct a 1 bit error for a page
1093 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
1094 u_char *read_ecc, u_char *isnull)
1096 struct nand_chip *nand_chip = mtd->priv;
1097 unsigned int ecc_status;
1098 unsigned int ecc_word, ecc_bit;
1100 /* get the status from the Status Register */
1101 ecc_status = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, SR);
1103 /* if there's no error */
1104 if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
1107 /* get error bit offset (4 bits) */
1108 ecc_bit = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_BITADDR;
1109 /* get word address (12 bits) */
1110 ecc_word = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_WORDADDR;
1113 /* if there are multiple errors */
1114 if (ecc_status & ATMEL_ECC_MULERR) {
1115 /* check if it is a freshly erased block
1116 * (filled with 0xff) */
1117 if ((ecc_bit == ATMEL_ECC_BITADDR)
1118 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
1119 /* the block has just been erased, return OK */
1122 /* it doesn't seems to be a freshly
1124 * We can't correct so many errors */
1125 dev_warn(host->dev, "atmel_nand : multiple errors detected."
1126 " Unable to correct.\n");
1130 /* if there's a single bit error : we can correct it */
1131 if (ecc_status & ATMEL_ECC_ECCERR) {
1132 /* there's nothing much to do here.
1133 * the bit error is on the ECC itself.
1135 dev_warn(host->dev, "atmel_nand : one bit error on ECC code."
1136 " Nothing to correct\n");
1140 dev_warn(host->dev, "atmel_nand : one bit error on data."
1141 " (word offset in the page :"
1142 " 0x%x bit offset : 0x%x)\n",
1144 /* correct the error */
1145 if (nand_chip->options & NAND_BUSWIDTH_16) {
1147 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1150 dat[ecc_word] ^= (1 << ecc_bit);
1152 dev_warn(host->dev, "atmel_nand : error corrected\n");
1157 * Enable HW ECC : unused on most chips
1159 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1163 int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
1165 nand->ecc.mode = NAND_ECC_HW;
1166 nand->ecc.calculate = atmel_nand_calculate;
1167 nand->ecc.correct = atmel_nand_correct;
1168 nand->ecc.hwctl = atmel_nand_hwctl;
1169 nand->ecc.read_page = atmel_nand_read_page;
1170 nand->ecc.bytes = 4;
1172 if (nand->ecc.mode == NAND_ECC_HW) {
1173 /* ECC is calculated for the whole page (1 step) */
1174 nand->ecc.size = mtd->writesize;
1176 /* set ECC page size and oob layout */
1177 switch (mtd->writesize) {
1179 nand->ecc.layout = &atmel_oobinfo_small;
1180 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1181 ATMEL_ECC_PAGESIZE_528);
1184 nand->ecc.layout = &atmel_oobinfo_large;
1185 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1186 ATMEL_ECC_PAGESIZE_1056);
1189 nand->ecc.layout = &atmel_oobinfo_large;
1190 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1191 ATMEL_ECC_PAGESIZE_2112);
1194 nand->ecc.layout = &atmel_oobinfo_large;
1195 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1196 ATMEL_ECC_PAGESIZE_4224);
1199 /* page size not handled by HW ECC */
1200 /* switching back to soft ECC */
1201 nand->ecc.mode = NAND_ECC_SOFT;
1202 nand->ecc.calculate = NULL;
1203 nand->ecc.correct = NULL;
1204 nand->ecc.hwctl = NULL;
1205 nand->ecc.read_page = NULL;
1206 nand->ecc.postpad = 0;
1207 nand->ecc.prepad = 0;
1208 nand->ecc.bytes = 0;
1216 #endif /* CONFIG_ATMEL_NAND_HW_PMECC */
1218 #endif /* CONFIG_ATMEL_NAND_HWECC */
1220 static void at91_nand_hwcontrol(struct mtd_info *mtd,
1221 int cmd, unsigned int ctrl)
1223 struct nand_chip *this = mtd->priv;
1225 if (ctrl & NAND_CTRL_CHANGE) {
1226 ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
1227 IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
1228 | CONFIG_SYS_NAND_MASK_CLE);
1230 if (ctrl & NAND_CLE)
1231 IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
1232 if (ctrl & NAND_ALE)
1233 IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
1235 #ifdef CONFIG_SYS_NAND_ENABLE_PIN
1236 gpio_set_value(CONFIG_SYS_NAND_ENABLE_PIN, !(ctrl & NAND_NCE));
1238 this->IO_ADDR_W = (void *) IO_ADDR_W;
1241 if (cmd != NAND_CMD_NONE)
1242 writeb(cmd, this->IO_ADDR_W);
1245 #ifdef CONFIG_SYS_NAND_READY_PIN
1246 static int at91_nand_ready(struct mtd_info *mtd)
1248 return gpio_get_value(CONFIG_SYS_NAND_READY_PIN);
1252 #ifdef CONFIG_SPL_BUILD
1253 /* The following code is for SPL */
1254 static nand_info_t mtd;
1255 static struct nand_chip nand_chip;
1257 static int nand_command(int block, int page, uint32_t offs, u8 cmd)
1259 struct nand_chip *this = mtd.priv;
1260 int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
1261 void (*hwctrl)(struct mtd_info *mtd, int cmd,
1262 unsigned int ctrl) = this->cmd_ctrl;
1264 while (!this->dev_ready(&mtd))
1267 if (cmd == NAND_CMD_READOOB) {
1268 offs += CONFIG_SYS_NAND_PAGE_SIZE;
1269 cmd = NAND_CMD_READ0;
1272 hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1274 if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
1277 hwctrl(&mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1278 hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE);
1279 hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE);
1280 hwctrl(&mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE);
1281 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
1282 hwctrl(&mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE);
1284 hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
1286 hwctrl(&mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1287 hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
1289 while (!this->dev_ready(&mtd))
1295 static int nand_is_bad_block(int block)
1297 struct nand_chip *this = mtd.priv;
1299 nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
1301 if (this->options & NAND_BUSWIDTH_16) {
1302 if (readw(this->IO_ADDR_R) != 0xffff)
1305 if (readb(this->IO_ADDR_R) != 0xff)
1312 #ifdef CONFIG_SPL_NAND_ECC
1313 static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
1314 #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
1315 CONFIG_SYS_NAND_ECCSIZE)
1316 #define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
1318 static int nand_read_page(int block, int page, void *dst)
1320 struct nand_chip *this = mtd.priv;
1321 u_char ecc_calc[ECCTOTAL];
1322 u_char ecc_code[ECCTOTAL];
1323 u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
1324 int eccsize = CONFIG_SYS_NAND_ECCSIZE;
1325 int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
1326 int eccsteps = ECCSTEPS;
1329 nand_command(block, page, 0, NAND_CMD_READ0);
1331 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1332 if (this->ecc.mode != NAND_ECC_SOFT)
1333 this->ecc.hwctl(&mtd, NAND_ECC_READ);
1334 this->read_buf(&mtd, p, eccsize);
1335 this->ecc.calculate(&mtd, p, &ecc_calc[i]);
1337 this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
1339 for (i = 0; i < ECCTOTAL; i++)
1340 ecc_code[i] = oob_data[nand_ecc_pos[i]];
1342 eccsteps = ECCSTEPS;
1345 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1346 this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
1351 int spl_nand_erase_one(int block, int page)
1353 struct nand_chip *this = mtd.priv;
1354 void (*hwctrl)(struct mtd_info *mtd, int cmd,
1355 unsigned int ctrl) = this->cmd_ctrl;
1358 if (nand_chip.select_chip)
1359 nand_chip.select_chip(&mtd, 0);
1361 page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
1362 hwctrl(&mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1364 hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1365 hwctrl(&mtd, ((page_addr >> 8) & 0xff),
1366 NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1367 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
1368 /* One more address cycle for devices > 128MiB */
1369 hwctrl(&mtd, (page_addr >> 16) & 0x0f,
1370 NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1373 hwctrl(&mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1376 while (!this->dev_ready(&mtd))
1384 static int nand_read_page(int block, int page, void *dst)
1386 struct nand_chip *this = mtd.priv;
1388 nand_command(block, page, 0, NAND_CMD_READ0);
1389 atmel_nand_pmecc_read_page(&mtd, this, dst, 0, page);
1393 #endif /* CONFIG_SPL_NAND_ECC */
1395 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
1397 unsigned int block, lastblock;
1400 block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
1401 lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
1402 page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
1404 while (block <= lastblock) {
1405 if (!nand_is_bad_block(block)) {
1406 while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
1407 nand_read_page(block, page, dst);
1408 dst += CONFIG_SYS_NAND_PAGE_SIZE;
1423 int at91_nand_wait_ready(struct mtd_info *mtd)
1425 struct nand_chip *this = mtd->priv;
1427 udelay(this->chip_delay);
1432 int board_nand_init(struct nand_chip *nand)
1436 nand->ecc.mode = NAND_ECC_SOFT;
1437 #ifdef CONFIG_SYS_NAND_DBW_16
1438 nand->options = NAND_BUSWIDTH_16;
1439 nand->read_buf = nand_read_buf16;
1441 nand->read_buf = nand_read_buf;
1443 nand->cmd_ctrl = at91_nand_hwcontrol;
1444 #ifdef CONFIG_SYS_NAND_READY_PIN
1445 nand->dev_ready = at91_nand_ready;
1447 nand->dev_ready = at91_nand_wait_ready;
1449 nand->chip_delay = 20;
1451 #ifdef CONFIG_ATMEL_NAND_HWECC
1452 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1453 ret = atmel_pmecc_nand_init_params(nand, &mtd);
1460 void nand_init(void)
1462 mtd.writesize = CONFIG_SYS_NAND_PAGE_SIZE;
1463 mtd.oobsize = CONFIG_SYS_NAND_OOBSIZE;
1464 mtd.priv = &nand_chip;
1465 nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
1466 nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
1467 board_nand_init(&nand_chip);
1469 #ifdef CONFIG_SPL_NAND_ECC
1470 if (nand_chip.ecc.mode == NAND_ECC_SOFT) {
1471 nand_chip.ecc.calculate = nand_calculate_ecc;
1472 nand_chip.ecc.correct = nand_correct_data;
1476 if (nand_chip.select_chip)
1477 nand_chip.select_chip(&mtd, 0);
1480 void nand_deselect(void)
1482 if (nand_chip.select_chip)
1483 nand_chip.select_chip(&mtd, -1);
1488 #ifndef CONFIG_SYS_NAND_BASE_LIST
1489 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
1491 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
1492 static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
1494 int atmel_nand_chip_init(int devnum, ulong base_addr)
1497 struct mtd_info *mtd = &nand_info[devnum];
1498 struct nand_chip *nand = &nand_chip[devnum];
1501 nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr;
1503 #ifdef CONFIG_NAND_ECC_BCH
1504 nand->ecc.mode = NAND_ECC_SOFT_BCH;
1506 nand->ecc.mode = NAND_ECC_SOFT;
1508 #ifdef CONFIG_SYS_NAND_DBW_16
1509 nand->options = NAND_BUSWIDTH_16;
1511 nand->cmd_ctrl = at91_nand_hwcontrol;
1512 #ifdef CONFIG_SYS_NAND_READY_PIN
1513 nand->dev_ready = at91_nand_ready;
1515 nand->chip_delay = 75;
1517 ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
1521 #ifdef CONFIG_ATMEL_NAND_HWECC
1522 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1523 ret = atmel_pmecc_nand_init_params(nand, mtd);
1525 ret = atmel_hwecc_nand_init_param(nand, mtd);
1531 ret = nand_scan_tail(mtd);
1533 nand_register(devnum);
1538 void board_nand_init(void)
1541 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
1542 if (atmel_nand_chip_init(i, base_addr[i]))
1543 dev_err(host->dev, "atmel_nand: Fail to initialize #%d chip",
1546 #endif /* CONFIG_SPL_BUILD */