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1 /*
2  * (C) Copyright 2007-2008
3  * Stelian Pop <stelian@popies.net>
4  * Lead Tech Design <www.leadtechdesign.com>
5  *
6  * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
7  *
8  * Add Programmable Multibit ECC support for various AT91 SoC
9  *     (C) Copyright 2012 ATMEL, Hong Xu
10  *
11  * See file CREDITS for list of people who contributed to this
12  * project.
13  *
14  * This program is free software; you can redistribute it and/or
15  * modify it under the terms of the GNU General Public License as
16  * published by the Free Software Foundation; either version 2 of
17  * the License, or (at your option) any later version.
18  *
19  * This program is distributed in the hope that it will be useful,
20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22  * GNU General Public License for more details.
23  *
24  * You should have received a copy of the GNU General Public License
25  * along with this program; if not, write to the Free Software
26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27  * MA 02111-1307 USA
28  */
29
30 #include <common.h>
31 #include <asm/arch/hardware.h>
32 #include <asm/arch/gpio.h>
33 #include <asm/arch/at91_pio.h>
34
35 #include <nand.h>
36 #include <watchdog.h>
37
38 #ifdef CONFIG_ATMEL_NAND_HWECC
39
40 /* Register access macros */
41 #define ecc_readl(add, reg)                             \
42         readl(AT91_BASE_SYS + add + ATMEL_ECC_##reg)
43 #define ecc_writel(add, reg, value)                     \
44         writel((value), AT91_BASE_SYS + add + ATMEL_ECC_##reg)
45
46 #include "atmel_nand_ecc.h"     /* Hardware ECC registers */
47
48 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
49
50 struct atmel_nand_host {
51         struct pmecc_regs __iomem *pmecc;
52         struct pmecc_errloc_regs __iomem *pmerrloc;
53         void __iomem            *pmecc_rom_base;
54
55         u8              pmecc_corr_cap;
56         u16             pmecc_sector_size;
57         u32             pmecc_index_table_offset;
58
59         int             pmecc_bytes_per_sector;
60         int             pmecc_sector_number;
61         int             pmecc_degree;   /* Degree of remainders */
62         int             pmecc_cw_len;   /* Length of codeword */
63
64         /* lookup table for alpha_to and index_of */
65         void __iomem    *pmecc_alpha_to;
66         void __iomem    *pmecc_index_of;
67
68         /* data for pmecc computation */
69         int16_t pmecc_smu[(CONFIG_PMECC_CAP + 2) * (2 * CONFIG_PMECC_CAP + 1)];
70         int16_t pmecc_partial_syn[2 * CONFIG_PMECC_CAP + 1];
71         int16_t pmecc_si[2 * CONFIG_PMECC_CAP + 1];
72         int16_t pmecc_lmu[CONFIG_PMECC_CAP + 1]; /* polynomal order */
73         int     pmecc_mu[CONFIG_PMECC_CAP + 1];
74         int     pmecc_dmu[CONFIG_PMECC_CAP + 1];
75         int     pmecc_delta[CONFIG_PMECC_CAP + 1];
76 };
77
78 static struct atmel_nand_host pmecc_host;
79 static struct nand_ecclayout atmel_pmecc_oobinfo;
80
81 /*
82  * Return number of ecc bytes per sector according to sector size and
83  * correction capability
84  *
85  * Following table shows what at91 PMECC supported:
86  * Correction Capability        Sector_512_bytes        Sector_1024_bytes
87  * =====================        ================        =================
88  *                2-bits                 4-bytes                  4-bytes
89  *                4-bits                 7-bytes                  7-bytes
90  *                8-bits                13-bytes                 14-bytes
91  *               12-bits                20-bytes                 21-bytes
92  *               24-bits                39-bytes                 42-bytes
93  */
94 static int pmecc_get_ecc_bytes(int cap, int sector_size)
95 {
96         int m = 12 + sector_size / 512;
97         return (m * cap + 7) / 8;
98 }
99
100 static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
101         int oobsize, int ecc_len)
102 {
103         int i;
104
105         layout->eccbytes = ecc_len;
106
107         /* ECC will occupy the last ecc_len bytes continuously */
108         for (i = 0; i < ecc_len; i++)
109                 layout->eccpos[i] = oobsize - ecc_len + i;
110
111         layout->oobfree[0].offset = 2;
112         layout->oobfree[0].length =
113                 oobsize - ecc_len - layout->oobfree[0].offset;
114 }
115
116 static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
117 {
118         int table_size;
119
120         table_size = host->pmecc_sector_size == 512 ?
121                 PMECC_INDEX_TABLE_SIZE_512 : PMECC_INDEX_TABLE_SIZE_1024;
122
123         /* the ALPHA lookup table is right behind the INDEX lookup table. */
124         return host->pmecc_rom_base + host->pmecc_index_table_offset +
125                         table_size * sizeof(int16_t);
126 }
127
128 static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
129 {
130         struct nand_chip *nand_chip = mtd->priv;
131         struct atmel_nand_host *host = nand_chip->priv;
132         int i;
133         uint32_t value;
134
135         /* Fill odd syndromes */
136         for (i = 0; i < host->pmecc_corr_cap; i++) {
137                 value = readl(&host->pmecc->rem_port[sector].rem[i / 2]);
138                 if (i & 1)
139                         value >>= 16;
140                 value &= 0xffff;
141                 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
142         }
143 }
144
145 static void pmecc_substitute(struct mtd_info *mtd)
146 {
147         struct nand_chip *nand_chip = mtd->priv;
148         struct atmel_nand_host *host = nand_chip->priv;
149         int16_t __iomem *alpha_to = host->pmecc_alpha_to;
150         int16_t __iomem *index_of = host->pmecc_index_of;
151         int16_t *partial_syn = host->pmecc_partial_syn;
152         const int cap = host->pmecc_corr_cap;
153         int16_t *si;
154         int i, j;
155
156         /* si[] is a table that holds the current syndrome value,
157          * an element of that table belongs to the field
158          */
159         si = host->pmecc_si;
160
161         memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
162
163         /* Computation 2t syndromes based on S(x) */
164         /* Odd syndromes */
165         for (i = 1; i < 2 * cap; i += 2) {
166                 for (j = 0; j < host->pmecc_degree; j++) {
167                         if (partial_syn[i] & (0x1 << j))
168                                 si[i] = readw(alpha_to + i * j) ^ si[i];
169                 }
170         }
171         /* Even syndrome = (Odd syndrome) ** 2 */
172         for (i = 2, j = 1; j <= cap; i = ++j << 1) {
173                 if (si[j] == 0) {
174                         si[i] = 0;
175                 } else {
176                         int16_t tmp;
177
178                         tmp = readw(index_of + si[j]);
179                         tmp = (tmp * 2) % host->pmecc_cw_len;
180                         si[i] = readw(alpha_to + tmp);
181                 }
182         }
183 }
184
185 /*
186  * This function defines a Berlekamp iterative procedure for
187  * finding the value of the error location polynomial.
188  * The input is si[], initialize by pmecc_substitute().
189  * The output is smu[][].
190  *
191  * This function is written according to chip datasheet Chapter:
192  * Find the Error Location Polynomial Sigma(x) of Section:
193  * Programmable Multibit ECC Control (PMECC).
194  */
195 static void pmecc_get_sigma(struct mtd_info *mtd)
196 {
197         struct nand_chip *nand_chip = mtd->priv;
198         struct atmel_nand_host *host = nand_chip->priv;
199
200         int16_t *lmu = host->pmecc_lmu;
201         int16_t *si = host->pmecc_si;
202         int *mu = host->pmecc_mu;
203         int *dmu = host->pmecc_dmu;     /* Discrepancy */
204         int *delta = host->pmecc_delta; /* Delta order */
205         int cw_len = host->pmecc_cw_len;
206         const int16_t cap = host->pmecc_corr_cap;
207         const int num = 2 * cap + 1;
208         int16_t __iomem *index_of = host->pmecc_index_of;
209         int16_t __iomem *alpha_to = host->pmecc_alpha_to;
210         int i, j, k;
211         uint32_t dmu_0_count, tmp;
212         int16_t *smu = host->pmecc_smu;
213
214         /* index of largest delta */
215         int ro;
216         int largest;
217         int diff;
218
219         /* Init the Sigma(x) */
220         memset(smu, 0, sizeof(int16_t) * ARRAY_SIZE(smu));
221
222         dmu_0_count = 0;
223
224         /* First Row */
225
226         /* Mu */
227         mu[0] = -1;
228
229         smu[0] = 1;
230
231         /* discrepancy set to 1 */
232         dmu[0] = 1;
233         /* polynom order set to 0 */
234         lmu[0] = 0;
235         /* delta[0] = (mu[0] * 2 - lmu[0]) >> 1; */
236         delta[0] = -1;
237
238         /* Second Row */
239
240         /* Mu */
241         mu[1] = 0;
242         /* Sigma(x) set to 1 */
243         smu[num] = 1;
244
245         /* discrepancy set to S1 */
246         dmu[1] = si[1];
247
248         /* polynom order set to 0 */
249         lmu[1] = 0;
250
251         /* delta[1] = (mu[1] * 2 - lmu[1]) >> 1; */
252         delta[1] = 0;
253
254         for (i = 1; i <= cap; i++) {
255                 mu[i + 1] = i << 1;
256                 /* Begin Computing Sigma (Mu+1) and L(mu) */
257                 /* check if discrepancy is set to 0 */
258                 if (dmu[i] == 0) {
259                         dmu_0_count++;
260
261                         tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
262                         if ((cap - (lmu[i] >> 1) - 1) & 0x1)
263                                 tmp += 2;
264                         else
265                                 tmp += 1;
266
267                         if (dmu_0_count == tmp) {
268                                 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
269                                         smu[(cap + 1) * num + j] =
270                                                         smu[i * num + j];
271
272                                 lmu[cap + 1] = lmu[i];
273                                 return;
274                         }
275
276                         /* copy polynom */
277                         for (j = 0; j <= lmu[i] >> 1; j++)
278                                 smu[(i + 1) * num + j] = smu[i * num + j];
279
280                         /* copy previous polynom order to the next */
281                         lmu[i + 1] = lmu[i];
282                 } else {
283                         ro = 0;
284                         largest = -1;
285                         /* find largest delta with dmu != 0 */
286                         for (j = 0; j < i; j++) {
287                                 if ((dmu[j]) && (delta[j] > largest)) {
288                                         largest = delta[j];
289                                         ro = j;
290                                 }
291                         }
292
293                         /* compute difference */
294                         diff = (mu[i] - mu[ro]);
295
296                         /* Compute degree of the new smu polynomial */
297                         if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
298                                 lmu[i + 1] = lmu[i];
299                         else
300                                 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
301
302                         /* Init smu[i+1] with 0 */
303                         for (k = 0; k < num; k++)
304                                 smu[(i + 1) * num + k] = 0;
305
306                         /* Compute smu[i+1] */
307                         for (k = 0; k <= lmu[ro] >> 1; k++) {
308                                 int16_t a, b, c;
309
310                                 if (!(smu[ro * num + k] && dmu[i]))
311                                         continue;
312                                 a = readw(index_of + dmu[i]);
313                                 b = readw(index_of + dmu[ro]);
314                                 c = readw(index_of + smu[ro * num + k]);
315                                 tmp = a + (cw_len - b) + c;
316                                 a = readw(alpha_to + tmp % cw_len);
317                                 smu[(i + 1) * num + (k + diff)] = a;
318                         }
319
320                         for (k = 0; k <= lmu[i] >> 1; k++)
321                                 smu[(i + 1) * num + k] ^= smu[i * num + k];
322                 }
323
324                 /* End Computing Sigma (Mu+1) and L(mu) */
325                 /* In either case compute delta */
326                 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
327
328                 /* Do not compute discrepancy for the last iteration */
329                 if (i >= cap)
330                         continue;
331
332                 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
333                         tmp = 2 * (i - 1);
334                         if (k == 0) {
335                                 dmu[i + 1] = si[tmp + 3];
336                         } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
337                                 int16_t a, b, c;
338                                 a = readw(index_of +
339                                                 smu[(i + 1) * num + k]);
340                                 b = si[2 * (i - 1) + 3 - k];
341                                 c = readw(index_of + b);
342                                 tmp = a + c;
343                                 tmp %= cw_len;
344                                 dmu[i + 1] = readw(alpha_to + tmp) ^
345                                         dmu[i + 1];
346                         }
347                 }
348         }
349 }
350
351 static int pmecc_err_location(struct mtd_info *mtd)
352 {
353         struct nand_chip *nand_chip = mtd->priv;
354         struct atmel_nand_host *host = nand_chip->priv;
355         const int cap = host->pmecc_corr_cap;
356         const int num = 2 * cap + 1;
357         int sector_size = host->pmecc_sector_size;
358         int err_nbr = 0;        /* number of error */
359         int roots_nbr;          /* number of roots */
360         int i;
361         uint32_t val;
362         int16_t *smu = host->pmecc_smu;
363         int timeout = PMECC_MAX_TIMEOUT_US;
364
365         writel(PMERRLOC_DISABLE, &host->pmerrloc->eldis);
366
367         for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
368                 writel(smu[(cap + 1) * num + i], &host->pmerrloc->sigma[i]);
369                 err_nbr++;
370         }
371
372         val = PMERRLOC_ELCFG_NUM_ERRORS(err_nbr - 1);
373         if (sector_size == 1024)
374                 val |= PMERRLOC_ELCFG_SECTOR_1024;
375
376         writel(val, &host->pmerrloc->elcfg);
377         writel(sector_size * 8 + host->pmecc_degree * cap,
378                         &host->pmerrloc->elen);
379
380         while (--timeout) {
381                 if (readl(&host->pmerrloc->elisr) & PMERRLOC_CALC_DONE)
382                         break;
383                 WATCHDOG_RESET();
384                 udelay(1);
385         }
386
387         if (!timeout) {
388                 printk(KERN_ERR "atmel_nand : Timeout to calculate PMECC error location\n");
389                 return -1;
390         }
391
392         roots_nbr = (readl(&host->pmerrloc->elisr) & PMERRLOC_ERR_NUM_MASK)
393                         >> 8;
394         /* Number of roots == degree of smu hence <= cap */
395         if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
396                 return err_nbr - 1;
397
398         /* Number of roots does not match the degree of smu
399          * unable to correct error */
400         return -1;
401 }
402
403 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
404                 int sector_num, int extra_bytes, int err_nbr)
405 {
406         struct nand_chip *nand_chip = mtd->priv;
407         struct atmel_nand_host *host = nand_chip->priv;
408         int i = 0;
409         int byte_pos, bit_pos, sector_size, pos;
410         uint32_t tmp;
411         uint8_t err_byte;
412
413         sector_size = host->pmecc_sector_size;
414
415         while (err_nbr) {
416                 tmp = readl(&host->pmerrloc->el[i]) - 1;
417                 byte_pos = tmp / 8;
418                 bit_pos  = tmp % 8;
419
420                 if (byte_pos >= (sector_size + extra_bytes))
421                         BUG();  /* should never happen */
422
423                 if (byte_pos < sector_size) {
424                         err_byte = *(buf + byte_pos);
425                         *(buf + byte_pos) ^= (1 << bit_pos);
426
427                         pos = sector_num * host->pmecc_sector_size + byte_pos;
428                         printk(KERN_INFO "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
429                                 pos, bit_pos, err_byte, *(buf + byte_pos));
430                 } else {
431                         /* Bit flip in OOB area */
432                         tmp = sector_num * host->pmecc_bytes_per_sector
433                                         + (byte_pos - sector_size);
434                         err_byte = ecc[tmp];
435                         ecc[tmp] ^= (1 << bit_pos);
436
437                         pos = tmp + nand_chip->ecc.layout->eccpos[0];
438                         printk(KERN_INFO "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
439                                 pos, bit_pos, err_byte, ecc[tmp]);
440                 }
441
442                 i++;
443                 err_nbr--;
444         }
445
446         return;
447 }
448
449 static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
450         u8 *ecc)
451 {
452         struct nand_chip *nand_chip = mtd->priv;
453         struct atmel_nand_host *host = nand_chip->priv;
454         int i, err_nbr, eccbytes;
455         uint8_t *buf_pos;
456
457         eccbytes = nand_chip->ecc.bytes;
458         for (i = 0; i < eccbytes; i++)
459                 if (ecc[i] != 0xff)
460                         goto normal_check;
461         /* Erased page, return OK */
462         return 0;
463
464 normal_check:
465         for (i = 0; i < host->pmecc_sector_number; i++) {
466                 err_nbr = 0;
467                 if (pmecc_stat & 0x1) {
468                         buf_pos = buf + i * host->pmecc_sector_size;
469
470                         pmecc_gen_syndrome(mtd, i);
471                         pmecc_substitute(mtd);
472                         pmecc_get_sigma(mtd);
473
474                         err_nbr = pmecc_err_location(mtd);
475                         if (err_nbr == -1) {
476                                 printk(KERN_ERR "PMECC: Too many errors\n");
477                                 mtd->ecc_stats.failed++;
478                                 return -EIO;
479                         } else {
480                                 pmecc_correct_data(mtd, buf_pos, ecc, i,
481                                         host->pmecc_bytes_per_sector, err_nbr);
482                                 mtd->ecc_stats.corrected += err_nbr;
483                         }
484                 }
485                 pmecc_stat >>= 1;
486         }
487
488         return 0;
489 }
490
491 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
492         struct nand_chip *chip, uint8_t *buf, int page)
493 {
494         struct atmel_nand_host *host = chip->priv;
495         int eccsize = chip->ecc.size;
496         uint8_t *oob = chip->oob_poi;
497         uint32_t *eccpos = chip->ecc.layout->eccpos;
498         uint32_t stat;
499         int timeout = PMECC_MAX_TIMEOUT_US;
500
501         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
502         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
503         pmecc_writel(host->pmecc, cfg, ((pmecc_readl(host->pmecc, cfg))
504                 & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
505
506         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
507         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
508
509         chip->read_buf(mtd, buf, eccsize);
510         chip->read_buf(mtd, oob, mtd->oobsize);
511
512         while (--timeout) {
513                 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
514                         break;
515                 WATCHDOG_RESET();
516                 udelay(1);
517         }
518
519         if (!timeout) {
520                 printk(KERN_ERR "atmel_nand : Timeout to read PMECC page\n");
521                 return -1;
522         }
523
524         stat = pmecc_readl(host->pmecc, isr);
525         if (stat != 0)
526                 if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
527                         return -EIO;
528
529         return 0;
530 }
531
532 static void atmel_nand_pmecc_write_page(struct mtd_info *mtd,
533                 struct nand_chip *chip, const uint8_t *buf)
534 {
535         struct atmel_nand_host *host = chip->priv;
536         uint32_t *eccpos = chip->ecc.layout->eccpos;
537         int i, j;
538         int timeout = PMECC_MAX_TIMEOUT_US;
539
540         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
541         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
542
543         pmecc_writel(host->pmecc, cfg, (pmecc_readl(host->pmecc, cfg) |
544                 PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
545
546         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
547         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
548
549         chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
550
551         while (--timeout) {
552                 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
553                         break;
554                 WATCHDOG_RESET();
555                 udelay(1);
556         }
557
558         if (!timeout) {
559                 printk(KERN_ERR "atmel_nand : Timeout to read PMECC status, fail to write PMECC in oob\n");
560                 return;
561         }
562
563         for (i = 0; i < host->pmecc_sector_number; i++) {
564                 for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
565                         int pos;
566
567                         pos = i * host->pmecc_bytes_per_sector + j;
568                         chip->oob_poi[eccpos[pos]] =
569                                 readb(&host->pmecc->ecc_port[i].ecc[j]);
570                 }
571         }
572         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
573 }
574
575 static void atmel_pmecc_core_init(struct mtd_info *mtd)
576 {
577         struct nand_chip *nand_chip = mtd->priv;
578         struct atmel_nand_host *host = nand_chip->priv;
579         uint32_t val = 0;
580         struct nand_ecclayout *ecc_layout;
581
582         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
583         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
584
585         switch (host->pmecc_corr_cap) {
586         case 2:
587                 val = PMECC_CFG_BCH_ERR2;
588                 break;
589         case 4:
590                 val = PMECC_CFG_BCH_ERR4;
591                 break;
592         case 8:
593                 val = PMECC_CFG_BCH_ERR8;
594                 break;
595         case 12:
596                 val = PMECC_CFG_BCH_ERR12;
597                 break;
598         case 24:
599                 val = PMECC_CFG_BCH_ERR24;
600                 break;
601         }
602
603         if (host->pmecc_sector_size == 512)
604                 val |= PMECC_CFG_SECTOR512;
605         else if (host->pmecc_sector_size == 1024)
606                 val |= PMECC_CFG_SECTOR1024;
607
608         switch (host->pmecc_sector_number) {
609         case 1:
610                 val |= PMECC_CFG_PAGE_1SECTOR;
611                 break;
612         case 2:
613                 val |= PMECC_CFG_PAGE_2SECTORS;
614                 break;
615         case 4:
616                 val |= PMECC_CFG_PAGE_4SECTORS;
617                 break;
618         case 8:
619                 val |= PMECC_CFG_PAGE_8SECTORS;
620                 break;
621         }
622
623         val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
624                 | PMECC_CFG_AUTO_DISABLE);
625         pmecc_writel(host->pmecc, cfg, val);
626
627         ecc_layout = nand_chip->ecc.layout;
628         pmecc_writel(host->pmecc, sarea, mtd->oobsize - 1);
629         pmecc_writel(host->pmecc, saddr, ecc_layout->eccpos[0]);
630         pmecc_writel(host->pmecc, eaddr,
631                         ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
632         /* See datasheet about PMECC Clock Control Register */
633         pmecc_writel(host->pmecc, clk, PMECC_CLK_133MHZ);
634         pmecc_writel(host->pmecc, idr, 0xff);
635         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
636 }
637
638 static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
639                 struct mtd_info *mtd)
640 {
641         struct atmel_nand_host *host;
642         int cap, sector_size;
643
644         host = nand->priv = &pmecc_host;
645
646         nand->ecc.mode = NAND_ECC_HW;
647         nand->ecc.calculate = NULL;
648         nand->ecc.correct = NULL;
649         nand->ecc.hwctl = NULL;
650
651         cap = host->pmecc_corr_cap = CONFIG_PMECC_CAP;
652         sector_size = host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
653         host->pmecc_index_table_offset = CONFIG_PMECC_INDEX_TABLE_OFFSET;
654
655         MTDDEBUG(MTD_DEBUG_LEVEL1,
656                 "Initialize PMECC params, cap: %d, sector: %d\n",
657                 cap, sector_size);
658
659         host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC;
660         host->pmerrloc = (struct pmecc_errloc_regs __iomem *)
661                         ATMEL_BASE_PMERRLOC;
662         host->pmecc_rom_base = (void __iomem *) ATMEL_BASE_ROM;
663
664         /* ECC is calculated for the whole page (1 step) */
665         nand->ecc.size = mtd->writesize;
666
667         /* set ECC page size and oob layout */
668         switch (mtd->writesize) {
669         case 2048:
670         case 4096:
671                 host->pmecc_degree = PMECC_GF_DIMENSION_13;
672                 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
673                 host->pmecc_sector_number = mtd->writesize / sector_size;
674                 host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
675                         cap, sector_size);
676                 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
677                 host->pmecc_index_of = host->pmecc_rom_base +
678                         host->pmecc_index_table_offset;
679
680                 nand->ecc.steps = 1;
681                 nand->ecc.bytes = host->pmecc_bytes_per_sector *
682                                        host->pmecc_sector_number;
683                 if (nand->ecc.bytes > mtd->oobsize - 2) {
684                         printk(KERN_ERR "No room for ECC bytes\n");
685                         return -EINVAL;
686                 }
687                 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
688                                         mtd->oobsize,
689                                         nand->ecc.bytes);
690                 nand->ecc.layout = &atmel_pmecc_oobinfo;
691                 break;
692         case 512:
693         case 1024:
694                 /* TODO */
695                 printk(KERN_ERR "Unsupported page size for PMECC, use Software ECC\n");
696         default:
697                 /* page size not handled by HW ECC */
698                 /* switching back to soft ECC */
699                 nand->ecc.mode = NAND_ECC_SOFT;
700                 nand->ecc.read_page = NULL;
701                 nand->ecc.postpad = 0;
702                 nand->ecc.prepad = 0;
703                 nand->ecc.bytes = 0;
704                 return 0;
705         }
706
707         nand->ecc.read_page = atmel_nand_pmecc_read_page;
708         nand->ecc.write_page = atmel_nand_pmecc_write_page;
709
710         atmel_pmecc_core_init(mtd);
711
712         return 0;
713 }
714
715 #else
716
717 /* oob layout for large page size
718  * bad block info is on bytes 0 and 1
719  * the bytes have to be consecutives to avoid
720  * several NAND_CMD_RNDOUT during read
721  */
722 static struct nand_ecclayout atmel_oobinfo_large = {
723         .eccbytes = 4,
724         .eccpos = {60, 61, 62, 63},
725         .oobfree = {
726                 {2, 58}
727         },
728 };
729
730 /* oob layout for small page size
731  * bad block info is on bytes 4 and 5
732  * the bytes have to be consecutives to avoid
733  * several NAND_CMD_RNDOUT during read
734  */
735 static struct nand_ecclayout atmel_oobinfo_small = {
736         .eccbytes = 4,
737         .eccpos = {0, 1, 2, 3},
738         .oobfree = {
739                 {6, 10}
740         },
741 };
742
743 /*
744  * Calculate HW ECC
745  *
746  * function called after a write
747  *
748  * mtd:        MTD block structure
749  * dat:        raw data (unused)
750  * ecc_code:   buffer for ECC
751  */
752 static int atmel_nand_calculate(struct mtd_info *mtd,
753                 const u_char *dat, unsigned char *ecc_code)
754 {
755         unsigned int ecc_value;
756
757         /* get the first 2 ECC bytes */
758         ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR);
759
760         ecc_code[0] = ecc_value & 0xFF;
761         ecc_code[1] = (ecc_value >> 8) & 0xFF;
762
763         /* get the last 2 ECC bytes */
764         ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, NPR) & ATMEL_ECC_NPARITY;
765
766         ecc_code[2] = ecc_value & 0xFF;
767         ecc_code[3] = (ecc_value >> 8) & 0xFF;
768
769         return 0;
770 }
771
772 /*
773  * HW ECC read page function
774  *
775  * mtd:        mtd info structure
776  * chip:       nand chip info structure
777  * buf:        buffer to store read data
778  */
779 static int atmel_nand_read_page(struct mtd_info *mtd,
780                 struct nand_chip *chip, uint8_t *buf, int page)
781 {
782         int eccsize = chip->ecc.size;
783         int eccbytes = chip->ecc.bytes;
784         uint32_t *eccpos = chip->ecc.layout->eccpos;
785         uint8_t *p = buf;
786         uint8_t *oob = chip->oob_poi;
787         uint8_t *ecc_pos;
788         int stat;
789
790         /* read the page */
791         chip->read_buf(mtd, p, eccsize);
792
793         /* move to ECC position if needed */
794         if (eccpos[0] != 0) {
795                 /* This only works on large pages
796                  * because the ECC controller waits for
797                  * NAND_CMD_RNDOUTSTART after the
798                  * NAND_CMD_RNDOUT.
799                  * anyway, for small pages, the eccpos[0] == 0
800                  */
801                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
802                                 mtd->writesize + eccpos[0], -1);
803         }
804
805         /* the ECC controller needs to read the ECC just after the data */
806         ecc_pos = oob + eccpos[0];
807         chip->read_buf(mtd, ecc_pos, eccbytes);
808
809         /* check if there's an error */
810         stat = chip->ecc.correct(mtd, p, oob, NULL);
811
812         if (stat < 0)
813                 mtd->ecc_stats.failed++;
814         else
815                 mtd->ecc_stats.corrected += stat;
816
817         /* get back to oob start (end of page) */
818         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
819
820         /* read the oob */
821         chip->read_buf(mtd, oob, mtd->oobsize);
822
823         return 0;
824 }
825
826 /*
827  * HW ECC Correction
828  *
829  * function called after a read
830  *
831  * mtd:        MTD block structure
832  * dat:        raw data read from the chip
833  * read_ecc:   ECC from the chip (unused)
834  * isnull:     unused
835  *
836  * Detect and correct a 1 bit error for a page
837  */
838 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
839                 u_char *read_ecc, u_char *isnull)
840 {
841         struct nand_chip *nand_chip = mtd->priv;
842         unsigned int ecc_status;
843         unsigned int ecc_word, ecc_bit;
844
845         /* get the status from the Status Register */
846         ecc_status = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, SR);
847
848         /* if there's no error */
849         if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
850                 return 0;
851
852         /* get error bit offset (4 bits) */
853         ecc_bit = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_BITADDR;
854         /* get word address (12 bits) */
855         ecc_word = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_WORDADDR;
856         ecc_word >>= 4;
857
858         /* if there are multiple errors */
859         if (ecc_status & ATMEL_ECC_MULERR) {
860                 /* check if it is a freshly erased block
861                  * (filled with 0xff) */
862                 if ((ecc_bit == ATMEL_ECC_BITADDR)
863                                 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
864                         /* the block has just been erased, return OK */
865                         return 0;
866                 }
867                 /* it doesn't seems to be a freshly
868                  * erased block.
869                  * We can't correct so many errors */
870                 printk(KERN_WARNING "atmel_nand : multiple errors detected."
871                                 " Unable to correct.\n");
872                 return -EIO;
873         }
874
875         /* if there's a single bit error : we can correct it */
876         if (ecc_status & ATMEL_ECC_ECCERR) {
877                 /* there's nothing much to do here.
878                  * the bit error is on the ECC itself.
879                  */
880                 printk(KERN_WARNING "atmel_nand : one bit error on ECC code."
881                                 " Nothing to correct\n");
882                 return 0;
883         }
884
885         printk(KERN_WARNING "atmel_nand : one bit error on data."
886                         " (word offset in the page :"
887                         " 0x%x bit offset : 0x%x)\n",
888                         ecc_word, ecc_bit);
889         /* correct the error */
890         if (nand_chip->options & NAND_BUSWIDTH_16) {
891                 /* 16 bits words */
892                 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
893         } else {
894                 /* 8 bits words */
895                 dat[ecc_word] ^= (1 << ecc_bit);
896         }
897         printk(KERN_WARNING "atmel_nand : error corrected\n");
898         return 1;
899 }
900
901 /*
902  * Enable HW ECC : unused on most chips
903  */
904 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
905 {
906 }
907
908 int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
909 {
910         nand->ecc.mode = NAND_ECC_HW;
911         nand->ecc.calculate = atmel_nand_calculate;
912         nand->ecc.correct = atmel_nand_correct;
913         nand->ecc.hwctl = atmel_nand_hwctl;
914         nand->ecc.read_page = atmel_nand_read_page;
915         nand->ecc.bytes = 4;
916
917         if (nand->ecc.mode == NAND_ECC_HW) {
918                 /* ECC is calculated for the whole page (1 step) */
919                 nand->ecc.size = mtd->writesize;
920
921                 /* set ECC page size and oob layout */
922                 switch (mtd->writesize) {
923                 case 512:
924                         nand->ecc.layout = &atmel_oobinfo_small;
925                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
926                                         ATMEL_ECC_PAGESIZE_528);
927                         break;
928                 case 1024:
929                         nand->ecc.layout = &atmel_oobinfo_large;
930                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
931                                         ATMEL_ECC_PAGESIZE_1056);
932                         break;
933                 case 2048:
934                         nand->ecc.layout = &atmel_oobinfo_large;
935                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
936                                         ATMEL_ECC_PAGESIZE_2112);
937                         break;
938                 case 4096:
939                         nand->ecc.layout = &atmel_oobinfo_large;
940                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
941                                         ATMEL_ECC_PAGESIZE_4224);
942                         break;
943                 default:
944                         /* page size not handled by HW ECC */
945                         /* switching back to soft ECC */
946                         nand->ecc.mode = NAND_ECC_SOFT;
947                         nand->ecc.calculate = NULL;
948                         nand->ecc.correct = NULL;
949                         nand->ecc.hwctl = NULL;
950                         nand->ecc.read_page = NULL;
951                         nand->ecc.postpad = 0;
952                         nand->ecc.prepad = 0;
953                         nand->ecc.bytes = 0;
954                         break;
955                 }
956         }
957
958         return 0;
959 }
960
961 #endif /* CONFIG_ATMEL_NAND_HW_PMECC */
962
963 #endif /* CONFIG_ATMEL_NAND_HWECC */
964
965 static void at91_nand_hwcontrol(struct mtd_info *mtd,
966                                          int cmd, unsigned int ctrl)
967 {
968         struct nand_chip *this = mtd->priv;
969
970         if (ctrl & NAND_CTRL_CHANGE) {
971                 ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
972                 IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
973                              | CONFIG_SYS_NAND_MASK_CLE);
974
975                 if (ctrl & NAND_CLE)
976                         IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
977                 if (ctrl & NAND_ALE)
978                         IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
979
980 #ifdef CONFIG_SYS_NAND_ENABLE_PIN
981                 at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN,
982                                     !(ctrl & NAND_NCE));
983 #endif
984                 this->IO_ADDR_W = (void *) IO_ADDR_W;
985         }
986
987         if (cmd != NAND_CMD_NONE)
988                 writeb(cmd, this->IO_ADDR_W);
989 }
990
991 #ifdef CONFIG_SYS_NAND_READY_PIN
992 static int at91_nand_ready(struct mtd_info *mtd)
993 {
994         return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN);
995 }
996 #endif
997
998 #ifndef CONFIG_SYS_NAND_BASE_LIST
999 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
1000 #endif
1001 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
1002 static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
1003
1004 int atmel_nand_chip_init(int devnum, ulong base_addr)
1005 {
1006         int ret;
1007         struct mtd_info *mtd = &nand_info[devnum];
1008         struct nand_chip *nand = &nand_chip[devnum];
1009
1010         mtd->priv = nand;
1011         nand->IO_ADDR_R = nand->IO_ADDR_W = (void  __iomem *)base_addr;
1012
1013         nand->ecc.mode = NAND_ECC_SOFT;
1014 #ifdef CONFIG_SYS_NAND_DBW_16
1015         nand->options = NAND_BUSWIDTH_16;
1016 #endif
1017         nand->cmd_ctrl = at91_nand_hwcontrol;
1018 #ifdef CONFIG_SYS_NAND_READY_PIN
1019         nand->dev_ready = at91_nand_ready;
1020 #endif
1021         nand->chip_delay = 20;
1022
1023         ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
1024         if (ret)
1025                 return ret;
1026
1027 #ifdef CONFIG_ATMEL_NAND_HWECC
1028 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1029         ret = atmel_pmecc_nand_init_params(nand, mtd);
1030 #else
1031         ret = atmel_hwecc_nand_init_param(nand, mtd);
1032 #endif
1033         if (ret)
1034                 return ret;
1035 #endif
1036
1037         ret = nand_scan_tail(mtd);
1038         if (!ret)
1039                 nand_register(devnum);
1040
1041         return ret;
1042 }
1043
1044 void board_nand_init(void)
1045 {
1046         int i;
1047         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
1048                 if (atmel_nand_chip_init(i, base_addr[i]))
1049                         printk(KERN_ERR "atmel_nand: Fail to initialize #%d chip",
1050                                 i);
1051 }