2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian@popies.net>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
8 * Add Programmable Multibit ECC support for various AT91 SoC
9 * (C) Copyright 2012 ATMEL, Hong Xu
11 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/gpio.h>
22 #ifdef CONFIG_ATMEL_NAND_HWECC
24 /* Register access macros */
25 #define ecc_readl(add, reg) \
26 readl(AT91_BASE_SYS + add + ATMEL_ECC_##reg)
27 #define ecc_writel(add, reg, value) \
28 writel((value), AT91_BASE_SYS + add + ATMEL_ECC_##reg)
30 #include "atmel_nand_ecc.h" /* Hardware ECC registers */
32 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
34 struct atmel_nand_host {
35 struct pmecc_regs __iomem *pmecc;
36 struct pmecc_errloc_regs __iomem *pmerrloc;
37 void __iomem *pmecc_rom_base;
40 u16 pmecc_sector_size;
41 u32 pmecc_index_table_offset;
43 int pmecc_bytes_per_sector;
44 int pmecc_sector_number;
45 int pmecc_degree; /* Degree of remainders */
46 int pmecc_cw_len; /* Length of codeword */
48 /* lookup table for alpha_to and index_of */
49 void __iomem *pmecc_alpha_to;
50 void __iomem *pmecc_index_of;
52 /* data for pmecc computation */
54 int16_t *pmecc_partial_syn;
56 int16_t *pmecc_lmu; /* polynomal order */
62 static struct atmel_nand_host pmecc_host;
63 static struct nand_ecclayout atmel_pmecc_oobinfo;
66 * Return number of ecc bytes per sector according to sector size and
67 * correction capability
69 * Following table shows what at91 PMECC supported:
70 * Correction Capability Sector_512_bytes Sector_1024_bytes
71 * ===================== ================ =================
72 * 2-bits 4-bytes 4-bytes
73 * 4-bits 7-bytes 7-bytes
74 * 8-bits 13-bytes 14-bytes
75 * 12-bits 20-bytes 21-bytes
76 * 24-bits 39-bytes 42-bytes
78 static int pmecc_get_ecc_bytes(int cap, int sector_size)
80 int m = 12 + sector_size / 512;
81 return (m * cap + 7) / 8;
84 static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
85 int oobsize, int ecc_len)
89 layout->eccbytes = ecc_len;
91 /* ECC will occupy the last ecc_len bytes continuously */
92 for (i = 0; i < ecc_len; i++)
93 layout->eccpos[i] = oobsize - ecc_len + i;
95 layout->oobfree[0].offset = 2;
96 layout->oobfree[0].length =
97 oobsize - ecc_len - layout->oobfree[0].offset;
100 static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
104 table_size = host->pmecc_sector_size == 512 ?
105 PMECC_INDEX_TABLE_SIZE_512 : PMECC_INDEX_TABLE_SIZE_1024;
107 /* the ALPHA lookup table is right behind the INDEX lookup table. */
108 return host->pmecc_rom_base + host->pmecc_index_table_offset +
109 table_size * sizeof(int16_t);
112 static void pmecc_data_free(struct atmel_nand_host *host)
114 free(host->pmecc_partial_syn);
115 free(host->pmecc_si);
116 free(host->pmecc_lmu);
117 free(host->pmecc_smu);
118 free(host->pmecc_mu);
119 free(host->pmecc_dmu);
120 free(host->pmecc_delta);
123 static int pmecc_data_alloc(struct atmel_nand_host *host)
125 const int cap = host->pmecc_corr_cap;
128 size = (2 * cap + 1) * sizeof(int16_t);
129 host->pmecc_partial_syn = malloc(size);
130 host->pmecc_si = malloc(size);
131 host->pmecc_lmu = malloc((cap + 1) * sizeof(int16_t));
132 host->pmecc_smu = malloc((cap + 2) * size);
134 size = (cap + 1) * sizeof(int);
135 host->pmecc_mu = malloc(size);
136 host->pmecc_dmu = malloc(size);
137 host->pmecc_delta = malloc(size);
139 if (host->pmecc_partial_syn &&
149 pmecc_data_free(host);
154 static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
156 struct nand_chip *nand_chip = mtd->priv;
157 struct atmel_nand_host *host = nand_chip->priv;
161 /* Fill odd syndromes */
162 for (i = 0; i < host->pmecc_corr_cap; i++) {
163 value = readl(&host->pmecc->rem_port[sector].rem[i / 2]);
167 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
171 static void pmecc_substitute(struct mtd_info *mtd)
173 struct nand_chip *nand_chip = mtd->priv;
174 struct atmel_nand_host *host = nand_chip->priv;
175 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
176 int16_t __iomem *index_of = host->pmecc_index_of;
177 int16_t *partial_syn = host->pmecc_partial_syn;
178 const int cap = host->pmecc_corr_cap;
182 /* si[] is a table that holds the current syndrome value,
183 * an element of that table belongs to the field
187 memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
189 /* Computation 2t syndromes based on S(x) */
191 for (i = 1; i < 2 * cap; i += 2) {
192 for (j = 0; j < host->pmecc_degree; j++) {
193 if (partial_syn[i] & (0x1 << j))
194 si[i] = readw(alpha_to + i * j) ^ si[i];
197 /* Even syndrome = (Odd syndrome) ** 2 */
198 for (i = 2, j = 1; j <= cap; i = ++j << 1) {
204 tmp = readw(index_of + si[j]);
205 tmp = (tmp * 2) % host->pmecc_cw_len;
206 si[i] = readw(alpha_to + tmp);
212 * This function defines a Berlekamp iterative procedure for
213 * finding the value of the error location polynomial.
214 * The input is si[], initialize by pmecc_substitute().
215 * The output is smu[][].
217 * This function is written according to chip datasheet Chapter:
218 * Find the Error Location Polynomial Sigma(x) of Section:
219 * Programmable Multibit ECC Control (PMECC).
221 static void pmecc_get_sigma(struct mtd_info *mtd)
223 struct nand_chip *nand_chip = mtd->priv;
224 struct atmel_nand_host *host = nand_chip->priv;
226 int16_t *lmu = host->pmecc_lmu;
227 int16_t *si = host->pmecc_si;
228 int *mu = host->pmecc_mu;
229 int *dmu = host->pmecc_dmu; /* Discrepancy */
230 int *delta = host->pmecc_delta; /* Delta order */
231 int cw_len = host->pmecc_cw_len;
232 const int16_t cap = host->pmecc_corr_cap;
233 const int num = 2 * cap + 1;
234 int16_t __iomem *index_of = host->pmecc_index_of;
235 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
237 uint32_t dmu_0_count, tmp;
238 int16_t *smu = host->pmecc_smu;
240 /* index of largest delta */
245 /* Init the Sigma(x) */
246 memset(smu, 0, sizeof(int16_t) * ARRAY_SIZE(smu));
257 /* discrepancy set to 1 */
259 /* polynom order set to 0 */
261 /* delta[0] = (mu[0] * 2 - lmu[0]) >> 1; */
268 /* Sigma(x) set to 1 */
271 /* discrepancy set to S1 */
274 /* polynom order set to 0 */
277 /* delta[1] = (mu[1] * 2 - lmu[1]) >> 1; */
280 for (i = 1; i <= cap; i++) {
282 /* Begin Computing Sigma (Mu+1) and L(mu) */
283 /* check if discrepancy is set to 0 */
287 tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
288 if ((cap - (lmu[i] >> 1) - 1) & 0x1)
293 if (dmu_0_count == tmp) {
294 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
295 smu[(cap + 1) * num + j] =
298 lmu[cap + 1] = lmu[i];
303 for (j = 0; j <= lmu[i] >> 1; j++)
304 smu[(i + 1) * num + j] = smu[i * num + j];
306 /* copy previous polynom order to the next */
311 /* find largest delta with dmu != 0 */
312 for (j = 0; j < i; j++) {
313 if ((dmu[j]) && (delta[j] > largest)) {
319 /* compute difference */
320 diff = (mu[i] - mu[ro]);
322 /* Compute degree of the new smu polynomial */
323 if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
326 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
328 /* Init smu[i+1] with 0 */
329 for (k = 0; k < num; k++)
330 smu[(i + 1) * num + k] = 0;
332 /* Compute smu[i+1] */
333 for (k = 0; k <= lmu[ro] >> 1; k++) {
336 if (!(smu[ro * num + k] && dmu[i]))
338 a = readw(index_of + dmu[i]);
339 b = readw(index_of + dmu[ro]);
340 c = readw(index_of + smu[ro * num + k]);
341 tmp = a + (cw_len - b) + c;
342 a = readw(alpha_to + tmp % cw_len);
343 smu[(i + 1) * num + (k + diff)] = a;
346 for (k = 0; k <= lmu[i] >> 1; k++)
347 smu[(i + 1) * num + k] ^= smu[i * num + k];
350 /* End Computing Sigma (Mu+1) and L(mu) */
351 /* In either case compute delta */
352 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
354 /* Do not compute discrepancy for the last iteration */
358 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
361 dmu[i + 1] = si[tmp + 3];
362 } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
365 smu[(i + 1) * num + k]);
366 b = si[2 * (i - 1) + 3 - k];
367 c = readw(index_of + b);
370 dmu[i + 1] = readw(alpha_to + tmp) ^
377 static int pmecc_err_location(struct mtd_info *mtd)
379 struct nand_chip *nand_chip = mtd->priv;
380 struct atmel_nand_host *host = nand_chip->priv;
381 const int cap = host->pmecc_corr_cap;
382 const int num = 2 * cap + 1;
383 int sector_size = host->pmecc_sector_size;
384 int err_nbr = 0; /* number of error */
385 int roots_nbr; /* number of roots */
388 int16_t *smu = host->pmecc_smu;
389 int timeout = PMECC_MAX_TIMEOUT_US;
391 writel(PMERRLOC_DISABLE, &host->pmerrloc->eldis);
393 for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
394 writel(smu[(cap + 1) * num + i], &host->pmerrloc->sigma[i]);
398 val = PMERRLOC_ELCFG_NUM_ERRORS(err_nbr - 1);
399 if (sector_size == 1024)
400 val |= PMERRLOC_ELCFG_SECTOR_1024;
402 writel(val, &host->pmerrloc->elcfg);
403 writel(sector_size * 8 + host->pmecc_degree * cap,
404 &host->pmerrloc->elen);
407 if (readl(&host->pmerrloc->elisr) & PMERRLOC_CALC_DONE)
414 dev_err(host->dev, "atmel_nand : Timeout to calculate PMECC error location\n");
418 roots_nbr = (readl(&host->pmerrloc->elisr) & PMERRLOC_ERR_NUM_MASK)
420 /* Number of roots == degree of smu hence <= cap */
421 if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
424 /* Number of roots does not match the degree of smu
425 * unable to correct error */
429 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
430 int sector_num, int extra_bytes, int err_nbr)
432 struct nand_chip *nand_chip = mtd->priv;
433 struct atmel_nand_host *host = nand_chip->priv;
435 int byte_pos, bit_pos, sector_size, pos;
439 sector_size = host->pmecc_sector_size;
442 tmp = readl(&host->pmerrloc->el[i]) - 1;
446 if (byte_pos >= (sector_size + extra_bytes))
447 BUG(); /* should never happen */
449 if (byte_pos < sector_size) {
450 err_byte = *(buf + byte_pos);
451 *(buf + byte_pos) ^= (1 << bit_pos);
453 pos = sector_num * host->pmecc_sector_size + byte_pos;
454 dev_dbg(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
455 pos, bit_pos, err_byte, *(buf + byte_pos));
457 /* Bit flip in OOB area */
458 tmp = sector_num * host->pmecc_bytes_per_sector
459 + (byte_pos - sector_size);
461 ecc[tmp] ^= (1 << bit_pos);
463 pos = tmp + nand_chip->ecc.layout->eccpos[0];
464 dev_dbg(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
465 pos, bit_pos, err_byte, ecc[tmp]);
475 static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
478 struct nand_chip *nand_chip = mtd->priv;
479 struct atmel_nand_host *host = nand_chip->priv;
480 int i, err_nbr, eccbytes;
483 eccbytes = nand_chip->ecc.bytes;
484 for (i = 0; i < eccbytes; i++)
487 /* Erased page, return OK */
491 for (i = 0; i < host->pmecc_sector_number; i++) {
493 if (pmecc_stat & 0x1) {
494 buf_pos = buf + i * host->pmecc_sector_size;
496 pmecc_gen_syndrome(mtd, i);
497 pmecc_substitute(mtd);
498 pmecc_get_sigma(mtd);
500 err_nbr = pmecc_err_location(mtd);
502 dev_err(host->dev, "PMECC: Too many errors\n");
503 mtd->ecc_stats.failed++;
506 pmecc_correct_data(mtd, buf_pos, ecc, i,
507 host->pmecc_bytes_per_sector, err_nbr);
508 mtd->ecc_stats.corrected += err_nbr;
517 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
518 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
520 struct atmel_nand_host *host = chip->priv;
521 int eccsize = chip->ecc.size;
522 uint8_t *oob = chip->oob_poi;
523 uint32_t *eccpos = chip->ecc.layout->eccpos;
525 int timeout = PMECC_MAX_TIMEOUT_US;
527 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
528 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
529 pmecc_writel(host->pmecc, cfg, ((pmecc_readl(host->pmecc, cfg))
530 & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
532 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
533 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
535 chip->read_buf(mtd, buf, eccsize);
536 chip->read_buf(mtd, oob, mtd->oobsize);
539 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
546 dev_err(host->dev, "atmel_nand : Timeout to read PMECC page\n");
550 stat = pmecc_readl(host->pmecc, isr);
552 if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
558 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
559 struct nand_chip *chip, const uint8_t *buf,
562 struct atmel_nand_host *host = chip->priv;
563 uint32_t *eccpos = chip->ecc.layout->eccpos;
565 int timeout = PMECC_MAX_TIMEOUT_US;
567 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
568 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
570 pmecc_writel(host->pmecc, cfg, (pmecc_readl(host->pmecc, cfg) |
571 PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
573 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
574 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
576 chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
579 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
586 dev_err(host->dev, "atmel_nand : Timeout to read PMECC status, fail to write PMECC in oob\n");
590 for (i = 0; i < host->pmecc_sector_number; i++) {
591 for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
594 pos = i * host->pmecc_bytes_per_sector + j;
595 chip->oob_poi[eccpos[pos]] =
596 readb(&host->pmecc->ecc_port[i].ecc[j]);
599 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
604 static void atmel_pmecc_core_init(struct mtd_info *mtd)
606 struct nand_chip *nand_chip = mtd->priv;
607 struct atmel_nand_host *host = nand_chip->priv;
609 struct nand_ecclayout *ecc_layout;
611 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
612 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
614 switch (host->pmecc_corr_cap) {
616 val = PMECC_CFG_BCH_ERR2;
619 val = PMECC_CFG_BCH_ERR4;
622 val = PMECC_CFG_BCH_ERR8;
625 val = PMECC_CFG_BCH_ERR12;
628 val = PMECC_CFG_BCH_ERR24;
632 if (host->pmecc_sector_size == 512)
633 val |= PMECC_CFG_SECTOR512;
634 else if (host->pmecc_sector_size == 1024)
635 val |= PMECC_CFG_SECTOR1024;
637 switch (host->pmecc_sector_number) {
639 val |= PMECC_CFG_PAGE_1SECTOR;
642 val |= PMECC_CFG_PAGE_2SECTORS;
645 val |= PMECC_CFG_PAGE_4SECTORS;
648 val |= PMECC_CFG_PAGE_8SECTORS;
652 val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
653 | PMECC_CFG_AUTO_DISABLE);
654 pmecc_writel(host->pmecc, cfg, val);
656 ecc_layout = nand_chip->ecc.layout;
657 pmecc_writel(host->pmecc, sarea, mtd->oobsize - 1);
658 pmecc_writel(host->pmecc, saddr, ecc_layout->eccpos[0]);
659 pmecc_writel(host->pmecc, eaddr,
660 ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
661 /* See datasheet about PMECC Clock Control Register */
662 pmecc_writel(host->pmecc, clk, PMECC_CLK_133MHZ);
663 pmecc_writel(host->pmecc, idr, 0xff);
664 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
667 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
669 * get_onfi_ecc_param - Get ECC requirement from ONFI parameters
670 * @ecc_bits: store the ONFI ECC correct bits capbility
671 * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
673 * Returns -1 if ONFI parameters is not supported. In this case @ecc_bits,
674 * @sector_size are initialize to 0.
675 * Return 0 if success to get the ECC requirement.
677 static int get_onfi_ecc_param(struct nand_chip *chip,
678 int *ecc_bits, int *sector_size)
680 *ecc_bits = *sector_size = 0;
682 if (chip->onfi_params.ecc_bits == 0xff)
683 /* TODO: the sector_size and ecc_bits need to be find in
684 * extended ecc parameter, currently we don't support it.
688 *ecc_bits = chip->onfi_params.ecc_bits;
690 /* The default sector size (ecc codeword size) is 512 */
697 * pmecc_choose_ecc - Get ecc requirement from ONFI parameters. If
698 * pmecc_corr_cap or pmecc_sector_size is 0, then set it as
699 * ONFI ECC parameters.
700 * @host: point to an atmel_nand_host structure.
701 * if host->pmecc_corr_cap is 0 then set it as the ONFI ecc_bits.
702 * if host->pmecc_sector_size is 0 then set it as the ONFI sector_size.
703 * @chip: point to an nand_chip structure.
704 * @cap: store the ONFI ECC correct bits capbility
705 * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
707 * Return 0 if success. otherwise return the error code.
709 static int pmecc_choose_ecc(struct atmel_nand_host *host,
710 struct nand_chip *chip,
711 int *cap, int *sector_size)
713 /* Get ECC requirement from ONFI parameters */
714 *cap = *sector_size = 0;
715 if (chip->onfi_version) {
716 if (!get_onfi_ecc_param(chip, cap, sector_size)) {
717 MTDDEBUG(MTD_DEBUG_LEVEL1, "ONFI params, minimum required ECC: %d bits in %d bytes\n",
720 dev_info(host->dev, "NAND chip ECC reqirement is in Extended ONFI parameter, we don't support yet.\n");
723 dev_info(host->dev, "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes");
725 if (*cap == 0 && *sector_size == 0) {
726 /* Non-ONFI compliant or use extended ONFI parameters */
731 /* If head file doesn't specify then use the one in ONFI parameters */
732 if (host->pmecc_corr_cap == 0) {
733 /* use the most fitable ecc bits (the near bigger one ) */
735 host->pmecc_corr_cap = 2;
737 host->pmecc_corr_cap = 4;
739 host->pmecc_corr_cap = 8;
741 host->pmecc_corr_cap = 12;
743 host->pmecc_corr_cap = 24;
747 if (host->pmecc_sector_size == 0) {
748 /* use the most fitable sector size (the near smaller one ) */
749 if (*sector_size >= 1024)
750 host->pmecc_sector_size = 1024;
751 else if (*sector_size >= 512)
752 host->pmecc_sector_size = 512;
760 static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
761 struct mtd_info *mtd)
763 struct atmel_nand_host *host;
764 int cap, sector_size;
766 host = nand->priv = &pmecc_host;
768 nand->ecc.mode = NAND_ECC_HW;
769 nand->ecc.calculate = NULL;
770 nand->ecc.correct = NULL;
771 nand->ecc.hwctl = NULL;
773 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
774 host->pmecc_corr_cap = host->pmecc_sector_size = 0;
776 #ifdef CONFIG_PMECC_CAP
777 host->pmecc_corr_cap = CONFIG_PMECC_CAP;
779 #ifdef CONFIG_PMECC_SECTOR_SIZE
780 host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
782 /* Get ECC requirement of ONFI parameters. And if CONFIG_PMECC_CAP or
783 * CONFIG_PMECC_SECTOR_SIZE not defined, then use ecc_bits, sector_size
786 if (pmecc_choose_ecc(host, nand, &cap, §or_size)) {
787 dev_err(host->dev, "The NAND flash's ECC requirement(ecc_bits: %d, sector_size: %d) are not support!",
792 if (cap > host->pmecc_corr_cap)
793 dev_info(host->dev, "WARNING: Using different ecc correct bits(%d bit) from Nand ONFI ECC reqirement (%d bit).\n",
794 host->pmecc_corr_cap, cap);
795 if (sector_size < host->pmecc_sector_size)
796 dev_info(host->dev, "WARNING: Using different ecc correct sector size (%d bytes) from Nand ONFI ECC reqirement (%d bytes).\n",
797 host->pmecc_sector_size, sector_size);
798 #else /* CONFIG_SYS_NAND_ONFI_DETECTION */
799 host->pmecc_corr_cap = CONFIG_PMECC_CAP;
800 host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
803 cap = host->pmecc_corr_cap;
804 sector_size = host->pmecc_sector_size;
806 /* TODO: need check whether cap & sector_size is validate */
808 if (host->pmecc_sector_size == 512)
809 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_512;
811 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_1024;
813 MTDDEBUG(MTD_DEBUG_LEVEL1,
814 "Initialize PMECC params, cap: %d, sector: %d\n",
817 host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC;
818 host->pmerrloc = (struct pmecc_errloc_regs __iomem *)
820 host->pmecc_rom_base = (void __iomem *) ATMEL_BASE_ROM;
822 /* ECC is calculated for the whole page (1 step) */
823 nand->ecc.size = mtd->writesize;
825 /* set ECC page size and oob layout */
826 switch (mtd->writesize) {
830 host->pmecc_degree = (sector_size == 512) ?
831 PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
832 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
833 host->pmecc_sector_number = mtd->writesize / sector_size;
834 host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
836 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
837 host->pmecc_index_of = host->pmecc_rom_base +
838 host->pmecc_index_table_offset;
841 nand->ecc.bytes = host->pmecc_bytes_per_sector *
842 host->pmecc_sector_number;
844 if (nand->ecc.bytes > MTD_MAX_ECCPOS_ENTRIES_LARGE) {
845 dev_err(host->dev, "too large eccpos entries. max support ecc.bytes is %d\n",
846 MTD_MAX_ECCPOS_ENTRIES_LARGE);
850 if (nand->ecc.bytes > mtd->oobsize - 2) {
851 dev_err(host->dev, "No room for ECC bytes\n");
854 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
857 nand->ecc.layout = &atmel_pmecc_oobinfo;
862 dev_err(host->dev, "Unsupported page size for PMECC, use Software ECC\n");
864 /* page size not handled by HW ECC */
865 /* switching back to soft ECC */
866 nand->ecc.mode = NAND_ECC_SOFT;
867 nand->ecc.read_page = NULL;
868 nand->ecc.postpad = 0;
869 nand->ecc.prepad = 0;
874 /* Allocate data for PMECC computation */
875 if (pmecc_data_alloc(host)) {
876 dev_err(host->dev, "Cannot allocate memory for PMECC computation!\n");
880 nand->ecc.read_page = atmel_nand_pmecc_read_page;
881 nand->ecc.write_page = atmel_nand_pmecc_write_page;
882 nand->ecc.strength = cap;
884 atmel_pmecc_core_init(mtd);
891 /* oob layout for large page size
892 * bad block info is on bytes 0 and 1
893 * the bytes have to be consecutives to avoid
894 * several NAND_CMD_RNDOUT during read
896 static struct nand_ecclayout atmel_oobinfo_large = {
898 .eccpos = {60, 61, 62, 63},
904 /* oob layout for small page size
905 * bad block info is on bytes 4 and 5
906 * the bytes have to be consecutives to avoid
907 * several NAND_CMD_RNDOUT during read
909 static struct nand_ecclayout atmel_oobinfo_small = {
911 .eccpos = {0, 1, 2, 3},
920 * function called after a write
922 * mtd: MTD block structure
923 * dat: raw data (unused)
924 * ecc_code: buffer for ECC
926 static int atmel_nand_calculate(struct mtd_info *mtd,
927 const u_char *dat, unsigned char *ecc_code)
929 unsigned int ecc_value;
931 /* get the first 2 ECC bytes */
932 ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR);
934 ecc_code[0] = ecc_value & 0xFF;
935 ecc_code[1] = (ecc_value >> 8) & 0xFF;
937 /* get the last 2 ECC bytes */
938 ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, NPR) & ATMEL_ECC_NPARITY;
940 ecc_code[2] = ecc_value & 0xFF;
941 ecc_code[3] = (ecc_value >> 8) & 0xFF;
947 * HW ECC read page function
949 * mtd: mtd info structure
950 * chip: nand chip info structure
951 * buf: buffer to store read data
952 * oob_required: caller expects OOB data read to chip->oob_poi
954 static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
955 uint8_t *buf, int oob_required, int page)
957 int eccsize = chip->ecc.size;
958 int eccbytes = chip->ecc.bytes;
959 uint32_t *eccpos = chip->ecc.layout->eccpos;
961 uint8_t *oob = chip->oob_poi;
966 chip->read_buf(mtd, p, eccsize);
968 /* move to ECC position if needed */
969 if (eccpos[0] != 0) {
970 /* This only works on large pages
971 * because the ECC controller waits for
972 * NAND_CMD_RNDOUTSTART after the
974 * anyway, for small pages, the eccpos[0] == 0
976 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
977 mtd->writesize + eccpos[0], -1);
980 /* the ECC controller needs to read the ECC just after the data */
981 ecc_pos = oob + eccpos[0];
982 chip->read_buf(mtd, ecc_pos, eccbytes);
984 /* check if there's an error */
985 stat = chip->ecc.correct(mtd, p, oob, NULL);
988 mtd->ecc_stats.failed++;
990 mtd->ecc_stats.corrected += stat;
992 /* get back to oob start (end of page) */
993 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
996 chip->read_buf(mtd, oob, mtd->oobsize);
1004 * function called after a read
1006 * mtd: MTD block structure
1007 * dat: raw data read from the chip
1008 * read_ecc: ECC from the chip (unused)
1011 * Detect and correct a 1 bit error for a page
1013 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
1014 u_char *read_ecc, u_char *isnull)
1016 struct nand_chip *nand_chip = mtd->priv;
1017 unsigned int ecc_status;
1018 unsigned int ecc_word, ecc_bit;
1020 /* get the status from the Status Register */
1021 ecc_status = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, SR);
1023 /* if there's no error */
1024 if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
1027 /* get error bit offset (4 bits) */
1028 ecc_bit = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_BITADDR;
1029 /* get word address (12 bits) */
1030 ecc_word = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_WORDADDR;
1033 /* if there are multiple errors */
1034 if (ecc_status & ATMEL_ECC_MULERR) {
1035 /* check if it is a freshly erased block
1036 * (filled with 0xff) */
1037 if ((ecc_bit == ATMEL_ECC_BITADDR)
1038 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
1039 /* the block has just been erased, return OK */
1042 /* it doesn't seems to be a freshly
1044 * We can't correct so many errors */
1045 dev_warn(host->dev, "atmel_nand : multiple errors detected."
1046 " Unable to correct.\n");
1050 /* if there's a single bit error : we can correct it */
1051 if (ecc_status & ATMEL_ECC_ECCERR) {
1052 /* there's nothing much to do here.
1053 * the bit error is on the ECC itself.
1055 dev_warn(host->dev, "atmel_nand : one bit error on ECC code."
1056 " Nothing to correct\n");
1060 dev_warn(host->dev, "atmel_nand : one bit error on data."
1061 " (word offset in the page :"
1062 " 0x%x bit offset : 0x%x)\n",
1064 /* correct the error */
1065 if (nand_chip->options & NAND_BUSWIDTH_16) {
1067 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1070 dat[ecc_word] ^= (1 << ecc_bit);
1072 dev_warn(host->dev, "atmel_nand : error corrected\n");
1077 * Enable HW ECC : unused on most chips
1079 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1083 int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
1085 nand->ecc.mode = NAND_ECC_HW;
1086 nand->ecc.calculate = atmel_nand_calculate;
1087 nand->ecc.correct = atmel_nand_correct;
1088 nand->ecc.hwctl = atmel_nand_hwctl;
1089 nand->ecc.read_page = atmel_nand_read_page;
1090 nand->ecc.bytes = 4;
1092 if (nand->ecc.mode == NAND_ECC_HW) {
1093 /* ECC is calculated for the whole page (1 step) */
1094 nand->ecc.size = mtd->writesize;
1096 /* set ECC page size and oob layout */
1097 switch (mtd->writesize) {
1099 nand->ecc.layout = &atmel_oobinfo_small;
1100 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1101 ATMEL_ECC_PAGESIZE_528);
1104 nand->ecc.layout = &atmel_oobinfo_large;
1105 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1106 ATMEL_ECC_PAGESIZE_1056);
1109 nand->ecc.layout = &atmel_oobinfo_large;
1110 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1111 ATMEL_ECC_PAGESIZE_2112);
1114 nand->ecc.layout = &atmel_oobinfo_large;
1115 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1116 ATMEL_ECC_PAGESIZE_4224);
1119 /* page size not handled by HW ECC */
1120 /* switching back to soft ECC */
1121 nand->ecc.mode = NAND_ECC_SOFT;
1122 nand->ecc.calculate = NULL;
1123 nand->ecc.correct = NULL;
1124 nand->ecc.hwctl = NULL;
1125 nand->ecc.read_page = NULL;
1126 nand->ecc.postpad = 0;
1127 nand->ecc.prepad = 0;
1128 nand->ecc.bytes = 0;
1136 #endif /* CONFIG_ATMEL_NAND_HW_PMECC */
1138 #endif /* CONFIG_ATMEL_NAND_HWECC */
1140 static void at91_nand_hwcontrol(struct mtd_info *mtd,
1141 int cmd, unsigned int ctrl)
1143 struct nand_chip *this = mtd->priv;
1145 if (ctrl & NAND_CTRL_CHANGE) {
1146 ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
1147 IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
1148 | CONFIG_SYS_NAND_MASK_CLE);
1150 if (ctrl & NAND_CLE)
1151 IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
1152 if (ctrl & NAND_ALE)
1153 IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
1155 #ifdef CONFIG_SYS_NAND_ENABLE_PIN
1156 gpio_set_value(CONFIG_SYS_NAND_ENABLE_PIN, !(ctrl & NAND_NCE));
1158 this->IO_ADDR_W = (void *) IO_ADDR_W;
1161 if (cmd != NAND_CMD_NONE)
1162 writeb(cmd, this->IO_ADDR_W);
1165 #ifdef CONFIG_SYS_NAND_READY_PIN
1166 static int at91_nand_ready(struct mtd_info *mtd)
1168 return gpio_get_value(CONFIG_SYS_NAND_READY_PIN);
1172 #ifndef CONFIG_SYS_NAND_BASE_LIST
1173 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
1175 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
1176 static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
1178 int atmel_nand_chip_init(int devnum, ulong base_addr)
1181 struct mtd_info *mtd = &nand_info[devnum];
1182 struct nand_chip *nand = &nand_chip[devnum];
1185 nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr;
1187 #ifdef CONFIG_NAND_ECC_BCH
1188 nand->ecc.mode = NAND_ECC_SOFT_BCH;
1190 nand->ecc.mode = NAND_ECC_SOFT;
1192 #ifdef CONFIG_SYS_NAND_DBW_16
1193 nand->options = NAND_BUSWIDTH_16;
1195 nand->cmd_ctrl = at91_nand_hwcontrol;
1196 #ifdef CONFIG_SYS_NAND_READY_PIN
1197 nand->dev_ready = at91_nand_ready;
1199 nand->chip_delay = 75;
1201 ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
1205 #ifdef CONFIG_ATMEL_NAND_HWECC
1206 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1207 ret = atmel_pmecc_nand_init_params(nand, mtd);
1209 ret = atmel_hwecc_nand_init_param(nand, mtd);
1215 ret = nand_scan_tail(mtd);
1217 nand_register(devnum);
1222 void board_nand_init(void)
1225 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
1226 if (atmel_nand_chip_init(i, base_addr[i]))
1227 dev_err(host->dev, "atmel_nand: Fail to initialize #%d chip",