2 * Driver for Blackfin on-chip NAND controller.
4 * Enter bugs at http://blackfin.uclinux.org/
6 * Copyright (c) 2007-2008 Analog Devices Inc.
8 * Licensed under the GPL-2 or later.
12 * - move bit defines into mach-common/bits/nand.h
13 * - try and replace all IRQSTAT usage with STAT polling
14 * - have software ecc mode use same algo as hw ecc ?
21 # define pr_stamp() printf("%s:%s:%i: here i am\n", __FILE__, __func__, __LINE__)
28 #include <asm/blackfin.h>
30 /* Bit masks for NFC_CTL */
32 #define WR_DLY 0xf /* Write Strobe Delay */
33 #define RD_DLY 0xf0 /* Read Strobe Delay */
34 #define NWIDTH 0x100 /* NAND Data Width */
35 #define PG_SIZE 0x200 /* Page Size */
37 /* Bit masks for NFC_STAT */
39 #define NBUSY 0x1 /* Not Busy */
40 #define WB_FULL 0x2 /* Write Buffer Full */
41 #define PG_WR_STAT 0x4 /* Page Write Pending */
42 #define PG_RD_STAT 0x8 /* Page Read Pending */
43 #define WB_EMPTY 0x10 /* Write Buffer Empty */
45 /* Bit masks for NFC_IRQSTAT */
47 #define NBUSYIRQ 0x1 /* Not Busy IRQ */
48 #define WB_OVF 0x2 /* Write Buffer Overflow */
49 #define WB_EDGE 0x4 /* Write Buffer Edge Detect */
50 #define RD_RDY 0x8 /* Read Data Ready */
51 #define WR_DONE 0x10 /* Page Write Done */
53 #define NAND_IS_512() (CONFIG_BFIN_NFC_CTL_VAL & 0x200)
56 * hardware specific access to control-lines
58 static void bfin_nfc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
62 if (cmd == NAND_CMD_NONE)
65 while (bfin_read_NFC_STAT() & WB_FULL)
69 bfin_write_NFC_CMD(cmd);
71 bfin_write_NFC_ADDR(cmd);
75 int bfin_nfc_devready(struct mtd_info *mtd)
78 return (bfin_read_NFC_STAT() & NBUSY ? 1 : 0);
82 * PIO mode for buffer writing and reading
84 static void bfin_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
91 * Data reads are requested by first writing to NFC_DATA_RD
92 * and then reading back from NFC_READ.
94 for (i = 0; i < len; ++i) {
95 while (bfin_read_NFC_STAT() & WB_FULL)
99 /* Contents do not matter */
100 bfin_write_NFC_DATA_RD(0x0000);
102 while (!(bfin_read_NFC_IRQSTAT() & RD_RDY))
106 buf[i] = bfin_read_NFC_READ();
108 bfin_write_NFC_IRQSTAT(RD_RDY);
112 static uint8_t bfin_nfc_read_byte(struct mtd_info *mtd)
117 bfin_nfc_read_buf(mtd, &val, 1);
121 static void bfin_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
127 for (i = 0; i < len; ++i) {
128 while (bfin_read_NFC_STAT() & WB_FULL)
132 bfin_write_NFC_DATA_WR(buf[i]);
138 * These allow the bfin to use the controller's ECC
139 * generator block to ECC the data as it passes through
143 * ECC error correction function
145 static int bfin_nfc_correct_data_256(struct mtd_info *mtd, u_char *dat,
146 u_char *read_ecc, u_char *calc_ecc)
150 unsigned short failing_bit, failing_byte;
155 calced = calc_ecc[0] | (calc_ecc[1] << 8) | (calc_ecc[2] << 16);
156 stored = read_ecc[0] | (read_ecc[1] << 8) | (read_ecc[2] << 16);
158 syndrome[0] = (calced ^ stored);
161 * syndrome 0: all zero
165 if (!syndrome[0] || !calced || !stored)
169 * sysdrome 0: only one bit is one
170 * ECC data was incorrect
173 if (hweight32(syndrome[0]) == 1)
176 syndrome[1] = (calced & 0x7FF) ^ (stored & 0x7FF);
177 syndrome[2] = (calced & 0x7FF) ^ ((calced >> 11) & 0x7FF);
178 syndrome[3] = (stored & 0x7FF) ^ ((stored >> 11) & 0x7FF);
179 syndrome[4] = syndrome[2] ^ syndrome[3];
182 * sysdrome 0: exactly 11 bits are one, each parity
183 * and parity' pair is 1 & 0 or 0 & 1.
184 * 1-bit correctable error
187 if (hweight32(syndrome[0]) == 11 && syndrome[4] == 0x7FF) {
188 failing_bit = syndrome[1] & 0x7;
189 failing_byte = syndrome[1] >> 0x3;
190 data = *(dat + failing_byte);
191 data = data ^ (0x1 << failing_bit);
192 *(dat + failing_byte) = data;
198 * sysdrome 0: random data
199 * More than 1-bit error, non-correctable error
200 * Discard data, mark bad block
206 static int bfin_nfc_correct_data(struct mtd_info *mtd, u_char *dat,
207 u_char *read_ecc, u_char *calc_ecc)
213 ret = bfin_nfc_correct_data_256(mtd, dat, read_ecc, calc_ecc);
215 /* If page size is 512, correct second 256 bytes */
220 ret |= bfin_nfc_correct_data_256(mtd, dat, read_ecc, calc_ecc);
226 static void reset_ecc(void)
228 bfin_write_NFC_RST(0x1);
229 while (bfin_read_NFC_RST() & 1)
233 static void bfin_nfc_enable_hwecc(struct mtd_info *mtd, int mode)
238 static int bfin_nfc_calculate_ecc(struct mtd_info *mtd,
239 const u_char *dat, u_char *ecc_code)
247 /* first 4 bytes ECC code for 256 page size */
248 ecc0 = bfin_read_NFC_ECC0();
249 ecc1 = bfin_read_NFC_ECC1();
251 code[0] = (ecc0 & 0x7FF) | ((ecc1 & 0x7FF) << 11);
253 /* first 3 bytes in ecc_code for 256 page size */
255 memcpy(ecc_code, p, 3);
257 /* second 4 bytes ECC code for 512 page size */
259 ecc0 = bfin_read_NFC_ECC2();
260 ecc1 = bfin_read_NFC_ECC3();
261 code[1] = (ecc0 & 0x7FF) | ((ecc1 & 0x7FF) << 11);
263 /* second 3 bytes in ecc_code for second 256
264 * bytes of 512 page size
266 p = (u8 *) (code + 1);
267 memcpy((ecc_code + 3), p, 3);
275 #ifdef CONFIG_BFIN_NFC_BOOTROM_ECC
276 # define BOOTROM_ECC 1
278 # define BOOTROM_ECC 0
281 static uint8_t bbt_pattern[] = { 0xff };
283 static struct nand_bbt_descr bootrom_bbt = {
287 .pattern = bbt_pattern,
290 static struct nand_ecclayout bootrom_ecclayout = {
293 0x8 * 0, 0x8 * 0 + 1, 0x8 * 0 + 2,
294 0x8 * 1, 0x8 * 1 + 1, 0x8 * 1 + 2,
295 0x8 * 2, 0x8 * 2 + 1, 0x8 * 2 + 2,
296 0x8 * 3, 0x8 * 3 + 1, 0x8 * 3 + 2,
297 0x8 * 4, 0x8 * 4 + 1, 0x8 * 4 + 2,
298 0x8 * 5, 0x8 * 5 + 1, 0x8 * 5 + 2,
299 0x8 * 6, 0x8 * 6 + 1, 0x8 * 6 + 2,
300 0x8 * 7, 0x8 * 7 + 1, 0x8 * 7 + 2
315 * Board-specific NAND initialization. The following members of the
316 * argument are board-specific (per include/linux/mtd/nand.h):
317 * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
318 * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
319 * - cmd_ctrl: hardwarespecific function for accesing control-lines
320 * - dev_ready: hardwarespecific function for accesing device ready/busy line
321 * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
322 * only be provided if a hardware ECC is available
323 * - ecc.mode: mode of ecc, see defines
324 * - chip_delay: chip dependent delay for transfering data from array to
326 * - options: various chip options. They can partly be set to inform
327 * nand_scan about special functionality. See the defines for further
329 * Members with a "?" were not set in the merged testing-NAND branch,
330 * so they are not set here either.
332 int board_nand_init(struct nand_chip *chip)
336 /* set width/ecc/timings/etc... */
337 bfin_write_NFC_CTL(CONFIG_BFIN_NFC_CTL_VAL);
339 /* clear interrupt status */
340 bfin_write_NFC_IRQMASK(0x0);
341 bfin_write_NFC_IRQSTAT(0xffff);
343 /* enable GPIO function enable register */
345 bfin_write_PORTJ_FER(bfin_read_PORTJ_FER() | 6);
346 #elif defined(__ADSPBF52x__)
347 bfin_write_PORTH_FER(bfin_read_PORTH_FER() | 0xFCFF);
348 bfin_write_PORTH_MUX(0);
350 # error no support for this variant
353 chip->cmd_ctrl = bfin_nfc_cmd_ctrl;
354 chip->read_buf = bfin_nfc_read_buf;
355 chip->write_buf = bfin_nfc_write_buf;
356 chip->read_byte = bfin_nfc_read_byte;
358 #ifdef CONFIG_BFIN_NFC_NO_HW_ECC
365 chip->badblock_pattern = &bootrom_bbt;
366 chip->ecc.layout = &bootrom_ecclayout;
368 if (!NAND_IS_512()) {
370 chip->ecc.size = 256;
373 chip->ecc.size = 512;
375 chip->ecc.mode = NAND_ECC_HW;
376 chip->ecc.calculate = bfin_nfc_calculate_ecc;
377 chip->ecc.correct = bfin_nfc_correct_data;
378 chip->ecc.hwctl = bfin_nfc_enable_hwecc;
380 chip->ecc.mode = NAND_ECC_SOFT;
381 chip->dev_ready = bfin_nfc_devready;
382 chip->chip_delay = 0;