2 * NAND driver for TI DaVinci based boards.
4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6 * Based on Linux DaVinci NAND driver by TI. Original copyright follows:
11 * linux/drivers/mtd/nand/nand_davinci.c
15 * Copyright (C) 2006 Texas Instruments.
17 * ----------------------------------------------------------------------------
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation; either version 2 of the License, or
22 * (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
32 * ----------------------------------------------------------------------------
35 * This is a device driver for the NAND flash device found on the
36 * DaVinci board which utilizes the Samsung k9k2g08 part.
39 ver. 1.0: Feb 2005, Vinod/Sudhakar
47 #include <asm/arch/nand_defs.h>
48 #include <asm/arch/emif_defs.h>
50 extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
52 static emif_registers *const emif_regs = (void *) DAVINCI_ASYNC_EMIF_CNTRL_BASE;
54 static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
56 struct nand_chip *this = mtd->priv;
57 u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
59 IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
61 if (ctrl & NAND_CTRL_CHANGE) {
62 if ( ctrl & NAND_CLE )
63 IO_ADDR_W |= MASK_CLE;
64 if ( ctrl & NAND_ALE )
65 IO_ADDR_W |= MASK_ALE;
66 this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
69 if (cmd != NAND_CMD_NONE)
70 writeb(cmd, this->IO_ADDR_W);
73 /* Set WP on deselect, write enable on select */
74 static void nand_davinci_select_chip(struct mtd_info *mtd, int chip)
76 #define GPIO_SET_DATA01 0x01c67018
77 #define GPIO_CLR_DATA01 0x01c6701c
78 #define GPIO_NAND_WP (1 << 4)
79 #ifdef SONATA_BOARD_GPIOWP
81 REG(GPIO_CLR_DATA01) |= GPIO_NAND_WP;
83 REG(GPIO_SET_DATA01) |= GPIO_NAND_WP;
88 #ifdef CONFIG_SYS_NAND_HW_ECC
89 #ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
90 /* Linux-compatible ECC uses MTD defaults. */
91 /* These layouts are not compatible with Linux or RBL/UBL. */
92 #ifdef CONFIG_SYS_NAND_LARGEPAGE
93 static struct nand_ecclayout davinci_nand_ecclayout = {
95 .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
97 {.offset = 2, .length = 6},
98 {.offset = 12, .length = 12},
99 {.offset = 28, .length = 12},
100 {.offset = 44, .length = 12},
101 {.offset = 60, .length = 4}
104 #elif defined(CONFIG_SYS_NAND_SMALLPAGE)
105 static struct nand_ecclayout davinci_nand_ecclayout = {
109 {.offset = 6, .length = 2},
110 {.offset = 8, .length = 8}
114 #error "Either CONFIG_SYS_NAND_LARGEPAGE or CONFIG_SYS_NAND_SMALLPAGE must be defined!"
116 #endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
118 static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
122 dummy = emif_regs->NANDF1ECC;
123 #ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
124 dummy = emif_regs->NANDF2ECC;
125 dummy = emif_regs->NANDF3ECC;
126 dummy = emif_regs->NANDF4ECC;
129 /* FIXME: only chipselect 0 is supported for now */
130 emif_regs->NANDFCR |= 1 << 8;
133 static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
138 ecc = emif_regs->NANDF1ECC;
139 else if (region == 2)
140 ecc = emif_regs->NANDF2ECC;
141 else if (region == 3)
142 ecc = emif_regs->NANDF3ECC;
143 else if (region == 4)
144 ecc = emif_regs->NANDF4ECC;
149 static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
152 #ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
154 * This is not how you should read ECCs on large page Davinci devices.
155 * The region parameter gets you ECCs for flash chips on different chip
156 * selects, not the 4x512 byte pages in a 2048 byte page.
158 * Preserved for backwards compatibility though.
162 struct nand_chip *this = mtd->priv;
164 n = (this->ecc.size/512);
168 tmp = nand_davinci_readecc(mtd, region);
170 *ecc_code++ = tmp >> 16;
171 *ecc_code++ = ((tmp >> 8) & 0x0f) | ((tmp >> 20) & 0xf0);
175 const int region = 1;
177 tmp = nand_davinci_readecc(mtd, region);
179 /* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
180 * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
181 tmp = (tmp & 0x00000fff) | ((tmp & 0x0fff0000) >> 4);
183 /* Invert so that erased block ECC is correct */
187 *ecc_code++ = tmp >> 8;
188 *ecc_code++ = tmp >> 16;
189 #endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
193 #ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
194 static void nand_davinci_gen_true_ecc(u_int8_t *ecc_buf)
196 u_int32_t tmp = ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xf0) << 20) | ((ecc_buf[2] & 0x0f) << 8);
198 ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) | P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
199 ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) | P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
200 ecc_buf[2] = ~( P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) | P1e(tmp) | P2048o(tmp) | P2048e(tmp));
203 static int nand_davinci_compare_ecc(u_int8_t *ecc_nand, u_int8_t *ecc_calc, u_int8_t *page_data)
206 u_int8_t tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
207 u_int8_t comp0_bit[8], comp1_bit[8], comp2_bit[8];
208 u_int8_t ecc_bit[24];
209 u_int8_t ecc_sum = 0;
210 u_int8_t find_bit = 0;
211 u_int32_t find_byte = 0;
214 is_ecc_ff = ((*ecc_nand == 0xff) && (*(ecc_nand + 1) == 0xff) && (*(ecc_nand + 2) == 0xff));
216 nand_davinci_gen_true_ecc(ecc_nand);
217 nand_davinci_gen_true_ecc(ecc_calc);
219 for (i = 0; i <= 2; i++) {
220 *(ecc_nand + i) = ~(*(ecc_nand + i));
221 *(ecc_calc + i) = ~(*(ecc_calc + i));
224 for (i = 0; i < 8; i++) {
225 tmp0_bit[i] = *ecc_nand % 2;
226 *ecc_nand = *ecc_nand / 2;
229 for (i = 0; i < 8; i++) {
230 tmp1_bit[i] = *(ecc_nand + 1) % 2;
231 *(ecc_nand + 1) = *(ecc_nand + 1) / 2;
234 for (i = 0; i < 8; i++) {
235 tmp2_bit[i] = *(ecc_nand + 2) % 2;
236 *(ecc_nand + 2) = *(ecc_nand + 2) / 2;
239 for (i = 0; i < 8; i++) {
240 comp0_bit[i] = *ecc_calc % 2;
241 *ecc_calc = *ecc_calc / 2;
244 for (i = 0; i < 8; i++) {
245 comp1_bit[i] = *(ecc_calc + 1) % 2;
246 *(ecc_calc + 1) = *(ecc_calc + 1) / 2;
249 for (i = 0; i < 8; i++) {
250 comp2_bit[i] = *(ecc_calc + 2) % 2;
251 *(ecc_calc + 2) = *(ecc_calc + 2) / 2;
254 for (i = 0; i< 6; i++)
255 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
257 for (i = 0; i < 8; i++)
258 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
260 for (i = 0; i < 8; i++)
261 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
263 ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
264 ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
266 for (i = 0; i < 24; i++)
267 ecc_sum += ecc_bit[i];
271 /* Not reached because this function is not called if
272 ECC values are equal */
275 /* Uncorrectable error */
276 MTDDEBUG (MTD_DEBUG_LEVEL0,
277 "ECC UNCORRECTED_ERROR 1\n");
280 /* Correctable error */
281 find_byte = (ecc_bit[23] << 8) +
291 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
293 MTDDEBUG (MTD_DEBUG_LEVEL0, "Correcting single bit ECC "
294 "error at offset: %d, bit: %d\n",
295 find_byte, find_bit);
297 page_data[find_byte] ^= (1 << find_bit);
302 if (ecc_calc[0] == 0 && ecc_calc[1] == 0 && ecc_calc[2] == 0)
305 MTDDEBUG (MTD_DEBUG_LEVEL0,
306 "UNCORRECTED_ERROR default\n");
310 #endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
312 static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc)
314 struct nand_chip *this = mtd->priv;
315 #ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
316 int block_count = 0, i, rc;
318 block_count = (this->ecc.size/512);
319 for (i = 0; i < block_count; i++) {
320 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
321 rc = nand_davinci_compare_ecc(read_ecc, calc_ecc, dat);
331 u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) |
333 u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) |
335 u_int32_t diff = ecc_calc ^ ecc_nand;
338 if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
339 /* Correctable error */
340 if ((diff >> (12 + 3)) < this->ecc.size) {
341 uint8_t find_bit = 1 << ((diff >> 12) & 7);
342 uint32_t find_byte = diff >> (12 + 3);
344 dat[find_byte] ^= find_bit;
345 MTDDEBUG(MTD_DEBUG_LEVEL0, "Correcting single "
346 "bit ECC error at offset: %d, bit: "
347 "%d\n", find_byte, find_bit);
352 } else if (!(diff & (diff - 1))) {
353 /* Single bit ECC error in the ECC itself,
355 MTDDEBUG(MTD_DEBUG_LEVEL0, "Single bit ECC error in "
359 /* Uncorrectable error */
360 MTDDEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
364 #endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
367 #endif /* CONFIG_SYS_NAND_HW_ECC */
369 static int nand_davinci_dev_ready(struct mtd_info *mtd)
371 return emif_regs->NANDFSR & 0x1;
374 static void nand_flash_init(void)
376 /* This is for DM6446 EVM and *very* similar. DO NOT GROW THIS!
377 * Instead, have your board_init() set EMIF timings, based on its
378 * knowledge of the clocks and what devices are hooked up ... and
379 * don't even do that unless no UBL handled it.
381 #ifdef CONFIG_SOC_DM6446
382 u_int32_t acfg1 = 0x3ffffffc;
384 /*------------------------------------------------------------------*
385 * NAND FLASH CHIP TIMEOUT @ 459 MHz *
387 * AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz *
388 * AEMIF.CLK period = 1/76.5 MHz = 13.1 ns *
390 *------------------------------------------------------------------*/
392 | (0 << 31 ) /* selectStrobe */
393 | (0 << 30 ) /* extWait */
394 | (1 << 26 ) /* writeSetup 10 ns */
395 | (3 << 20 ) /* writeStrobe 40 ns */
396 | (1 << 17 ) /* writeHold 10 ns */
397 | (1 << 13 ) /* readSetup 10 ns */
398 | (5 << 7 ) /* readStrobe 60 ns */
399 | (1 << 4 ) /* readHold 10 ns */
400 | (3 << 2 ) /* turnAround ?? ns */
401 | (0 << 0 ) /* asyncSize 8-bit bus */
404 emif_regs->AB1CR = acfg1; /* CS2 */
406 emif_regs->NANDFCR = 0x00000101; /* NAND flash on CS2 */
410 int board_nand_init(struct nand_chip *nand)
412 nand->chip_delay = 0;
413 nand->select_chip = nand_davinci_select_chip;
414 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
415 nand->options = NAND_USE_FLASH_BBT;
417 #ifdef CONFIG_SYS_NAND_HW_ECC
418 nand->ecc.mode = NAND_ECC_HW;
419 #ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
420 nand->ecc.layout = &davinci_nand_ecclayout;
421 #ifdef CONFIG_SYS_NAND_LARGEPAGE
422 nand->ecc.size = 2048;
423 nand->ecc.bytes = 12;
424 #elif defined(CONFIG_SYS_NAND_SMALLPAGE)
425 nand->ecc.size = 512;
428 #error "Either CONFIG_SYS_NAND_LARGEPAGE or CONFIG_SYS_NAND_SMALLPAGE must be defined!"
431 nand->ecc.size = 512;
433 #endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
434 nand->ecc.calculate = nand_davinci_calculate_ecc;
435 nand->ecc.correct = nand_davinci_correct_data;
436 nand->ecc.hwctl = nand_davinci_enable_hwecc;
438 nand->ecc.mode = NAND_ECC_SOFT;
439 #endif /* CONFIG_SYS_NAND_HW_ECC */
441 /* Set address of hardware control function */
442 nand->cmd_ctrl = nand_davinci_hwcontrol;
444 nand->dev_ready = nand_davinci_dev_ready;