2 * NAND driver for TI DaVinci based boards.
4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6 * Based on Linux DaVinci NAND driver by TI. Original copyright follows:
11 * linux/drivers/mtd/nand/nand_davinci.c
15 * Copyright (C) 2006 Texas Instruments.
17 * ----------------------------------------------------------------------------
19 * SPDX-License-Identifier: GPL-2.0+
21 * ----------------------------------------------------------------------------
24 * This is a device driver for the NAND flash device found on the
25 * DaVinci board which utilizes the Samsung k9k2g08 part.
28 ver. 1.0: Feb 2005, Vinod/Sudhakar
35 #include <asm/arch/nand_defs.h>
36 #include <asm/arch/emif_defs.h>
38 /* Definitions for 4-bit hardware ECC */
39 #define NAND_TIMEOUT 10240
40 #define NAND_ECC_BUSY 0xC
41 #define NAND_4BITECC_MASK 0x03FF03FF
42 #define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00
43 #define ECC_STATE_NO_ERR 0x0
44 #define ECC_STATE_TOO_MANY_ERRS 0x1
45 #define ECC_STATE_ERR_CORR_COMP_P 0x2
46 #define ECC_STATE_ERR_CORR_COMP_N 0x3
49 * Exploit the little endianness of the ARM to do multi-byte transfers
50 * per device read. This can perform over twice as quickly as individual
51 * byte transfers when buffer alignment is conducive.
53 * NOTE: This only works if the NAND is not connected to the 2 LSBs of
54 * the address bus. On Davinci EVM platforms this has always been true.
56 static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
58 struct nand_chip *chip = mtd->priv;
59 const u32 *nand = chip->IO_ADDR_R;
61 /* Make sure that buf is 32 bit aligned */
62 if (((int)buf & 0x3) != 0) {
63 if (((int)buf & 0x1) != 0) {
71 if (((int)buf & 0x3) != 0) {
73 *(u16 *)buf = readw(nand);
80 /* copy aligned data */
82 *(u32 *)buf = __raw_readl(nand);
87 /* mop up any remaining bytes */
90 *(u16 *)buf = readw(nand);
100 static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf,
103 struct nand_chip *chip = mtd->priv;
104 const u32 *nand = chip->IO_ADDR_W;
106 /* Make sure that buf is 32 bit aligned */
107 if (((int)buf & 0x3) != 0) {
108 if (((int)buf & 0x1) != 0) {
116 if (((int)buf & 0x3) != 0) {
118 writew(*(u16 *)buf, nand);
125 /* copy aligned data */
127 __raw_writel(*(u32 *)buf, nand);
132 /* mop up any remaining bytes */
135 writew(*(u16 *)buf, nand);
145 static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
148 struct nand_chip *this = mtd->priv;
149 u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
151 if (ctrl & NAND_CTRL_CHANGE) {
152 IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
155 IO_ADDR_W |= MASK_CLE;
157 IO_ADDR_W |= MASK_ALE;
158 this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
161 if (cmd != NAND_CMD_NONE)
162 writeb(cmd, IO_ADDR_W);
165 #ifdef CONFIG_SYS_NAND_HW_ECC
167 static u_int32_t nand_davinci_readecc(struct mtd_info *mtd)
171 ecc = __raw_readl(&(davinci_emif_regs->nandfecc[
172 CONFIG_SYS_NAND_CS - 2]));
177 static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
181 /* reading the ECC result register resets the ECC calculation */
182 nand_davinci_readecc(mtd);
184 val = __raw_readl(&davinci_emif_regs->nandfcr);
185 val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
186 val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
187 __raw_writel(val, &davinci_emif_regs->nandfcr);
190 static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
195 tmp = nand_davinci_readecc(mtd);
197 /* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
198 * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
199 tmp = (tmp & 0x00000fff) | ((tmp & 0x0fff0000) >> 4);
201 /* Invert so that erased block ECC is correct */
205 *ecc_code++ = tmp >> 8;
206 *ecc_code++ = tmp >> 16;
208 /* NOTE: the above code matches mainline Linux:
209 * .PQR.stu ==> ~PQRstu
211 * MontaVista/TI kernels encode those bytes differently, use
212 * complicated (and allegedly sometimes-wrong) correction code,
213 * and usually shipped with U-Boot that uses software ECC:
214 * .PQR.stu ==> PsQRtu
216 * If you need MV/TI compatible NAND I/O in U-Boot, it should
217 * be possible to (a) change the mangling above, (b) reverse
218 * that mangling in nand_davinci_correct_data() below.
224 static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat,
225 u_char *read_ecc, u_char *calc_ecc)
227 struct nand_chip *this = mtd->priv;
228 u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) |
230 u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) |
232 u_int32_t diff = ecc_calc ^ ecc_nand;
235 if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
236 /* Correctable error */
237 if ((diff >> (12 + 3)) < this->ecc.size) {
238 uint8_t find_bit = 1 << ((diff >> 12) & 7);
239 uint32_t find_byte = diff >> (12 + 3);
241 dat[find_byte] ^= find_bit;
242 MTDDEBUG(MTD_DEBUG_LEVEL0, "Correcting single "
243 "bit ECC error at offset: %d, bit: "
244 "%d\n", find_byte, find_bit);
249 } else if (!(diff & (diff - 1))) {
250 /* Single bit ECC error in the ECC itself,
252 MTDDEBUG(MTD_DEBUG_LEVEL0, "Single bit ECC error in "
256 /* Uncorrectable error */
257 MTDDEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
263 #endif /* CONFIG_SYS_NAND_HW_ECC */
265 #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
266 static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = {
267 #if defined(CONFIG_SYS_NAND_PAGE_2K)
271 29, 30, 31, 32, 33, 34, 35, 36, 37, 38,
272 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
273 49, 50, 51, 52, 53, 54, 55, 56, 57, 58,
277 {.offset = 2, .length = 22, },
279 #elif defined(CONFIG_SYS_NAND_PAGE_4K)
282 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
283 58, 59, 60, 61, 62, 63, 64, 65, 66, 67,
284 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
285 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,
286 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
287 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
288 108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
289 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
292 {.offset = 2, .length = 46, },
297 static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
305 * Start a new ECC calculation for reading or writing 512 bytes
308 val = __raw_readl(&davinci_emif_regs->nandfcr);
309 val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
310 val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
311 val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
312 val |= DAVINCI_NANDFCR_4BIT_ECC_START;
313 __raw_writel(val, &davinci_emif_regs->nandfcr);
315 case NAND_ECC_READSYN:
316 val = __raw_readl(&davinci_emif_regs->nand4bitecc[0]);
323 static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4])
327 for (i = 0; i < 4; i++) {
328 ecc[i] = __raw_readl(&davinci_emif_regs->nand4bitecc[i]) &
335 static int nand_davinci_4bit_calculate_ecc(struct mtd_info *mtd,
339 unsigned int hw_4ecc[4];
342 nand_davinci_4bit_readecc(mtd, hw_4ecc);
344 /*Convert 10 bit ecc value to 8 bit */
345 for (i = 0; i < 2; i++) {
346 unsigned int hw_ecc_low = hw_4ecc[i * 2];
347 unsigned int hw_ecc_hi = hw_4ecc[(i * 2) + 1];
349 /* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */
350 *ecc_code++ = hw_ecc_low & 0xFF;
353 * Take 2 bits as LSB bits from val1 (count1=0) or val5
354 * (count1=1) and 6 bits from val2 (count1=0) or
358 ((hw_ecc_low >> 8) & 0x3) | ((hw_ecc_low >> 14) & 0xFC);
361 * Take 4 bits from val2 (count1=0) or val5 (count1=1) and
362 * 4 bits from val3 (count1=0) or val6 (count1=1)
365 ((hw_ecc_low >> 22) & 0xF) | ((hw_ecc_hi << 4) & 0xF0);
368 * Take 6 bits from val3(count1=0) or val6 (count1=1) and
369 * 2 bits from val4 (count1=0) or val7 (count1=1)
372 ((hw_ecc_hi >> 4) & 0x3F) | ((hw_ecc_hi >> 10) & 0xC0);
374 /* Take 8 bits from val4 (count1=0) or val7 (count1=1) */
375 *ecc_code++ = (hw_ecc_hi >> 18) & 0xFF;
381 static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
382 uint8_t *read_ecc, uint8_t *calc_ecc)
385 unsigned int hw_4ecc[4];
386 unsigned int iserror;
387 unsigned short *ecc16;
388 unsigned int numerrors, erroraddress, errorvalue;
392 * Check for an ECC where all bytes are 0xFF. If this is the case, we
393 * will assume we are looking at an erased page and we should ignore
396 for (i = 0; i < 10; i++) {
397 if (read_ecc[i] != 0xFF)
403 /* Convert 8 bit in to 10 bit */
404 ecc16 = (unsigned short *)&read_ecc[0];
407 * Write the parity values in the NAND Flash 4-bit ECC Load register.
408 * Write each parity value one at a time starting from 4bit_ecc_val8
412 /*Take 2 bits from 8th byte and 8 bits from 9th byte */
413 __raw_writel(((ecc16[4]) >> 6) & 0x3FF,
414 &davinci_emif_regs->nand4biteccload);
416 /* Take 4 bits from 7th byte and 6 bits from 8th byte */
417 __raw_writel((((ecc16[3]) >> 12) & 0xF) | ((((ecc16[4])) << 4) & 0x3F0),
418 &davinci_emif_regs->nand4biteccload);
420 /* Take 6 bits from 6th byte and 4 bits from 7th byte */
421 __raw_writel((ecc16[3] >> 2) & 0x3FF,
422 &davinci_emif_regs->nand4biteccload);
424 /* Take 8 bits from 5th byte and 2 bits from 6th byte */
425 __raw_writel(((ecc16[2]) >> 8) | ((((ecc16[3])) << 8) & 0x300),
426 &davinci_emif_regs->nand4biteccload);
428 /*Take 2 bits from 3rd byte and 8 bits from 4th byte */
429 __raw_writel((((ecc16[1]) >> 14) & 0x3) | ((((ecc16[2])) << 2) & 0x3FC),
430 &davinci_emif_regs->nand4biteccload);
432 /* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
433 __raw_writel(((ecc16[1]) >> 4) & 0x3FF,
434 &davinci_emif_regs->nand4biteccload);
436 /* Take 6 bits from 1st byte and 4 bits from 2nd byte */
437 __raw_writel((((ecc16[0]) >> 10) & 0x3F) | (((ecc16[1]) << 6) & 0x3C0),
438 &davinci_emif_regs->nand4biteccload);
440 /* Take 10 bits from 0th and 1st bytes */
441 __raw_writel((ecc16[0]) & 0x3FF,
442 &davinci_emif_regs->nand4biteccload);
445 * Perform a dummy read to the EMIF Revision Code and Status register.
446 * This is required to ensure time for syndrome calculation after
447 * writing the ECC values in previous step.
450 val = __raw_readl(&davinci_emif_regs->nandfsr);
453 * Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers.
454 * A syndrome value of 0 means no bit errors. If the syndrome is
455 * non-zero then go further otherwise return.
457 nand_davinci_4bit_readecc(mtd, hw_4ecc);
459 if (!(hw_4ecc[0] | hw_4ecc[1] | hw_4ecc[2] | hw_4ecc[3]))
463 * Clear any previous address calculation by doing a dummy read of an
464 * error address register.
466 val = __raw_readl(&davinci_emif_regs->nanderradd1);
469 * Set the addr_calc_st bit(bit no 13) in the NAND Flash Control
472 __raw_writel(DAVINCI_NANDFCR_4BIT_CALC_START,
473 &davinci_emif_regs->nandfcr);
476 * Wait for the corr_state field (bits 8 to 11) in the
477 * NAND Flash Status register to be not equal to 0x0, 0x1, 0x2, or 0x3.
478 * Otherwise ECC calculation has not even begun and the next loop might
479 * fail because of a false positive!
483 val = __raw_readl(&davinci_emif_regs->nandfsr);
486 } while ((i > 0) && !val);
489 * Wait for the corr_state field (bits 8 to 11) in the
490 * NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3.
494 val = __raw_readl(&davinci_emif_regs->nandfsr);
497 } while ((i > 0) && val);
499 iserror = __raw_readl(&davinci_emif_regs->nandfsr);
500 iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
501 iserror = iserror >> 8;
504 * ECC_STATE_TOO_MANY_ERRS (0x1) means errors cannot be
505 * corrected (five or more errors). The number of errors
506 * calculated (err_num field) differs from the number of errors
507 * searched. ECC_STATE_ERR_CORR_COMP_P (0x2) means error
508 * correction complete (errors on bit 8 or 9).
509 * ECC_STATE_ERR_CORR_COMP_N (0x3) means error correction
510 * complete (error exists).
513 if (iserror == ECC_STATE_NO_ERR) {
514 val = __raw_readl(&davinci_emif_regs->nanderrval1);
516 } else if (iserror == ECC_STATE_TOO_MANY_ERRS) {
517 val = __raw_readl(&davinci_emif_regs->nanderrval1);
521 numerrors = ((__raw_readl(&davinci_emif_regs->nandfsr) >> 16)
524 /* Read the error address, error value and correct */
525 for (i = 0; i < numerrors; i++) {
528 ((__raw_readl(&davinci_emif_regs->nanderradd2) >>
529 (16 * (i & 1))) & 0x3FF);
530 erroraddress = ((512 + 7) - erroraddress);
532 ((__raw_readl(&davinci_emif_regs->nanderrval2) >>
533 (16 * (i & 1))) & 0xFF);
536 ((__raw_readl(&davinci_emif_regs->nanderradd1) >>
537 (16 * (i & 1))) & 0x3FF);
538 erroraddress = ((512 + 7) - erroraddress);
540 ((__raw_readl(&davinci_emif_regs->nanderrval1) >>
541 (16 * (i & 1))) & 0xFF);
543 /* xor the corrupt data with error value */
544 if (erroraddress < 512)
545 dat[erroraddress] ^= errorvalue;
550 #endif /* CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST */
552 static int nand_davinci_dev_ready(struct mtd_info *mtd)
554 return __raw_readl(&davinci_emif_regs->nandfsr) & 0x1;
557 static void nand_flash_init(void)
559 /* This is for DM6446 EVM and *very* similar. DO NOT GROW THIS!
560 * Instead, have your board_init() set EMIF timings, based on its
561 * knowledge of the clocks and what devices are hooked up ... and
562 * don't even do that unless no UBL handled it.
564 #ifdef CONFIG_SOC_DM644X
565 u_int32_t acfg1 = 0x3ffffffc;
567 /*------------------------------------------------------------------*
568 * NAND FLASH CHIP TIMEOUT @ 459 MHz *
570 * AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz *
571 * AEMIF.CLK period = 1/76.5 MHz = 13.1 ns *
573 *------------------------------------------------------------------*/
575 | (0 << 31) /* selectStrobe */
576 | (0 << 30) /* extWait */
577 | (1 << 26) /* writeSetup 10 ns */
578 | (3 << 20) /* writeStrobe 40 ns */
579 | (1 << 17) /* writeHold 10 ns */
580 | (1 << 13) /* readSetup 10 ns */
581 | (5 << 7) /* readStrobe 60 ns */
582 | (1 << 4) /* readHold 10 ns */
583 | (3 << 2) /* turnAround ?? ns */
584 | (0 << 0) /* asyncSize 8-bit bus */
587 __raw_writel(acfg1, &davinci_emif_regs->ab1cr); /* CS2 */
589 /* NAND flash on CS2 */
590 __raw_writel(0x00000101, &davinci_emif_regs->nandfcr);
594 void davinci_nand_init(struct nand_chip *nand)
596 nand->chip_delay = 0;
597 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
598 nand->bbt_options |= NAND_BBT_USE_FLASH;
600 #ifdef CONFIG_SYS_NAND_HW_ECC
601 nand->ecc.mode = NAND_ECC_HW;
602 nand->ecc.size = 512;
604 nand->ecc.strength = 1;
605 nand->ecc.calculate = nand_davinci_calculate_ecc;
606 nand->ecc.correct = nand_davinci_correct_data;
607 nand->ecc.hwctl = nand_davinci_enable_hwecc;
609 nand->ecc.mode = NAND_ECC_SOFT;
610 #endif /* CONFIG_SYS_NAND_HW_ECC */
611 #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
612 nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
613 nand->ecc.size = 512;
614 nand->ecc.bytes = 10;
615 nand->ecc.strength = 4;
616 nand->ecc.calculate = nand_davinci_4bit_calculate_ecc;
617 nand->ecc.correct = nand_davinci_4bit_correct_data;
618 nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc;
619 nand->ecc.layout = &nand_davinci_4bit_layout_oobfirst;
621 /* Set address of hardware control function */
622 nand->cmd_ctrl = nand_davinci_hwcontrol;
624 nand->read_buf = nand_davinci_read_buf;
625 nand->write_buf = nand_davinci_write_buf;
627 nand->dev_ready = nand_davinci_dev_ready;
632 int board_nand_init(struct nand_chip *chip) __attribute__((weak));
634 int board_nand_init(struct nand_chip *chip)
636 davinci_nand_init(chip);