git.sur5r.net Git - u-boot/blob - drivers/mtd/nand/denali.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2013-2014 Altera Corporation <www.altera.com>
   4  * Copyright (C) 2009-2010, Intel Corporation and its suppliers.
   5  */
   6
   7 #ifndef __DENALI_H__
   8 #define __DENALI_H__
   9
  10 #include <linux/bitops.h>
  11 #include <linux/mtd/rawnand.h>
  12 #include <linux/types.h>
  13
  14 #define DEVICE_RESET                            0x0
  15 #define     DEVICE_RESET__BANK(bank)                    BIT(bank)
  16
  17 #define TRANSFER_SPARE_REG                      0x10
  18 #define     TRANSFER_SPARE_REG__FLAG                    BIT(0)
  19
  20 #define LOAD_WAIT_CNT                           0x20
  21 #define     LOAD_WAIT_CNT__VALUE                        GENMASK(15, 0)
  22
  23 #define PROGRAM_WAIT_CNT                        0x30
  24 #define     PROGRAM_WAIT_CNT__VALUE                     GENMASK(15, 0)
  25
  26 #define ERASE_WAIT_CNT                          0x40
  27 #define     ERASE_WAIT_CNT__VALUE                       GENMASK(15, 0)
  28
  29 #define INT_MON_CYCCNT                          0x50
  30 #define     INT_MON_CYCCNT__VALUE                       GENMASK(15, 0)
  31
  32 #define RB_PIN_ENABLED                          0x60
  33 #define     RB_PIN_ENABLED__BANK(bank)                  BIT(bank)
  34
  35 #define MULTIPLANE_OPERATION                    0x70
  36 #define     MULTIPLANE_OPERATION__FLAG                  BIT(0)
  37
  38 #define MULTIPLANE_READ_ENABLE                  0x80
  39 #define     MULTIPLANE_READ_ENABLE__FLAG                BIT(0)
  40
  41 #define COPYBACK_DISABLE                        0x90
  42 #define     COPYBACK_DISABLE__FLAG                      BIT(0)
  43
  44 #define CACHE_WRITE_ENABLE                      0xa0
  45 #define     CACHE_WRITE_ENABLE__FLAG                    BIT(0)
  46
  47 #define CACHE_READ_ENABLE                       0xb0
  48 #define     CACHE_READ_ENABLE__FLAG                     BIT(0)
  49
  50 #define PREFETCH_MODE                           0xc0
  51 #define     PREFETCH_MODE__PREFETCH_EN                  BIT(0)
  52 #define     PREFETCH_MODE__PREFETCH_BURST_LENGTH        GENMASK(15, 4)
  53
  54 #define CHIP_ENABLE_DONT_CARE                   0xd0
  55 #define     CHIP_EN_DONT_CARE__FLAG                     BIT(0)
  56
  57 #define ECC_ENABLE                              0xe0
  58 #define     ECC_ENABLE__FLAG                            BIT(0)
  59
  60 #define GLOBAL_INT_ENABLE                       0xf0
  61 #define     GLOBAL_INT_EN_FLAG                          BIT(0)
  62
  63 #define TWHR2_AND_WE_2_RE                       0x100
  64 #define     TWHR2_AND_WE_2_RE__WE_2_RE                  GENMASK(5, 0)
  65 #define     TWHR2_AND_WE_2_RE__TWHR2                    GENMASK(13, 8)
  66
  67 #define TCWAW_AND_ADDR_2_DATA                   0x110
  68 /* The width of ADDR_2_DATA is 6 bit for old IP, 7 bit for new IP */
  69 #define     TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA          GENMASK(6, 0)
  70 #define     TCWAW_AND_ADDR_2_DATA__TCWAW                GENMASK(13, 8)
  71
  72 #define RE_2_WE                                 0x120
  73 #define     RE_2_WE__VALUE                              GENMASK(5, 0)
  74
  75 #define ACC_CLKS                                0x130
  76 #define     ACC_CLKS__VALUE                             GENMASK(3, 0)
  77
  78 #define NUMBER_OF_PLANES                        0x140
  79 #define     NUMBER_OF_PLANES__VALUE                     GENMASK(2, 0)
  80
  81 #define PAGES_PER_BLOCK                         0x150
  82 #define     PAGES_PER_BLOCK__VALUE                      GENMASK(15, 0)
  83
  84 #define DEVICE_WIDTH                            0x160
  85 #define     DEVICE_WIDTH__VALUE                         GENMASK(1, 0)
  86
  87 #define DEVICE_MAIN_AREA_SIZE                   0x170
  88 #define     DEVICE_MAIN_AREA_SIZE__VALUE                GENMASK(15, 0)
  89
  90 #define DEVICE_SPARE_AREA_SIZE                  0x180
  91 #define     DEVICE_SPARE_AREA_SIZE__VALUE               GENMASK(15, 0)
  92
  93 #define TWO_ROW_ADDR_CYCLES                     0x190
  94 #define     TWO_ROW_ADDR_CYCLES__FLAG                   BIT(0)
  95
  96 #define MULTIPLANE_ADDR_RESTRICT                0x1a0
  97 #define     MULTIPLANE_ADDR_RESTRICT__FLAG              BIT(0)
  98
  99 #define ECC_CORRECTION                          0x1b0
 100 #define     ECC_CORRECTION__VALUE                       GENMASK(4, 0)
 101 #define     ECC_CORRECTION__ERASE_THRESHOLD             GENMASK(31, 16)
 102
 103 #define READ_MODE                               0x1c0
 104 #define     READ_MODE__VALUE                            GENMASK(3, 0)
 105
 106 #define WRITE_MODE                              0x1d0
 107 #define     WRITE_MODE__VALUE                           GENMASK(3, 0)
 108
 109 #define COPYBACK_MODE                           0x1e0
 110 #define     COPYBACK_MODE__VALUE                        GENMASK(3, 0)
 111
 112 #define RDWR_EN_LO_CNT                          0x1f0
 113 #define     RDWR_EN_LO_CNT__VALUE                       GENMASK(4, 0)
 114
 115 #define RDWR_EN_HI_CNT                          0x200
 116 #define     RDWR_EN_HI_CNT__VALUE                       GENMASK(4, 0)
 117
 118 #define MAX_RD_DELAY                            0x210
 119 #define     MAX_RD_DELAY__VALUE                         GENMASK(3, 0)
 120
 121 #define CS_SETUP_CNT                            0x220
 122 #define     CS_SETUP_CNT__VALUE                         GENMASK(4, 0)
 123 #define     CS_SETUP_CNT__TWB                           GENMASK(17, 12)
 124
 125 #define SPARE_AREA_SKIP_BYTES                   0x230
 126 #define     SPARE_AREA_SKIP_BYTES__VALUE                GENMASK(5, 0)
 127
 128 #define SPARE_AREA_MARKER                       0x240
 129 #define     SPARE_AREA_MARKER__VALUE                    GENMASK(15, 0)
 130
 131 #define DEVICES_CONNECTED                       0x250
 132 #define     DEVICES_CONNECTED__VALUE                    GENMASK(2, 0)
 133
 134 #define DIE_MASK                                0x260
 135 #define     DIE_MASK__VALUE                             GENMASK(7, 0)
 136
 137 #define FIRST_BLOCK_OF_NEXT_PLANE               0x270
 138 #define     FIRST_BLOCK_OF_NEXT_PLANE__VALUE            GENMASK(15, 0)
 139
 140 #define WRITE_PROTECT                           0x280
 141 #define     WRITE_PROTECT__FLAG                         BIT(0)
 142
 143 #define RE_2_RE                                 0x290
 144 #define     RE_2_RE__VALUE                              GENMASK(5, 0)
 145
 146 #define MANUFACTURER_ID                         0x300
 147 #define     MANUFACTURER_ID__VALUE                      GENMASK(7, 0)
 148
 149 #define DEVICE_ID                               0x310
 150 #define     DEVICE_ID__VALUE                            GENMASK(7, 0)
 151
 152 #define DEVICE_PARAM_0                          0x320
 153 #define     DEVICE_PARAM_0__VALUE                       GENMASK(7, 0)
 154
 155 #define DEVICE_PARAM_1                          0x330
 156 #define     DEVICE_PARAM_1__VALUE                       GENMASK(7, 0)
 157
 158 #define DEVICE_PARAM_2                          0x340
 159 #define     DEVICE_PARAM_2__VALUE                       GENMASK(7, 0)
 160
 161 #define LOGICAL_PAGE_DATA_SIZE                  0x350
 162 #define     LOGICAL_PAGE_DATA_SIZE__VALUE               GENMASK(15, 0)
 163
 164 #define LOGICAL_PAGE_SPARE_SIZE                 0x360
 165 #define     LOGICAL_PAGE_SPARE_SIZE__VALUE              GENMASK(15, 0)
 166
 167 #define REVISION                                0x370
 168 #define     REVISION__VALUE                             GENMASK(15, 0)
 169
 170 #define ONFI_DEVICE_FEATURES                    0x380
 171 #define     ONFI_DEVICE_FEATURES__VALUE                 GENMASK(5, 0)
 172
 173 #define ONFI_OPTIONAL_COMMANDS                  0x390
 174 #define     ONFI_OPTIONAL_COMMANDS__VALUE               GENMASK(5, 0)
 175
 176 #define ONFI_TIMING_MODE                        0x3a0
 177 #define     ONFI_TIMING_MODE__VALUE                     GENMASK(5, 0)
 178
 179 #define ONFI_PGM_CACHE_TIMING_MODE              0x3b0
 180 #define     ONFI_PGM_CACHE_TIMING_MODE__VALUE           GENMASK(5, 0)
 181
 182 #define ONFI_DEVICE_NO_OF_LUNS                  0x3c0
 183 #define     ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS          GENMASK(7, 0)
 184 #define     ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE         BIT(8)
 185
 186 #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L      0x3d0
 187 #define     ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE   GENMASK(15, 0)
 188
 189 #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U      0x3e0
 190 #define     ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE   GENMASK(15, 0)
 191
 192 #define FEATURES                                0x3f0
 193 #define     FEATURES__N_BANKS                           GENMASK(1, 0)
 194 #define     FEATURES__ECC_MAX_ERR                       GENMASK(5, 2)
 195 #define     FEATURES__DMA                               BIT(6)
 196 #define     FEATURES__CMD_DMA                           BIT(7)
 197 #define     FEATURES__PARTITION                         BIT(8)
 198 #define     FEATURES__XDMA_SIDEBAND                     BIT(9)
 199 #define     FEATURES__GPREG                             BIT(10)
 200 #define     FEATURES__INDEX_ADDR                        BIT(11)
 201
 202 #define TRANSFER_MODE                           0x400
 203 #define     TRANSFER_MODE__VALUE                        GENMASK(1, 0)
 204
 205 #define INTR_STATUS(bank)                       (0x410 + (bank) * 0x50)
 206 #define INTR_EN(bank)                           (0x420 + (bank) * 0x50)
 207 /* bit[1:0] is used differently depending on IP version */
 208 #define     INTR__ECC_UNCOR_ERR                         BIT(0)  /* new IP */
 209 #define     INTR__ECC_TRANSACTION_DONE                  BIT(0)  /* old IP */
 210 #define     INTR__ECC_ERR                               BIT(1)  /* old IP */
 211 #define     INTR__DMA_CMD_COMP                          BIT(2)
 212 #define     INTR__TIME_OUT                              BIT(3)
 213 #define     INTR__PROGRAM_FAIL                          BIT(4)
 214 #define     INTR__ERASE_FAIL                            BIT(5)
 215 #define     INTR__LOAD_COMP                             BIT(6)
 216 #define     INTR__PROGRAM_COMP                          BIT(7)
 217 #define     INTR__ERASE_COMP                            BIT(8)
 218 #define     INTR__PIPE_CPYBCK_CMD_COMP                  BIT(9)
 219 #define     INTR__LOCKED_BLK                            BIT(10)
 220 #define     INTR__UNSUP_CMD                             BIT(11)
 221 #define     INTR__INT_ACT                               BIT(12)
 222 #define     INTR__RST_COMP                              BIT(13)
 223 #define     INTR__PIPE_CMD_ERR                          BIT(14)
 224 #define     INTR__PAGE_XFER_INC                         BIT(15)
 225 #define     INTR__ERASED_PAGE                           BIT(16)
 226
 227 #define PAGE_CNT(bank)                          (0x430 + (bank) * 0x50)
 228 #define ERR_PAGE_ADDR(bank)                     (0x440 + (bank) * 0x50)
 229 #define ERR_BLOCK_ADDR(bank)                    (0x450 + (bank) * 0x50)
 230
 231 #define ECC_THRESHOLD                           0x600
 232 #define     ECC_THRESHOLD__VALUE                        GENMASK(9, 0)
 233
 234 #define ECC_ERROR_BLOCK_ADDRESS                 0x610
 235 #define     ECC_ERROR_BLOCK_ADDRESS__VALUE              GENMASK(15, 0)
 236
 237 #define ECC_ERROR_PAGE_ADDRESS                  0x620
 238 #define     ECC_ERROR_PAGE_ADDRESS__VALUE               GENMASK(11, 0)
 239 #define     ECC_ERROR_PAGE_ADDRESS__BANK                GENMASK(15, 12)
 240
 241 #define ECC_ERROR_ADDRESS                       0x630
 242 #define     ECC_ERROR_ADDRESS__OFFSET                   GENMASK(11, 0)
 243 #define     ECC_ERROR_ADDRESS__SECTOR                   GENMASK(15, 12)
 244
 245 #define ERR_CORRECTION_INFO                     0x640
 246 #define     ERR_CORRECTION_INFO__BYTE                   GENMASK(7, 0)
 247 #define     ERR_CORRECTION_INFO__DEVICE                 GENMASK(11, 8)
 248 #define     ERR_CORRECTION_INFO__UNCOR                  BIT(14)
 249 #define     ERR_CORRECTION_INFO__LAST_ERR               BIT(15)
 250
 251 #define ECC_COR_INFO(bank)                      (0x650 + (bank) / 2 * 0x10)
 252 #define     ECC_COR_INFO__SHIFT(bank)                   ((bank) % 2 * 8)
 253 #define     ECC_COR_INFO__MAX_ERRORS                    GENMASK(6, 0)
 254 #define     ECC_COR_INFO__UNCOR_ERR                     BIT(7)
 255
 256 #define CFG_DATA_BLOCK_SIZE                     0x6b0
 257
 258 #define CFG_LAST_DATA_BLOCK_SIZE                0x6c0
 259
 260 #define CFG_NUM_DATA_BLOCKS                     0x6d0
 261
 262 #define CFG_META_DATA_SIZE                      0x6e0
 263
 264 #define DMA_ENABLE                              0x700
 265 #define     DMA_ENABLE__FLAG                            BIT(0)
 266
 267 #define IGNORE_ECC_DONE                         0x710
 268 #define     IGNORE_ECC_DONE__FLAG                       BIT(0)
 269
 270 #define DMA_INTR                                0x720
 271 #define DMA_INTR_EN                             0x730
 272 #define     DMA_INTR__TARGET_ERROR                      BIT(0)
 273 #define     DMA_INTR__DESC_COMP_CHANNEL0                BIT(1)
 274 #define     DMA_INTR__DESC_COMP_CHANNEL1                BIT(2)
 275 #define     DMA_INTR__DESC_COMP_CHANNEL2                BIT(3)
 276 #define     DMA_INTR__DESC_COMP_CHANNEL3                BIT(4)
 277 #define     DMA_INTR__MEMCOPY_DESC_COMP                 BIT(5)
 278
 279 #define TARGET_ERR_ADDR_LO                      0x740
 280 #define     TARGET_ERR_ADDR_LO__VALUE                   GENMASK(15, 0)
 281
 282 #define TARGET_ERR_ADDR_HI                      0x750
 283 #define     TARGET_ERR_ADDR_HI__VALUE                   GENMASK(15, 0)
 284
 285 #define CHNL_ACTIVE                             0x760
 286 #define     CHNL_ACTIVE__CHANNEL0                       BIT(0)
 287 #define     CHNL_ACTIVE__CHANNEL1                       BIT(1)
 288 #define     CHNL_ACTIVE__CHANNEL2                       BIT(2)
 289 #define     CHNL_ACTIVE__CHANNEL3                       BIT(3)
 290
 291 struct udevice;
 292
 293 struct denali_nand_info {
 294         struct nand_chip nand;
 295         unsigned long clk_x_rate;       /* bus interface clock rate */
 296         int active_bank;                /* currently selected bank */
 297         struct udevice *dev;
 298         uint32_t page;
 299         void __iomem *reg;              /* Register Interface */
 300         void __iomem *host;             /* Host Data/Command Interface */
 301         u32 irq_mask;                   /* interrupts we are waiting for */
 302         u32 irq_status;                 /* interrupts that have happened */
 303         int irq;
 304         void *buf;                      /* for syndrome layout conversion */
 305         dma_addr_t dma_addr;
 306         int dma_avail;                  /* can support DMA? */
 307         int devs_per_cs;                /* devices connected in parallel */
 308         int oob_skip_bytes;             /* number of bytes reserved for BBM */
 309         int max_banks;
 310         unsigned int revision;          /* IP revision */
 311         unsigned int caps;              /* IP capability (or quirk) */
 312         const struct nand_ecc_caps *ecc_caps;
 313         u32 (*host_read)(struct denali_nand_info *denali, u32 addr);
 314         void (*host_write)(struct denali_nand_info *denali, u32 addr, u32 data);
 315         void (*setup_dma)(struct denali_nand_info *denali, dma_addr_t dma_addr,
 316                           int page, int write);
 317 };
 318
 319 #define DENALI_CAP_HW_ECC_FIXUP                 BIT(0)
 320 #define DENALI_CAP_DMA_64BIT                    BIT(1)
 321
 322 int denali_calc_ecc_bytes(int step_size, int strength);
 323 int denali_init(struct denali_nand_info *denali);
 324
 325 #endif /* __DENALI_H__ */