2 * Copyright (C) 2014 Panasonic Corporation
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/unaligned.h>
10 #include <linux/mtd/nand.h>
13 #define SPARE_ACCESS 0x41
14 #define MAIN_ACCESS 0x42
15 #define PIPELINE_ACCESS 0x2000
17 #define BANK(x) ((x) << 24)
19 static void __iomem *denali_flash_mem =
20 (void __iomem *)CONFIG_SYS_NAND_DATA_BASE;
21 static void __iomem *denali_flash_reg =
22 (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
24 static const int flash_bank;
25 static uint8_t page_buffer[NAND_MAX_PAGESIZE];
26 static int page_size, oob_size, pages_per_block;
28 static void index_addr(uint32_t address, uint32_t data)
30 writel(address, denali_flash_mem + INDEX_CTRL_REG);
31 writel(data, denali_flash_mem + INDEX_DATA_REG);
34 static int wait_for_irq(uint32_t irq_mask)
36 unsigned long timeout = 1000000;
40 intr_status = readl(denali_flash_reg + INTR_STATUS(flash_bank));
42 if (intr_status & INTR_STATUS__ECC_UNCOR_ERR) {
43 debug("Uncorrected ECC detected\n");
47 if (intr_status & irq_mask)
55 debug("Timeout with interrupt status %08x\n", intr_status);
62 static void read_data_from_flash_mem(uint8_t *buf, int len)
67 /* transfer the data from the flash */
68 buf32 = (uint32_t *)buf;
71 * Let's take care of unaligned access although it rarely happens.
72 * Avoid put_unaligned() for the normal use cases since it leads to
73 * a bit performance regression.
75 if ((unsigned long)buf32 % 4) {
76 for (i = 0; i < len / 4; i++)
77 put_unaligned(readl(denali_flash_mem + INDEX_DATA_REG),
80 for (i = 0; i < len / 4; i++)
81 *buf32++ = readl(denali_flash_mem + INDEX_DATA_REG);
87 tmp = cpu_to_le32(readl(denali_flash_mem + INDEX_DATA_REG));
88 buf = (uint8_t *)buf32;
89 for (i = 0; i < len % 4; i++) {
96 int denali_send_pipeline_cmd(int page, int ecc_en, int access_type)
99 static uint32_t page_count = 1;
101 writel(ecc_en, denali_flash_reg + ECC_ENABLE);
103 /* clear all bits of intr_status. */
104 writel(0xffff, denali_flash_reg + INTR_STATUS(flash_bank));
106 addr = BANK(flash_bank) | page;
108 /* setup the acccess type */
109 cmd = MODE_10 | addr;
110 index_addr(cmd, access_type);
112 /* setup the pipeline command */
113 index_addr(cmd, PIPELINE_ACCESS | page_count);
115 cmd = MODE_01 | addr;
116 writel(cmd, denali_flash_mem + INDEX_CTRL_REG);
118 return wait_for_irq(INTR_STATUS__LOAD_COMP);
121 static int nand_read_oob(void *buf, int page)
125 ret = denali_send_pipeline_cmd(page, 0, SPARE_ACCESS);
129 read_data_from_flash_mem(buf, oob_size);
134 static int nand_read_page(void *buf, int page)
138 ret = denali_send_pipeline_cmd(page, 1, MAIN_ACCESS);
142 read_data_from_flash_mem(buf, page_size);
147 static int nand_block_isbad(int block)
151 ret = nand_read_oob(page_buffer, block * pages_per_block);
155 return page_buffer[CONFIG_SYS_NAND_BAD_BLOCK_POS] != 0xff;
158 /* nand_init() - initialize data to make nand usable by SPL */
161 /* access to main area */
162 writel(0, denali_flash_reg + TRANSFER_SPARE_REG);
165 * These registers are expected to be already set by the hardware
166 * or earlier boot code. So we read these values out.
168 page_size = readl(denali_flash_reg + DEVICE_MAIN_AREA_SIZE);
169 oob_size = readl(denali_flash_reg + DEVICE_SPARE_AREA_SIZE);
170 pages_per_block = readl(denali_flash_reg + PAGES_PER_BLOCK);
173 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
175 int block, page, column, readlen;
177 int force_bad_block_check = 1;
179 page = offs / page_size;
180 column = offs % page_size;
182 block = page / pages_per_block;
183 page = page % pages_per_block;
186 if (force_bad_block_check || page == 0) {
187 ret = nand_block_isbad(block);
197 force_bad_block_check = 0;
199 if (unlikely(column || size < page_size)) {
200 /* Partial page read */
201 ret = nand_read_page(page_buffer,
202 block * pages_per_block + page);
206 readlen = min(page_size - column, size);
207 memcpy(dst, page_buffer, readlen);
211 ret = nand_read_page(dst,
212 block * pages_per_block + page);
222 if (page == pages_per_block) {
231 void nand_deselect(void) {}