2 * SPL driver for Diskonchip G4 nand flash
4 * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
6 * SPDX-License-Identifier: GPL-2.0+
8 * This driver basically mimics the load functionality of a typical IPL (initial
9 * program loader) resident in the 2k NOR-like region of the docg4 that is
10 * mapped to the reset vector. It allows the u-boot SPL to continue loading if
11 * the IPL loads a fixed number of flash blocks that is insufficient to contain
12 * the entire u-boot image. In this case, a concatenated spl + u-boot image is
13 * written at the flash offset from which the IPL loads an image, and when the
14 * IPL jumps to the SPL, the SPL resumes loading where the IPL left off. See
15 * the palmtreo680 for an example.
17 * This driver assumes that the data was written to the flash using the device's
18 * "reliable" mode, and also assumes that each 512 byte page is stored
19 * redundantly in the subsequent page. This storage format is likely to be used
20 * by all boards that boot from the docg4. The format compensates for the lack
23 * Reliable mode reduces the capacity of a block by half, and the redundant
24 * pages reduce it by half again. As a result, the normal 256k capacity of a
25 * block is reduced to 64k for the purposes of the IPL/SPL.
29 #include <linux/mtd/docg4.h>
31 /* forward declarations */
32 static inline void write_nop(void __iomem *docptr);
33 static int poll_status(void __iomem *docptr);
34 static void write_addr(void __iomem *docptr, uint32_t docg4_addr);
35 static void address_sequence(unsigned int g4_page, unsigned int g4_index,
36 void __iomem *docptr);
37 static int docg4_load_block_reliable(uint32_t flash_offset, void *dest_addr);
39 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
41 void *load_addr = dst;
42 uint32_t flash_offset = offs;
43 const unsigned int block_count =
44 (size + DOCG4_BLOCK_CAPACITY_SPL - 1)
45 / DOCG4_BLOCK_CAPACITY_SPL;
48 for (i = 0; i < block_count; i++) {
49 int ret = docg4_load_block_reliable(flash_offset, load_addr);
52 load_addr += DOCG4_BLOCK_CAPACITY_SPL;
53 flash_offset += DOCG4_BLOCK_SIZE;
58 static inline void write_nop(void __iomem *docptr)
60 writew(0, docptr + DOC_NOP);
63 static int poll_status(void __iomem *docptr)
66 * Busy-wait for the FLASHREADY bit to be set in the FLASHCONTROL
67 * register. Operations known to take a long time (e.g., block erase)
68 * should sleep for a while before calling this.
73 /* hardware quirk requires reading twice initially */
74 flash_status = readb(docptr + DOC_FLASHCONTROL);
77 flash_status = readb(docptr + DOC_FLASHCONTROL);
78 } while (!(flash_status & DOC_CTRL_FLASHREADY));
83 static void write_addr(void __iomem *docptr, uint32_t docg4_addr)
85 /* write the four address bytes packed in docg4_addr to the device */
87 writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
89 writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
91 writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
93 writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
96 static void address_sequence(unsigned int g4_page, unsigned int g4_index,
99 writew(DOCG4_SEQ_PAGE_READ, docptr + DOC_FLASHSEQUENCE);
100 writew(DOCG4_CMD_PAGE_READ, docptr + DOC_FLASHCOMMAND);
102 write_addr(docptr, ((uint32_t)g4_page << 16) | g4_index);
106 static int docg4_load_block_reliable(uint32_t flash_offset, void *dest_addr)
108 void __iomem *docptr = (void *)CONFIG_SYS_NAND_BASE;
109 unsigned int g4_page = flash_offset >> 11; /* 2k page */
110 const unsigned int last_g4_page = g4_page + 0x80; /* last in block */
112 uint16_t flash_status;
115 /* flash_offset must be aligned to the start of a block */
116 if (flash_offset & 0x3ffff)
119 writew(DOC_SEQ_RESET, docptr + DOC_FLASHSEQUENCE);
120 writew(DOC_CMD_RESET, docptr + DOC_FLASHCOMMAND);
125 writew(0x45, docptr + DOC_FLASHSEQUENCE);
126 writew(0xa3, docptr + DOC_FLASHCOMMAND);
128 writew(0x22, docptr + DOC_FLASHCOMMAND);
131 /* read 1st 4 oob bytes of first subpage of block */
132 address_sequence(g4_page, 0x0100, docptr); /* index at oob */
134 flash_status = readw(docptr + DOC_FLASHCONTROL);
135 flash_status = readw(docptr + DOC_FLASHCONTROL);
136 if (flash_status & 0x06) /* sequence or protection errors */
138 writew(DOCG4_CMD_READ2, docptr + DOC_FLASHCOMMAND);
142 writew(DOC_ECCCONF0_READ_MODE | 4, docptr + DOC_ECCCONF0);
150 * Here we read the first four oob bytes of the first page of the block.
151 * The IPL on the palmtreo680 requires that this contain a 32 bit magic
152 * number, or the load aborts. We'll ignore it.
154 readw(docptr + 0x103c); /* hw quirk; 1st read discarded */
155 readw(docptr + 0x103c); /* lower 16 bits of magic number */
156 readw(docptr + DOCG4_MYSTERY_REG); /* upper 16 bits of magic number */
157 writew(0, docptr + DOC_DATAEND);
161 /* load contents of block to memory */
162 buf = (uint16_t *)dest_addr;
166 address_sequence(g4_page, g4_index, docptr);
167 writew(DOCG4_CMD_READ2,
168 docptr + DOC_FLASHCOMMAND);
172 writew(DOC_ECCCONF0_READ_MODE |
173 DOC_ECCCONF0_ECC_ENABLE |
175 docptr + DOC_ECCCONF0);
182 /* read the 512 bytes of page data, 2 bytes at a time */
183 readw(docptr + 0x103c); /* hw quirk */
184 for (i = 0; i < 256; i++)
185 *buf++ = readw(docptr + 0x103c);
187 /* read oob, but discard it */
188 for (i = 0; i < 7; i++)
189 readw(docptr + 0x103c);
190 readw(docptr + DOCG4_OOB_6_7);
191 readw(docptr + DOCG4_OOB_6_7);
193 writew(0, docptr + DOC_DATAEND);
197 if (!(g4_index & 0x100)) {
198 /* not redundant subpage read; check for ecc error */
200 flash_status = readw(docptr + DOC_ECCCONF1);
201 flash_status = readw(docptr + DOC_ECCCONF1);
202 if (flash_status & 0x80) { /* ecc error */
203 g4_index += 0x108; /* read redundant subpage */
204 buf -= 256; /* back up ram ptr */
206 } else /* no ecc error */
207 g4_index += 0x210; /* skip redundant subpage */
208 } else /* redundant page was just read; skip ecc error check */
211 if (g4_index == 0x420) { /* finished with 2k page */
213 g4_page += 2; /* odd-numbered 2k pages skipped */
216 } while (g4_page != last_g4_page); /* while still on same block */