1 /* Freescale Enhanced Local Bus Controller FCM NAND driver
3 * Copyright (c) 2006-2008 Freescale Semiconductor
5 * Authors: Nick Spence <nick.spence@freescale.com>,
6 * Scott Wood <scottwood@freescale.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 #include <linux/mtd/mtd.h>
27 #include <linux/mtd/nand.h>
28 #include <linux/mtd/nand_ecc.h>
31 #include <asm/errno.h>
35 #define vdbg(format, arg...) printf("DEBUG: " format, ##arg)
37 #define vdbg(format, arg...) do {} while (0)
40 /* Can't use plain old DEBUG because the linux mtd
41 * headers define it as a macro.
44 #define dbg(format, arg...) printf("DEBUG: " format, ##arg)
46 #define dbg(format, arg...) do {} while (0)
50 #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
51 #define FCM_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for FCM */
53 #define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
57 /* mtd information per set */
61 struct nand_chip chip;
62 struct fsl_elbc_ctrl *ctrl;
65 int bank; /* Chip select bank number */
66 u8 __iomem *vbase; /* Chip select base virtual address */
67 int page_size; /* NAND page size (0=512, 1=2048) */
68 unsigned int fmr; /* FCM Flash Mode Register value */
71 /* overview of the fsl elbc controller */
73 struct fsl_elbc_ctrl {
74 struct nand_hw_control controller;
75 struct fsl_elbc_mtd *chips[MAX_BANKS];
79 u8 __iomem *addr; /* Address of assigned FCM buffer */
80 unsigned int page; /* Last page written to / read from */
81 unsigned int read_bytes; /* Number of bytes read during command */
82 unsigned int column; /* Saved column from SEQIN */
83 unsigned int index; /* Pointer to next byte to 'read' */
84 unsigned int status; /* status read from LTESR after last op */
85 unsigned int mdr; /* UPM/FCM Data Register value */
86 unsigned int use_mdr; /* Non zero if the MDR is to be set */
87 unsigned int oob; /* Non zero if operating on OOB data */
90 /* These map to the positions used by the FCM hardware ECC generator */
92 /* Small Page FLASH with FMR[ECCM] = 0 */
93 static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = {
96 .oobfree = { {0, 5}, {9, 7} },
99 /* Small Page FLASH with FMR[ECCM] = 1 */
100 static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = {
102 .eccpos = {8, 9, 10},
103 .oobfree = { {0, 5}, {6, 2}, {11, 5} },
106 /* Large Page FLASH with FMR[ECCM] = 0 */
107 static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = {
109 .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
110 .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} },
113 /* Large Page FLASH with FMR[ECCM] = 1 */
114 static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
116 .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
117 .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} },
121 * fsl_elbc_oob_lp_eccm* specify that LP NAND's OOB free area starts at offset
122 * 1, so we have to adjust bad block pattern. This pattern should be used for
123 * x8 chips only. So far hardware does not support x16 chips anyway.
125 static u8 scan_ff_pattern[] = { 0xff, };
127 static struct nand_bbt_descr largepage_memorybased = {
131 .pattern = scan_ff_pattern,
135 * ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt,
136 * interfere with ECC positions, that's why we implement our own descriptors.
137 * OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0.
139 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
140 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
142 static struct nand_bbt_descr bbt_main_descr = {
143 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
144 NAND_BBT_2BIT | NAND_BBT_VERSION,
149 .pattern = bbt_pattern,
152 static struct nand_bbt_descr bbt_mirror_descr = {
153 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
154 NAND_BBT_2BIT | NAND_BBT_VERSION,
159 .pattern = mirror_pattern,
162 /*=================================*/
165 * Set up the FCM hardware block and page address fields, and the fcm
166 * structure addr field to point to the correct FCM buffer in memory
168 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
170 struct nand_chip *chip = mtd->priv;
171 struct fsl_elbc_mtd *priv = chip->priv;
172 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
173 fsl_lbc_t *lbc = ctrl->regs;
176 ctrl->page = page_addr;
178 if (priv->page_size) {
179 out_be32(&lbc->fbar, page_addr >> 6);
181 ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
182 (oob ? FPAR_LP_MS : 0) | column);
183 buf_num = (page_addr & 1) << 2;
185 out_be32(&lbc->fbar, page_addr >> 5);
187 ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
188 (oob ? FPAR_SP_MS : 0) | column);
189 buf_num = page_addr & 7;
192 ctrl->addr = priv->vbase + buf_num * 1024;
193 ctrl->index = column;
195 /* for OOB data point to the second half of the buffer */
197 ctrl->index += priv->page_size ? 2048 : 512;
199 vdbg("set_addr: bank=%d, ctrl->addr=0x%p (0x%p), "
200 "index %x, pes %d ps %d\n",
201 buf_num, ctrl->addr, priv->vbase, ctrl->index,
202 chip->phys_erase_shift, chip->page_shift);
206 * execute FCM command and wait for it to complete
208 static int fsl_elbc_run_command(struct mtd_info *mtd)
210 struct nand_chip *chip = mtd->priv;
211 struct fsl_elbc_mtd *priv = chip->priv;
212 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
213 fsl_lbc_t *lbc = ctrl->regs;
217 /* Setup the FMR[OP] to execute without write protection */
218 out_be32(&lbc->fmr, priv->fmr | 3);
220 out_be32(&lbc->mdr, ctrl->mdr);
222 vdbg("fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
223 in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
224 vdbg("fsl_elbc_run_command: fbar=%08x fpar=%08x "
225 "fbcr=%08x bank=%d\n",
226 in_be32(&lbc->fbar), in_be32(&lbc->fpar),
227 in_be32(&lbc->fbcr), priv->bank);
229 /* execute special operation */
230 out_be32(&lbc->lsor, priv->bank);
232 /* wait for FCM complete flag or timeout */
233 end_tick = usec2ticks(FCM_TIMEOUT_MSECS * 1000) + get_ticks();
236 while (end_tick > get_ticks()) {
237 ltesr = in_be32(&lbc->ltesr);
238 if (ltesr & LTESR_CC)
242 ctrl->status = ltesr & LTESR_NAND_MASK;
243 out_be32(&lbc->ltesr, ctrl->status);
244 out_be32(&lbc->lteatr, 0);
246 /* store mdr value in case it was needed */
248 ctrl->mdr = in_be32(&lbc->mdr);
252 vdbg("fsl_elbc_run_command: stat=%08x mdr=%08x fmr=%08x\n",
253 ctrl->status, ctrl->mdr, in_be32(&lbc->fmr));
255 /* returns 0 on success otherwise non-zero) */
256 return ctrl->status == LTESR_CC ? 0 : -EIO;
259 static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
261 struct fsl_elbc_mtd *priv = chip->priv;
262 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
263 fsl_lbc_t *lbc = ctrl->regs;
265 if (priv->page_size) {
267 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
268 (FIR_OP_CA << FIR_OP1_SHIFT) |
269 (FIR_OP_PA << FIR_OP2_SHIFT) |
270 (FIR_OP_CW1 << FIR_OP3_SHIFT) |
271 (FIR_OP_RBW << FIR_OP4_SHIFT));
273 out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
274 (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
277 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
278 (FIR_OP_CA << FIR_OP1_SHIFT) |
279 (FIR_OP_PA << FIR_OP2_SHIFT) |
280 (FIR_OP_RBW << FIR_OP3_SHIFT));
284 NAND_CMD_READOOB << FCR_CMD0_SHIFT);
286 out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
290 /* cmdfunc send commands to the FCM */
291 static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
292 int column, int page_addr)
294 struct nand_chip *chip = mtd->priv;
295 struct fsl_elbc_mtd *priv = chip->priv;
296 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
297 fsl_lbc_t *lbc = ctrl->regs;
301 /* clear the read buffer */
302 ctrl->read_bytes = 0;
303 if (command != NAND_CMD_PAGEPROG)
307 /* READ0 and READ1 read the entire buffer to use hardware ECC. */
313 vdbg("fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
314 " 0x%x, column: 0x%x.\n", page_addr, column);
316 out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
317 set_addr(mtd, 0, page_addr, 0);
319 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
320 ctrl->index += column;
322 fsl_elbc_do_read(chip, 0);
323 fsl_elbc_run_command(mtd);
326 /* READOOB reads only the OOB because no ECC is performed. */
327 case NAND_CMD_READOOB:
328 vdbg("fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
329 " 0x%x, column: 0x%x.\n", page_addr, column);
331 out_be32(&lbc->fbcr, mtd->oobsize - column);
332 set_addr(mtd, column, page_addr, 1);
334 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
336 fsl_elbc_do_read(chip, 1);
337 fsl_elbc_run_command(mtd);
341 /* READID must read all 5 possible bytes while CEB is active */
342 case NAND_CMD_READID:
343 vdbg("fsl_elbc_cmdfunc: NAND_CMD_READID.\n");
345 out_be32(&lbc->fir, (FIR_OP_CW0 << FIR_OP0_SHIFT) |
346 (FIR_OP_UA << FIR_OP1_SHIFT) |
347 (FIR_OP_RBW << FIR_OP2_SHIFT));
348 out_be32(&lbc->fcr, NAND_CMD_READID << FCR_CMD0_SHIFT);
349 /* 5 bytes for manuf, device and exts */
350 out_be32(&lbc->fbcr, 5);
351 ctrl->read_bytes = 5;
355 set_addr(mtd, 0, 0, 0);
356 fsl_elbc_run_command(mtd);
359 /* ERASE1 stores the block and page address */
360 case NAND_CMD_ERASE1:
361 vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
362 "page_addr: 0x%x.\n", page_addr);
363 set_addr(mtd, 0, page_addr, 0);
366 /* ERASE2 uses the block and page address from ERASE1 */
367 case NAND_CMD_ERASE2:
368 vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
371 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
372 (FIR_OP_PA << FIR_OP1_SHIFT) |
373 (FIR_OP_CM1 << FIR_OP2_SHIFT));
376 (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
377 (NAND_CMD_ERASE2 << FCR_CMD1_SHIFT));
379 out_be32(&lbc->fbcr, 0);
380 ctrl->read_bytes = 0;
382 fsl_elbc_run_command(mtd);
385 /* SEQIN sets up the addr buffer and all registers except the length */
386 case NAND_CMD_SEQIN: {
388 vdbg("fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
389 "page_addr: 0x%x, column: 0x%x.\n",
392 ctrl->column = column;
395 if (priv->page_size) {
396 fcr = (NAND_CMD_SEQIN << FCR_CMD0_SHIFT) |
397 (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT);
400 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
401 (FIR_OP_CA << FIR_OP1_SHIFT) |
402 (FIR_OP_PA << FIR_OP2_SHIFT) |
403 (FIR_OP_WB << FIR_OP3_SHIFT) |
404 (FIR_OP_CW1 << FIR_OP4_SHIFT));
406 fcr = (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT) |
407 (NAND_CMD_SEQIN << FCR_CMD2_SHIFT);
410 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
411 (FIR_OP_CM2 << FIR_OP1_SHIFT) |
412 (FIR_OP_CA << FIR_OP2_SHIFT) |
413 (FIR_OP_PA << FIR_OP3_SHIFT) |
414 (FIR_OP_WB << FIR_OP4_SHIFT) |
415 (FIR_OP_CW1 << FIR_OP5_SHIFT));
417 if (column >= mtd->writesize) {
418 /* OOB area --> READOOB */
419 column -= mtd->writesize;
420 fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
422 } else if (column < 256) {
423 /* First 256 bytes --> READ0 */
424 fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
426 /* Second 256 bytes --> READ1 */
427 fcr |= NAND_CMD_READ1 << FCR_CMD0_SHIFT;
431 out_be32(&lbc->fcr, fcr);
432 set_addr(mtd, column, page_addr, ctrl->oob);
436 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
437 case NAND_CMD_PAGEPROG: {
438 vdbg("fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
439 "writing %d bytes.\n", ctrl->index);
441 /* if the write did not start at 0 or is not a full page
442 * then set the exact length, otherwise use a full page
443 * write so the HW generates the ECC.
445 if (ctrl->oob || ctrl->column != 0 ||
446 ctrl->index != mtd->writesize + mtd->oobsize)
447 out_be32(&lbc->fbcr, ctrl->index);
449 out_be32(&lbc->fbcr, 0);
451 fsl_elbc_run_command(mtd);
456 /* CMD_STATUS must read the status byte while CEB is active */
457 /* Note - it does not wait for the ready line */
458 case NAND_CMD_STATUS:
460 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
461 (FIR_OP_RBW << FIR_OP1_SHIFT));
462 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
463 out_be32(&lbc->fbcr, 1);
464 set_addr(mtd, 0, 0, 0);
465 ctrl->read_bytes = 1;
467 fsl_elbc_run_command(mtd);
469 /* The chip always seems to report that it is
470 * write-protected, even when it is not.
472 out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
475 /* RESET without waiting for the ready line */
477 dbg("fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
478 out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
479 out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
480 fsl_elbc_run_command(mtd);
484 printf("fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
489 static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
491 /* The hardware does not seem to support multiple
497 * Write buf to the FCM Controller Data Buffer
499 static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
501 struct nand_chip *chip = mtd->priv;
502 struct fsl_elbc_mtd *priv = chip->priv;
503 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
504 unsigned int bufsize = mtd->writesize + mtd->oobsize;
507 printf("write_buf of %d bytes", len);
512 if ((unsigned int)len > bufsize - ctrl->index) {
513 printf("write_buf beyond end of buffer "
514 "(%d requested, %u available)\n",
515 len, bufsize - ctrl->index);
516 len = bufsize - ctrl->index;
519 memcpy_toio(&ctrl->addr[ctrl->index], buf, len);
521 * This is workaround for the weird elbc hangs during nand write,
522 * Scott Wood says: "...perhaps difference in how long it takes a
523 * write to make it through the localbus compared to a write to IMMR
524 * is causing problems, and sync isn't helping for some reason."
525 * Reading back the last byte helps though.
527 in_8(&ctrl->addr[ctrl->index] + len - 1);
533 * read a byte from either the FCM hardware buffer if it has any data left
534 * otherwise issue a command to read a single byte.
536 static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
538 struct nand_chip *chip = mtd->priv;
539 struct fsl_elbc_mtd *priv = chip->priv;
540 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
542 /* If there are still bytes in the FCM, then use the next byte. */
543 if (ctrl->index < ctrl->read_bytes)
544 return in_8(&ctrl->addr[ctrl->index++]);
546 printf("read_byte beyond end of buffer\n");
551 * Read from the FCM Controller Data Buffer
553 static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
555 struct nand_chip *chip = mtd->priv;
556 struct fsl_elbc_mtd *priv = chip->priv;
557 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
563 avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
564 memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail);
565 ctrl->index += avail;
568 printf("read_buf beyond end of buffer "
569 "(%d requested, %d available)\n",
574 * Verify buffer against the FCM Controller Data Buffer
576 static int fsl_elbc_verify_buf(struct mtd_info *mtd,
577 const u_char *buf, int len)
579 struct nand_chip *chip = mtd->priv;
580 struct fsl_elbc_mtd *priv = chip->priv;
581 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
585 printf("write_buf of %d bytes", len);
589 if ((unsigned int)len > ctrl->read_bytes - ctrl->index) {
590 printf("verify_buf beyond end of buffer "
591 "(%d requested, %u available)\n",
592 len, ctrl->read_bytes - ctrl->index);
594 ctrl->index = ctrl->read_bytes;
598 for (i = 0; i < len; i++)
599 if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i])
603 return i == len && ctrl->status == LTESR_CC ? 0 : -EIO;
606 /* This function is called after Program and Erase Operations to
607 * check for success or failure.
609 static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
611 struct fsl_elbc_mtd *priv = chip->priv;
612 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
613 fsl_lbc_t *lbc = ctrl->regs;
615 if (ctrl->status != LTESR_CC)
616 return NAND_STATUS_FAIL;
618 /* Use READ_STATUS command, but wait for the device to be ready */
621 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
622 (FIR_OP_RBW << FIR_OP1_SHIFT));
623 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
624 out_be32(&lbc->fbcr, 1);
625 set_addr(mtd, 0, 0, 0);
626 ctrl->read_bytes = 1;
628 fsl_elbc_run_command(mtd);
630 if (ctrl->status != LTESR_CC)
631 return NAND_STATUS_FAIL;
633 /* The chip always seems to report that it is
634 * write-protected, even when it is not.
636 out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
637 return fsl_elbc_read_byte(mtd);
640 static int fsl_elbc_read_page(struct mtd_info *mtd,
641 struct nand_chip *chip,
642 uint8_t *buf, int page)
644 fsl_elbc_read_buf(mtd, buf, mtd->writesize);
645 fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
647 if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL)
648 mtd->ecc_stats.failed++;
653 /* ECC will be calculated automatically, and errors will be detected in
656 static void fsl_elbc_write_page(struct mtd_info *mtd,
657 struct nand_chip *chip,
660 fsl_elbc_write_buf(mtd, buf, mtd->writesize);
661 fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
664 static struct fsl_elbc_ctrl *elbc_ctrl;
666 static void fsl_elbc_ctrl_init(void)
668 elbc_ctrl = kzalloc(sizeof(*elbc_ctrl), GFP_KERNEL);
672 elbc_ctrl->regs = LBC_BASE_ADDR;
674 /* clear event registers */
675 out_be32(&elbc_ctrl->regs->ltesr, LTESR_NAND_MASK);
676 out_be32(&elbc_ctrl->regs->lteatr, 0);
678 /* Enable interrupts for any detected events */
679 out_be32(&elbc_ctrl->regs->lteir, LTESR_NAND_MASK);
681 elbc_ctrl->read_bytes = 0;
682 elbc_ctrl->index = 0;
683 elbc_ctrl->addr = NULL;
686 int board_nand_init(struct nand_chip *nand)
688 struct fsl_elbc_mtd *priv;
689 uint32_t br = 0, or = 0;
692 fsl_elbc_ctrl_init();
697 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
701 priv->ctrl = elbc_ctrl;
702 priv->vbase = nand->IO_ADDR_R;
704 /* Find which chip select it is connected to. It'd be nice
705 * if we could pass more than one datum to the NAND driver...
707 for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
708 phys_addr_t base_addr = virt_to_phys(nand->IO_ADDR_R);
710 br = in_be32(&elbc_ctrl->regs->bank[priv->bank].br);
711 or = in_be32(&elbc_ctrl->regs->bank[priv->bank].or);
713 if ((br & BR_V) && (br & BR_MSEL) == BR_MS_FCM &&
714 (br & or & BR_BA) == BR_PHYS_ADDR(base_addr))
718 if (priv->bank >= MAX_BANKS) {
719 printf("fsl_elbc_nand: address did not match any "
724 elbc_ctrl->chips[priv->bank] = priv;
726 /* fill in nand_chip structure */
727 /* set up function call table */
728 nand->read_byte = fsl_elbc_read_byte;
729 nand->write_buf = fsl_elbc_write_buf;
730 nand->read_buf = fsl_elbc_read_buf;
731 nand->verify_buf = fsl_elbc_verify_buf;
732 nand->select_chip = fsl_elbc_select_chip;
733 nand->cmdfunc = fsl_elbc_cmdfunc;
734 nand->waitfunc = fsl_elbc_wait;
736 /* set up nand options */
737 nand->bbt_td = &bbt_main_descr;
738 nand->bbt_md = &bbt_mirror_descr;
740 /* set up nand options */
741 nand->options = NAND_NO_READRDY | NAND_NO_AUTOINCR |
744 nand->controller = &elbc_ctrl->controller;
747 nand->ecc.read_page = fsl_elbc_read_page;
748 nand->ecc.write_page = fsl_elbc_write_page;
750 #ifdef CONFIG_FSL_ELBC_FMR
751 priv->fmr = CONFIG_FSL_ELBC_FMR;
753 priv->fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT);
756 * Hardware expects small page has ECCM0, large page has ECCM1
757 * when booting from NAND. Board config can override if not
761 priv->fmr |= FMR_ECCM;
764 /* If CS Base Register selects full hardware ECC then use it */
765 if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
766 nand->ecc.mode = NAND_ECC_HW;
768 nand->ecc.layout = (priv->fmr & FMR_ECCM) ?
769 &fsl_elbc_oob_sp_eccm1 :
770 &fsl_elbc_oob_sp_eccm0;
772 nand->ecc.size = 512;
776 /* otherwise fall back to default software ECC */
777 nand->ecc.mode = NAND_ECC_SOFT;
780 /* Large-page-specific setup */
781 if (or & OR_FCM_PGS) {
783 nand->badblock_pattern = &largepage_memorybased;
785 /* adjust ecc setup if needed */
786 if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
788 nand->ecc.layout = (priv->fmr & FMR_ECCM) ?
789 &fsl_elbc_oob_lp_eccm1 :
790 &fsl_elbc_oob_lp_eccm0;