1 /* Freescale Enhanced Local Bus Controller FCM NAND driver
3 * Copyright (c) 2006-2008 Freescale Semiconductor
5 * Authors: Nick Spence <nick.spence@freescale.com>,
6 * Scott Wood <scottwood@freescale.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 #include <linux/mtd/mtd.h>
27 #include <linux/mtd/nand.h>
28 #include <linux/mtd/nand_ecc.h>
31 #include <asm/errno.h>
35 #define vdbg(format, arg...) printf("DEBUG: " format, ##arg)
37 #define vdbg(format, arg...) do {} while (0)
40 /* Can't use plain old DEBUG because the linux mtd
41 * headers define it as a macro.
44 #define dbg(format, arg...) printf("DEBUG: " format, ##arg)
46 #define dbg(format, arg...) do {} while (0)
50 #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
51 #define FCM_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for FCM */
53 #define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
57 /* mtd information per set */
61 struct nand_chip chip;
62 struct fsl_elbc_ctrl *ctrl;
65 int bank; /* Chip select bank number */
66 u8 __iomem *vbase; /* Chip select base virtual address */
67 int page_size; /* NAND page size (0=512, 1=2048) */
68 unsigned int fmr; /* FCM Flash Mode Register value */
71 /* overview of the fsl elbc controller */
73 struct fsl_elbc_ctrl {
74 struct nand_hw_control controller;
75 struct fsl_elbc_mtd *chips[MAX_BANKS];
79 u8 __iomem *addr; /* Address of assigned FCM buffer */
80 unsigned int page; /* Last page written to / read from */
81 unsigned int read_bytes; /* Number of bytes read during command */
82 unsigned int column; /* Saved column from SEQIN */
83 unsigned int index; /* Pointer to next byte to 'read' */
84 unsigned int status; /* status read from LTESR after last op */
85 unsigned int mdr; /* UPM/FCM Data Register value */
86 unsigned int use_mdr; /* Non zero if the MDR is to be set */
87 unsigned int oob; /* Non zero if operating on OOB data */
88 uint8_t *oob_poi; /* Place to write ECC after read back */
91 /* These map to the positions used by the FCM hardware ECC generator */
93 /* Small Page FLASH with FMR[ECCM] = 0 */
94 static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = {
97 .oobfree = { {0, 5}, {9, 7} },
101 /* Small Page FLASH with FMR[ECCM] = 1 */
102 static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = {
104 .eccpos = {8, 9, 10},
105 .oobfree = { {0, 5}, {6, 2}, {11, 5} },
109 /* Large Page FLASH with FMR[ECCM] = 0 */
110 static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = {
112 .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
113 .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} },
117 /* Large Page FLASH with FMR[ECCM] = 1 */
118 static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
120 .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
121 .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} },
125 /*=================================*/
128 * Set up the FCM hardware block and page address fields, and the fcm
129 * structure addr field to point to the correct FCM buffer in memory
131 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
133 struct nand_chip *chip = mtd->priv;
134 struct fsl_elbc_mtd *priv = chip->priv;
135 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
136 lbus83xx_t *lbc = ctrl->regs;
139 ctrl->page = page_addr;
142 page_addr >> (chip->phys_erase_shift - chip->page_shift));
144 if (priv->page_size) {
146 ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
147 (oob ? FPAR_LP_MS : 0) | column);
148 buf_num = (page_addr & 1) << 2;
151 ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
152 (oob ? FPAR_SP_MS : 0) | column);
153 buf_num = page_addr & 7;
156 ctrl->addr = priv->vbase + buf_num * 1024;
157 ctrl->index = column;
159 /* for OOB data point to the second half of the buffer */
161 ctrl->index += priv->page_size ? 2048 : 512;
163 vdbg("set_addr: bank=%d, ctrl->addr=0x%p (0x%p), "
164 "index %x, pes %d ps %d\n",
165 buf_num, ctrl->addr, priv->vbase, ctrl->index,
166 chip->phys_erase_shift, chip->page_shift);
170 * execute FCM command and wait for it to complete
172 static int fsl_elbc_run_command(struct mtd_info *mtd)
174 struct nand_chip *chip = mtd->priv;
175 struct fsl_elbc_mtd *priv = chip->priv;
176 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
177 lbus83xx_t *lbc = ctrl->regs;
181 /* Setup the FMR[OP] to execute without write protection */
182 out_be32(&lbc->fmr, priv->fmr | 3);
184 out_be32(&lbc->mdr, ctrl->mdr);
186 vdbg("fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
187 in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
188 vdbg("fsl_elbc_run_command: fbar=%08x fpar=%08x "
189 "fbcr=%08x bank=%d\n",
190 in_be32(&lbc->fbar), in_be32(&lbc->fpar),
191 in_be32(&lbc->fbcr), priv->bank);
193 /* execute special operation */
194 out_be32(&lbc->lsor, priv->bank);
196 /* wait for FCM complete flag or timeout */
197 end_tick = usec2ticks(FCM_TIMEOUT_MSECS * 1000) + get_ticks();
200 while (end_tick > get_ticks()) {
201 ltesr = in_be32(&lbc->ltesr);
202 if (ltesr & LTESR_CC)
206 ctrl->status = ltesr & LTESR_NAND_MASK;
207 out_be32(&lbc->ltesr, ctrl->status);
208 out_be32(&lbc->lteatr, 0);
210 /* store mdr value in case it was needed */
212 ctrl->mdr = in_be32(&lbc->mdr);
216 vdbg("fsl_elbc_run_command: stat=%08x mdr=%08x fmr=%08x\n",
217 ctrl->status, ctrl->mdr, in_be32(&lbc->fmr));
219 /* returns 0 on success otherwise non-zero) */
220 return ctrl->status == LTESR_CC ? 0 : -EIO;
223 static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
225 struct fsl_elbc_mtd *priv = chip->priv;
226 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
227 lbus83xx_t *lbc = ctrl->regs;
229 if (priv->page_size) {
231 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
232 (FIR_OP_CA << FIR_OP1_SHIFT) |
233 (FIR_OP_PA << FIR_OP2_SHIFT) |
234 (FIR_OP_CW1 << FIR_OP3_SHIFT) |
235 (FIR_OP_RBW << FIR_OP4_SHIFT));
237 out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
238 (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
241 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
242 (FIR_OP_CA << FIR_OP1_SHIFT) |
243 (FIR_OP_PA << FIR_OP2_SHIFT) |
244 (FIR_OP_RBW << FIR_OP3_SHIFT));
248 NAND_CMD_READOOB << FCR_CMD0_SHIFT);
250 out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
254 /* cmdfunc send commands to the FCM */
255 static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
256 int column, int page_addr)
258 struct nand_chip *chip = mtd->priv;
259 struct fsl_elbc_mtd *priv = chip->priv;
260 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
261 lbus83xx_t *lbc = ctrl->regs;
265 /* clear the read buffer */
266 ctrl->read_bytes = 0;
267 if (command != NAND_CMD_PAGEPROG)
271 /* READ0 and READ1 read the entire buffer to use hardware ECC. */
277 vdbg("fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
278 " 0x%x, column: 0x%x.\n", page_addr, column);
280 out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
281 set_addr(mtd, 0, page_addr, 0);
283 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
284 ctrl->index += column;
286 fsl_elbc_do_read(chip, 0);
287 fsl_elbc_run_command(mtd);
290 /* READOOB reads only the OOB because no ECC is performed. */
291 case NAND_CMD_READOOB:
292 vdbg("fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
293 " 0x%x, column: 0x%x.\n", page_addr, column);
295 out_be32(&lbc->fbcr, mtd->oobsize - column);
296 set_addr(mtd, column, page_addr, 1);
298 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
300 fsl_elbc_do_read(chip, 1);
301 fsl_elbc_run_command(mtd);
305 /* READID must read all 5 possible bytes while CEB is active */
306 case NAND_CMD_READID:
307 vdbg("fsl_elbc_cmdfunc: NAND_CMD_READID.\n");
309 out_be32(&lbc->fir, (FIR_OP_CW0 << FIR_OP0_SHIFT) |
310 (FIR_OP_UA << FIR_OP1_SHIFT) |
311 (FIR_OP_RBW << FIR_OP2_SHIFT));
312 out_be32(&lbc->fcr, NAND_CMD_READID << FCR_CMD0_SHIFT);
313 /* 5 bytes for manuf, device and exts */
314 out_be32(&lbc->fbcr, 5);
315 ctrl->read_bytes = 5;
319 set_addr(mtd, 0, 0, 0);
320 fsl_elbc_run_command(mtd);
323 /* ERASE1 stores the block and page address */
324 case NAND_CMD_ERASE1:
325 vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
326 "page_addr: 0x%x.\n", page_addr);
327 set_addr(mtd, 0, page_addr, 0);
330 /* ERASE2 uses the block and page address from ERASE1 */
331 case NAND_CMD_ERASE2:
332 vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
335 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
336 (FIR_OP_PA << FIR_OP1_SHIFT) |
337 (FIR_OP_CM1 << FIR_OP2_SHIFT));
340 (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
341 (NAND_CMD_ERASE2 << FCR_CMD1_SHIFT));
343 out_be32(&lbc->fbcr, 0);
344 ctrl->read_bytes = 0;
346 fsl_elbc_run_command(mtd);
349 /* SEQIN sets up the addr buffer and all registers except the length */
350 case NAND_CMD_SEQIN: {
352 vdbg("fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
353 "page_addr: 0x%x, column: 0x%x.\n",
356 ctrl->column = column;
359 if (priv->page_size) {
360 fcr = (NAND_CMD_SEQIN << FCR_CMD0_SHIFT) |
361 (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT);
364 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
365 (FIR_OP_CA << FIR_OP1_SHIFT) |
366 (FIR_OP_PA << FIR_OP2_SHIFT) |
367 (FIR_OP_WB << FIR_OP3_SHIFT) |
368 (FIR_OP_CW1 << FIR_OP4_SHIFT));
370 fcr = (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT) |
371 (NAND_CMD_SEQIN << FCR_CMD2_SHIFT);
374 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
375 (FIR_OP_CM2 << FIR_OP1_SHIFT) |
376 (FIR_OP_CA << FIR_OP2_SHIFT) |
377 (FIR_OP_PA << FIR_OP3_SHIFT) |
378 (FIR_OP_WB << FIR_OP4_SHIFT) |
379 (FIR_OP_CW1 << FIR_OP5_SHIFT));
381 if (column >= mtd->writesize) {
382 /* OOB area --> READOOB */
383 column -= mtd->writesize;
384 fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
386 } else if (column < 256) {
387 /* First 256 bytes --> READ0 */
388 fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
390 /* Second 256 bytes --> READ1 */
391 fcr |= NAND_CMD_READ1 << FCR_CMD0_SHIFT;
395 out_be32(&lbc->fcr, fcr);
396 set_addr(mtd, column, page_addr, ctrl->oob);
400 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
401 case NAND_CMD_PAGEPROG: {
403 vdbg("fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
404 "writing %d bytes.\n", ctrl->index);
406 /* if the write did not start at 0 or is not a full page
407 * then set the exact length, otherwise use a full page
408 * write so the HW generates the ECC.
410 if (ctrl->oob || ctrl->column != 0 ||
411 ctrl->index != mtd->writesize + mtd->oobsize) {
412 out_be32(&lbc->fbcr, ctrl->index);
415 out_be32(&lbc->fbcr, 0);
419 fsl_elbc_run_command(mtd);
421 /* Read back the page in order to fill in the ECC for the
422 * caller. Is this really needed?
424 if (full_page && ctrl->oob_poi) {
425 out_be32(&lbc->fbcr, 3);
426 set_addr(mtd, 6, page_addr, 1);
428 ctrl->read_bytes = mtd->writesize + 9;
430 fsl_elbc_do_read(chip, 1);
431 fsl_elbc_run_command(mtd);
433 memcpy_fromio(ctrl->oob_poi + 6,
434 &ctrl->addr[ctrl->index], 3);
438 ctrl->oob_poi = NULL;
442 /* CMD_STATUS must read the status byte while CEB is active */
443 /* Note - it does not wait for the ready line */
444 case NAND_CMD_STATUS:
446 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
447 (FIR_OP_RBW << FIR_OP1_SHIFT));
448 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
449 out_be32(&lbc->fbcr, 1);
450 set_addr(mtd, 0, 0, 0);
451 ctrl->read_bytes = 1;
453 fsl_elbc_run_command(mtd);
455 /* The chip always seems to report that it is
456 * write-protected, even when it is not.
458 out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
461 /* RESET without waiting for the ready line */
463 dbg("fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
464 out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
465 out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
466 fsl_elbc_run_command(mtd);
470 printf("fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
475 static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
477 /* The hardware does not seem to support multiple
483 * Write buf to the FCM Controller Data Buffer
485 static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
487 struct nand_chip *chip = mtd->priv;
488 struct fsl_elbc_mtd *priv = chip->priv;
489 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
490 unsigned int bufsize = mtd->writesize + mtd->oobsize;
493 printf("write_buf of %d bytes", len);
498 if ((unsigned int)len > bufsize - ctrl->index) {
499 printf("write_buf beyond end of buffer "
500 "(%d requested, %u available)\n",
501 len, bufsize - ctrl->index);
502 len = bufsize - ctrl->index;
505 memcpy_toio(&ctrl->addr[ctrl->index], buf, len);
510 * read a byte from either the FCM hardware buffer if it has any data left
511 * otherwise issue a command to read a single byte.
513 static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
515 struct nand_chip *chip = mtd->priv;
516 struct fsl_elbc_mtd *priv = chip->priv;
517 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
519 /* If there are still bytes in the FCM, then use the next byte. */
520 if (ctrl->index < ctrl->read_bytes)
521 return in_8(&ctrl->addr[ctrl->index++]);
523 printf("read_byte beyond end of buffer\n");
528 * Read from the FCM Controller Data Buffer
530 static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
532 struct nand_chip *chip = mtd->priv;
533 struct fsl_elbc_mtd *priv = chip->priv;
534 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
540 avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
541 memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail);
542 ctrl->index += avail;
545 printf("read_buf beyond end of buffer "
546 "(%d requested, %d available)\n",
551 * Verify buffer against the FCM Controller Data Buffer
553 static int fsl_elbc_verify_buf(struct mtd_info *mtd,
554 const u_char *buf, int len)
556 struct nand_chip *chip = mtd->priv;
557 struct fsl_elbc_mtd *priv = chip->priv;
558 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
562 printf("write_buf of %d bytes", len);
566 if ((unsigned int)len > ctrl->read_bytes - ctrl->index) {
567 printf("verify_buf beyond end of buffer "
568 "(%d requested, %u available)\n",
569 len, ctrl->read_bytes - ctrl->index);
571 ctrl->index = ctrl->read_bytes;
575 for (i = 0; i < len; i++)
576 if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i])
580 return i == len && ctrl->status == LTESR_CC ? 0 : -EIO;
583 /* This function is called after Program and Erase Operations to
584 * check for success or failure.
586 static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
588 struct fsl_elbc_mtd *priv = chip->priv;
589 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
590 lbus83xx_t *lbc = ctrl->regs;
592 if (ctrl->status != LTESR_CC)
593 return NAND_STATUS_FAIL;
595 /* Use READ_STATUS command, but wait for the device to be ready */
598 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
599 (FIR_OP_RBW << FIR_OP1_SHIFT));
600 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
601 out_be32(&lbc->fbcr, 1);
602 set_addr(mtd, 0, 0, 0);
603 ctrl->read_bytes = 1;
605 fsl_elbc_run_command(mtd);
607 if (ctrl->status != LTESR_CC)
608 return NAND_STATUS_FAIL;
610 /* The chip always seems to report that it is
611 * write-protected, even when it is not.
613 out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
614 return fsl_elbc_read_byte(mtd);
617 static int fsl_elbc_read_page(struct mtd_info *mtd,
618 struct nand_chip *chip,
621 fsl_elbc_read_buf(mtd, buf, mtd->writesize);
622 fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
624 if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL)
625 mtd->ecc_stats.failed++;
630 /* ECC will be calculated automatically, and errors will be detected in
633 static void fsl_elbc_write_page(struct mtd_info *mtd,
634 struct nand_chip *chip,
637 struct fsl_elbc_mtd *priv = chip->priv;
638 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
640 fsl_elbc_write_buf(mtd, buf, mtd->writesize);
641 fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
643 ctrl->oob_poi = chip->oob_poi;
646 static struct fsl_elbc_ctrl *elbc_ctrl;
648 static void fsl_elbc_ctrl_init(void)
650 immap_t *im = (immap_t *)CFG_IMMR;
652 elbc_ctrl = kzalloc(sizeof(*elbc_ctrl), GFP_KERNEL);
656 elbc_ctrl->regs = &im->lbus;
658 /* clear event registers */
659 out_be32(&elbc_ctrl->regs->ltesr, LTESR_NAND_MASK);
660 out_be32(&elbc_ctrl->regs->lteatr, 0);
662 /* Enable interrupts for any detected events */
663 out_be32(&elbc_ctrl->regs->lteir, LTESR_NAND_MASK);
665 elbc_ctrl->read_bytes = 0;
666 elbc_ctrl->index = 0;
667 elbc_ctrl->addr = NULL;
670 int board_nand_init(struct nand_chip *nand)
672 struct fsl_elbc_mtd *priv;
676 fsl_elbc_ctrl_init();
681 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
685 priv->ctrl = elbc_ctrl;
686 priv->vbase = nand->IO_ADDR_R;
688 /* Find which chip select it is connected to. It'd be nice
689 * if we could pass more than one datum to the NAND driver...
691 for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
692 br = in_be32(&elbc_ctrl->regs->bank[priv->bank].br);
693 or = in_be32(&elbc_ctrl->regs->bank[priv->bank].or);
695 if ((br & BR_V) && (br & BR_MSEL) == BR_MS_FCM &&
696 (br & or & BR_BA) == (phys_addr_t)nand->IO_ADDR_R)
700 if (priv->bank >= MAX_BANKS) {
701 printf("fsl_elbc_nand: address did not match any "
706 elbc_ctrl->chips[priv->bank] = priv;
708 /* fill in nand_chip structure */
709 /* set up function call table */
710 nand->read_byte = fsl_elbc_read_byte;
711 nand->write_buf = fsl_elbc_write_buf;
712 nand->read_buf = fsl_elbc_read_buf;
713 nand->verify_buf = fsl_elbc_verify_buf;
714 nand->select_chip = fsl_elbc_select_chip;
715 nand->cmdfunc = fsl_elbc_cmdfunc;
716 nand->waitfunc = fsl_elbc_wait;
718 /* set up nand options */
719 nand->options = NAND_NO_READRDY | NAND_NO_AUTOINCR;
721 nand->controller = &elbc_ctrl->controller;
724 nand->ecc.read_page = fsl_elbc_read_page;
725 nand->ecc.write_page = fsl_elbc_write_page;
727 /* If CS Base Register selects full hardware ECC then use it */
728 if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
729 nand->ecc.mode = NAND_ECC_HW;
731 nand->ecc.layout = (priv->fmr & FMR_ECCM) ?
732 &fsl_elbc_oob_sp_eccm1 :
733 &fsl_elbc_oob_sp_eccm0;
735 nand->ecc.size = 512;
739 /* otherwise fall back to default software ECC */
740 nand->ecc.mode = NAND_ECC_SOFT;
743 priv->fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT);
745 /* adjust Option Register and ECC to match Flash page size */
746 if (or & OR_FCM_PGS) {
749 /* adjust ecc setup if needed */
750 if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
752 nand->ecc.layout = (priv->fmr & FMR_ECCM) ?
753 &fsl_elbc_oob_lp_eccm1 :
754 &fsl_elbc_oob_lp_eccm0;