git.sur5r.net Git - u-boot/blob - drivers/mtd/nand/fsl_elbc_nand.c

   1 /* Freescale Enhanced Local Bus Controller FCM NAND driver
   2  *
   3  * Copyright (c) 2006-2008 Freescale Semiconductor
   4  *
   5  * Authors: Nick Spence <nick.spence@freescale.com>,
   6  *          Scott Wood <scottwood@freescale.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21  */
  22
  23 #include <common.h>
  24 #include <malloc.h>
  25
  26 #include <linux/mtd/mtd.h>
  27 #include <linux/mtd/nand.h>
  28 #include <linux/mtd/nand_ecc.h>
  29
  30 #include <asm/io.h>
  31 #include <asm/errno.h>
  32
  33 #ifdef VERBOSE_DEBUG
  34 #define DEBUG_ELBC
  35 #define vdbg(format, arg...) printf("DEBUG: " format, ##arg)
  36 #else
  37 #define vdbg(format, arg...) do {} while (0)
  38 #endif
  39
  40 /* Can't use plain old DEBUG because the linux mtd
  41  * headers define it as a macro.
  42  */
  43 #ifdef DEBUG_ELBC
  44 #define dbg(format, arg...) printf("DEBUG: " format, ##arg)
  45 #else
  46 #define dbg(format, arg...) do {} while (0)
  47 #endif
  48
  49 #define MAX_BANKS 8
  50 #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
  51 #define FCM_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for FCM */
  52
  53 #define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
  54
  55 struct fsl_elbc_ctrl;
  56
  57 /* mtd information per set */
  58
  59 struct fsl_elbc_mtd {
  60         struct mtd_info mtd;
  61         struct nand_chip chip;
  62         struct fsl_elbc_ctrl *ctrl;
  63
  64         struct device *dev;
  65         int bank;               /* Chip select bank number           */
  66         u8 __iomem *vbase;      /* Chip select base virtual address  */
  67         int page_size;          /* NAND page size (0=512, 1=2048)    */
  68         unsigned int fmr;       /* FCM Flash Mode Register value     */
  69 };
  70
  71 /* overview of the fsl elbc controller */
  72
  73 struct fsl_elbc_ctrl {
  74         struct nand_hw_control controller;
  75         struct fsl_elbc_mtd *chips[MAX_BANKS];
  76
  77         /* device info */
  78         lbus83xx_t *regs;
  79         u8 __iomem *addr;        /* Address of assigned FCM buffer        */
  80         unsigned int page;       /* Last page written to / read from      */
  81         unsigned int read_bytes; /* Number of bytes read during command   */
  82         unsigned int column;     /* Saved column from SEQIN               */
  83         unsigned int index;      /* Pointer to next byte to 'read'        */
  84         unsigned int status;     /* status read from LTESR after last op  */
  85         unsigned int mdr;        /* UPM/FCM Data Register value           */
  86         unsigned int use_mdr;    /* Non zero if the MDR is to be set      */
  87         unsigned int oob;        /* Non zero if operating on OOB data     */
  88         uint8_t *oob_poi;        /* Place to write ECC after read back    */
  89 };
  90
  91 /* These map to the positions used by the FCM hardware ECC generator */
  92
  93 /* Small Page FLASH with FMR[ECCM] = 0 */
  94 static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = {
  95         .eccbytes = 3,
  96         .eccpos = {6, 7, 8},
  97         .oobfree = { {0, 5}, {9, 7} },
  98         .oobavail = 12,
  99 };
 100
 101 /* Small Page FLASH with FMR[ECCM] = 1 */
 102 static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = {
 103         .eccbytes = 3,
 104         .eccpos = {8, 9, 10},
 105         .oobfree = { {0, 5}, {6, 2}, {11, 5} },
 106         .oobavail = 12,
 107 };
 108
 109 /* Large Page FLASH with FMR[ECCM] = 0 */
 110 static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = {
 111         .eccbytes = 12,
 112         .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
 113         .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} },
 114         .oobavail = 48,
 115 };
 116
 117 /* Large Page FLASH with FMR[ECCM] = 1 */
 118 static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
 119         .eccbytes = 12,
 120         .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
 121         .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} },
 122         .oobavail = 48,
 123 };
 124
 125 /*
 126  * fsl_elbc_oob_lp_eccm* specify that LP NAND's OOB free area starts at offset
 127  * 1, so we have to adjust bad block pattern. This pattern should be used for
 128  * x8 chips only. So far hardware does not support x16 chips anyway.
 129  */
 130 static u8 scan_ff_pattern[] = { 0xff, };
 131
 132 static struct nand_bbt_descr largepage_memorybased = {
 133         .options = 0,
 134         .offs = 0,
 135         .len = 1,
 136         .pattern = scan_ff_pattern,
 137 };
 138
 139 /*=================================*/
 140
 141 /*
 142  * Set up the FCM hardware block and page address fields, and the fcm
 143  * structure addr field to point to the correct FCM buffer in memory
 144  */
 145 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 146 {
 147         struct nand_chip *chip = mtd->priv;
 148         struct fsl_elbc_mtd *priv = chip->priv;
 149         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 150         lbus83xx_t *lbc = ctrl->regs;
 151         int buf_num;
 152
 153         ctrl->page = page_addr;
 154
 155         if (priv->page_size) {
 156                 out_be32(&lbc->fbar, page_addr >> 6);
 157                 out_be32(&lbc->fpar,
 158                          ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
 159                          (oob ? FPAR_LP_MS : 0) | column);
 160                 buf_num = (page_addr & 1) << 2;
 161         } else {
 162                 out_be32(&lbc->fbar, page_addr >> 5);
 163                 out_be32(&lbc->fpar,
 164                          ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
 165                          (oob ? FPAR_SP_MS : 0) | column);
 166                 buf_num = page_addr & 7;
 167         }
 168
 169         ctrl->addr = priv->vbase + buf_num * 1024;
 170         ctrl->index = column;
 171
 172         /* for OOB data point to the second half of the buffer */
 173         if (oob)
 174                 ctrl->index += priv->page_size ? 2048 : 512;
 175
 176         vdbg("set_addr: bank=%d, ctrl->addr=0x%p (0x%p), "
 177              "index %x, pes %d ps %d\n",
 178              buf_num, ctrl->addr, priv->vbase, ctrl->index,
 179              chip->phys_erase_shift, chip->page_shift);
 180 }
 181
 182 /*
 183  * execute FCM command and wait for it to complete
 184  */
 185 static int fsl_elbc_run_command(struct mtd_info *mtd)
 186 {
 187         struct nand_chip *chip = mtd->priv;
 188         struct fsl_elbc_mtd *priv = chip->priv;
 189         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 190         lbus83xx_t *lbc = ctrl->regs;
 191         long long end_tick;
 192         u32 ltesr;
 193
 194         /* Setup the FMR[OP] to execute without write protection */
 195         out_be32(&lbc->fmr, priv->fmr | 3);
 196         if (ctrl->use_mdr)
 197                 out_be32(&lbc->mdr, ctrl->mdr);
 198
 199         vdbg("fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
 200              in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
 201         vdbg("fsl_elbc_run_command: fbar=%08x fpar=%08x "
 202              "fbcr=%08x bank=%d\n",
 203              in_be32(&lbc->fbar), in_be32(&lbc->fpar),
 204              in_be32(&lbc->fbcr), priv->bank);
 205
 206         /* execute special operation */
 207         out_be32(&lbc->lsor, priv->bank);
 208
 209         /* wait for FCM complete flag or timeout */
 210         end_tick = usec2ticks(FCM_TIMEOUT_MSECS * 1000) + get_ticks();
 211
 212         ltesr = 0;
 213         while (end_tick > get_ticks()) {
 214                 ltesr = in_be32(&lbc->ltesr);
 215                 if (ltesr & LTESR_CC)
 216                         break;
 217         }
 218
 219         ctrl->status = ltesr & LTESR_NAND_MASK;
 220         out_be32(&lbc->ltesr, ctrl->status);
 221         out_be32(&lbc->lteatr, 0);
 222
 223         /* store mdr value in case it was needed */
 224         if (ctrl->use_mdr)
 225                 ctrl->mdr = in_be32(&lbc->mdr);
 226
 227         ctrl->use_mdr = 0;
 228
 229         vdbg("fsl_elbc_run_command: stat=%08x mdr=%08x fmr=%08x\n",
 230              ctrl->status, ctrl->mdr, in_be32(&lbc->fmr));
 231
 232         /* returns 0 on success otherwise non-zero) */
 233         return ctrl->status == LTESR_CC ? 0 : -EIO;
 234 }
 235
 236 static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
 237 {
 238         struct fsl_elbc_mtd *priv = chip->priv;
 239         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 240         lbus83xx_t *lbc = ctrl->regs;
 241
 242         if (priv->page_size) {
 243                 out_be32(&lbc->fir,
 244                          (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 245                          (FIR_OP_CA  << FIR_OP1_SHIFT) |
 246                          (FIR_OP_PA  << FIR_OP2_SHIFT) |
 247                          (FIR_OP_CW1 << FIR_OP3_SHIFT) |
 248                          (FIR_OP_RBW << FIR_OP4_SHIFT));
 249
 250                 out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
 251                                     (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
 252         } else {
 253                 out_be32(&lbc->fir,
 254                          (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 255                          (FIR_OP_CA  << FIR_OP1_SHIFT) |
 256                          (FIR_OP_PA  << FIR_OP2_SHIFT) |
 257                          (FIR_OP_RBW << FIR_OP3_SHIFT));
 258
 259                 if (oob)
 260                         out_be32(&lbc->fcr,
 261                                  NAND_CMD_READOOB << FCR_CMD0_SHIFT);
 262                 else
 263                         out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
 264         }
 265 }
 266
 267 /* cmdfunc send commands to the FCM */
 268 static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 269                              int column, int page_addr)
 270 {
 271         struct nand_chip *chip = mtd->priv;
 272         struct fsl_elbc_mtd *priv = chip->priv;
 273         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 274         lbus83xx_t *lbc = ctrl->regs;
 275
 276         ctrl->use_mdr = 0;
 277
 278         /* clear the read buffer */
 279         ctrl->read_bytes = 0;
 280         if (command != NAND_CMD_PAGEPROG)
 281                 ctrl->index = 0;
 282
 283         switch (command) {
 284         /* READ0 and READ1 read the entire buffer to use hardware ECC. */
 285         case NAND_CMD_READ1:
 286                 column += 256;
 287
 288         /* fall-through */
 289         case NAND_CMD_READ0:
 290                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
 291                      " 0x%x, column: 0x%x.\n", page_addr, column);
 292
 293                 out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
 294                 set_addr(mtd, 0, page_addr, 0);
 295
 296                 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 297                 ctrl->index += column;
 298
 299                 fsl_elbc_do_read(chip, 0);
 300                 fsl_elbc_run_command(mtd);
 301                 return;
 302
 303         /* READOOB reads only the OOB because no ECC is performed. */
 304         case NAND_CMD_READOOB:
 305                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
 306                      " 0x%x, column: 0x%x.\n", page_addr, column);
 307
 308                 out_be32(&lbc->fbcr, mtd->oobsize - column);
 309                 set_addr(mtd, column, page_addr, 1);
 310
 311                 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 312
 313                 fsl_elbc_do_read(chip, 1);
 314                 fsl_elbc_run_command(mtd);
 315
 316                 return;
 317
 318         /* READID must read all 5 possible bytes while CEB is active */
 319         case NAND_CMD_READID:
 320                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_READID.\n");
 321
 322                 out_be32(&lbc->fir, (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 323                                     (FIR_OP_UA  << FIR_OP1_SHIFT) |
 324                                     (FIR_OP_RBW << FIR_OP2_SHIFT));
 325                 out_be32(&lbc->fcr, NAND_CMD_READID << FCR_CMD0_SHIFT);
 326                 /* 5 bytes for manuf, device and exts */
 327                 out_be32(&lbc->fbcr, 5);
 328                 ctrl->read_bytes = 5;
 329                 ctrl->use_mdr = 1;
 330                 ctrl->mdr = 0;
 331
 332                 set_addr(mtd, 0, 0, 0);
 333                 fsl_elbc_run_command(mtd);
 334                 return;
 335
 336         /* ERASE1 stores the block and page address */
 337         case NAND_CMD_ERASE1:
 338                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
 339                      "page_addr: 0x%x.\n", page_addr);
 340                 set_addr(mtd, 0, page_addr, 0);
 341                 return;
 342
 343         /* ERASE2 uses the block and page address from ERASE1 */
 344         case NAND_CMD_ERASE2:
 345                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
 346
 347                 out_be32(&lbc->fir,
 348                          (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 349                          (FIR_OP_PA  << FIR_OP1_SHIFT) |
 350                          (FIR_OP_CM1 << FIR_OP2_SHIFT));
 351
 352                 out_be32(&lbc->fcr,
 353                          (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
 354                          (NAND_CMD_ERASE2 << FCR_CMD1_SHIFT));
 355
 356                 out_be32(&lbc->fbcr, 0);
 357                 ctrl->read_bytes = 0;
 358
 359                 fsl_elbc_run_command(mtd);
 360                 return;
 361
 362         /* SEQIN sets up the addr buffer and all registers except the length */
 363         case NAND_CMD_SEQIN: {
 364                 u32 fcr;
 365                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
 366                      "page_addr: 0x%x, column: 0x%x.\n",
 367                      page_addr, column);
 368
 369                 ctrl->column = column;
 370                 ctrl->oob = 0;
 371
 372                 if (priv->page_size) {
 373                         fcr = (NAND_CMD_SEQIN << FCR_CMD0_SHIFT) |
 374                               (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT);
 375
 376                         out_be32(&lbc->fir,
 377                                  (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 378                                  (FIR_OP_CA  << FIR_OP1_SHIFT) |
 379                                  (FIR_OP_PA  << FIR_OP2_SHIFT) |
 380                                  (FIR_OP_WB  << FIR_OP3_SHIFT) |
 381                                  (FIR_OP_CW1 << FIR_OP4_SHIFT));
 382                 } else {
 383                         fcr = (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT) |
 384                               (NAND_CMD_SEQIN << FCR_CMD2_SHIFT);
 385
 386                         out_be32(&lbc->fir,
 387                                  (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 388                                  (FIR_OP_CM2 << FIR_OP1_SHIFT) |
 389                                  (FIR_OP_CA  << FIR_OP2_SHIFT) |
 390                                  (FIR_OP_PA  << FIR_OP3_SHIFT) |
 391                                  (FIR_OP_WB  << FIR_OP4_SHIFT) |
 392                                  (FIR_OP_CW1 << FIR_OP5_SHIFT));
 393
 394                         if (column >= mtd->writesize) {
 395                                 /* OOB area --> READOOB */
 396                                 column -= mtd->writesize;
 397                                 fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
 398                                 ctrl->oob = 1;
 399                         } else if (column < 256) {
 400                                 /* First 256 bytes --> READ0 */
 401                                 fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
 402                         } else {
 403                                 /* Second 256 bytes --> READ1 */
 404                                 fcr |= NAND_CMD_READ1 << FCR_CMD0_SHIFT;
 405                         }
 406                 }
 407
 408                 out_be32(&lbc->fcr, fcr);
 409                 set_addr(mtd, column, page_addr, ctrl->oob);
 410                 return;
 411         }
 412
 413         /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
 414         case NAND_CMD_PAGEPROG: {
 415                 int full_page;
 416                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
 417                      "writing %d bytes.\n", ctrl->index);
 418
 419                 /* if the write did not start at 0 or is not a full page
 420                  * then set the exact length, otherwise use a full page
 421                  * write so the HW generates the ECC.
 422                  */
 423                 if (ctrl->oob || ctrl->column != 0 ||
 424                     ctrl->index != mtd->writesize + mtd->oobsize) {
 425                         out_be32(&lbc->fbcr, ctrl->index);
 426                         full_page = 0;
 427                 } else {
 428                         out_be32(&lbc->fbcr, 0);
 429                         full_page = 1;
 430                 }
 431
 432                 fsl_elbc_run_command(mtd);
 433
 434                 /* Read back the page in order to fill in the ECC for the
 435                  * caller.  Is this really needed?
 436                  */
 437                 if (full_page && ctrl->oob_poi) {
 438                         out_be32(&lbc->fbcr, 3);
 439                         set_addr(mtd, 6, page_addr, 1);
 440
 441                         ctrl->read_bytes = mtd->writesize + 9;
 442
 443                         fsl_elbc_do_read(chip, 1);
 444                         fsl_elbc_run_command(mtd);
 445
 446                         memcpy_fromio(ctrl->oob_poi + 6,
 447                                       &ctrl->addr[ctrl->index], 3);
 448                         ctrl->index += 3;
 449                 }
 450
 451                 ctrl->oob_poi = NULL;
 452                 return;
 453         }
 454
 455         /* CMD_STATUS must read the status byte while CEB is active */
 456         /* Note - it does not wait for the ready line */
 457         case NAND_CMD_STATUS:
 458                 out_be32(&lbc->fir,
 459                          (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 460                          (FIR_OP_RBW << FIR_OP1_SHIFT));
 461                 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
 462                 out_be32(&lbc->fbcr, 1);
 463                 set_addr(mtd, 0, 0, 0);
 464                 ctrl->read_bytes = 1;
 465
 466                 fsl_elbc_run_command(mtd);
 467
 468                 /* The chip always seems to report that it is
 469                  * write-protected, even when it is not.
 470                  */
 471                 out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
 472                 return;
 473
 474         /* RESET without waiting for the ready line */
 475         case NAND_CMD_RESET:
 476                 dbg("fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
 477                 out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
 478                 out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
 479                 fsl_elbc_run_command(mtd);
 480                 return;
 481
 482         default:
 483                 printf("fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
 484                         command);
 485         }
 486 }
 487
 488 static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
 489 {
 490         /* The hardware does not seem to support multiple
 491          * chips per bank.
 492          */
 493 }
 494
 495 /*
 496  * Write buf to the FCM Controller Data Buffer
 497  */
 498 static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 499 {
 500         struct nand_chip *chip = mtd->priv;
 501         struct fsl_elbc_mtd *priv = chip->priv;
 502         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 503         unsigned int bufsize = mtd->writesize + mtd->oobsize;
 504
 505         if (len <= 0) {
 506                 printf("write_buf of %d bytes", len);
 507                 ctrl->status = 0;
 508                 return;
 509         }
 510
 511         if ((unsigned int)len > bufsize - ctrl->index) {
 512                 printf("write_buf beyond end of buffer "
 513                        "(%d requested, %u available)\n",
 514                        len, bufsize - ctrl->index);
 515                 len = bufsize - ctrl->index;
 516         }
 517
 518         memcpy_toio(&ctrl->addr[ctrl->index], buf, len);
 519         /*
 520          * This is workaround for the weird elbc hangs during nand write,
 521          * Scott Wood says: "...perhaps difference in how long it takes a
 522          * write to make it through the localbus compared to a write to IMMR
 523          * is causing problems, and sync isn't helping for some reason."
 524          * Reading back the last byte helps though.
 525          */
 526         in_8(&ctrl->addr[ctrl->index] + len - 1);
 527
 528         ctrl->index += len;
 529 }
 530
 531 /*
 532  * read a byte from either the FCM hardware buffer if it has any data left
 533  * otherwise issue a command to read a single byte.
 534  */
 535 static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
 536 {
 537         struct nand_chip *chip = mtd->priv;
 538         struct fsl_elbc_mtd *priv = chip->priv;
 539         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 540
 541         /* If there are still bytes in the FCM, then use the next byte. */
 542         if (ctrl->index < ctrl->read_bytes)
 543                 return in_8(&ctrl->addr[ctrl->index++]);
 544
 545         printf("read_byte beyond end of buffer\n");
 546         return ERR_BYTE;
 547 }
 548
 549 /*
 550  * Read from the FCM Controller Data Buffer
 551  */
 552 static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 553 {
 554         struct nand_chip *chip = mtd->priv;
 555         struct fsl_elbc_mtd *priv = chip->priv;
 556         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 557         int avail;
 558
 559         if (len < 0)
 560                 return;
 561
 562         avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
 563         memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail);
 564         ctrl->index += avail;
 565
 566         if (len > avail)
 567                 printf("read_buf beyond end of buffer "
 568                        "(%d requested, %d available)\n",
 569                        len, avail);
 570 }
 571
 572 /*
 573  * Verify buffer against the FCM Controller Data Buffer
 574  */
 575 static int fsl_elbc_verify_buf(struct mtd_info *mtd,
 576                                const u_char *buf, int len)
 577 {
 578         struct nand_chip *chip = mtd->priv;
 579         struct fsl_elbc_mtd *priv = chip->priv;
 580         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 581         int i;
 582
 583         if (len < 0) {
 584                 printf("write_buf of %d bytes", len);
 585                 return -EINVAL;
 586         }
 587
 588         if ((unsigned int)len > ctrl->read_bytes - ctrl->index) {
 589                 printf("verify_buf beyond end of buffer "
 590                        "(%d requested, %u available)\n",
 591                        len, ctrl->read_bytes - ctrl->index);
 592
 593                 ctrl->index = ctrl->read_bytes;
 594                 return -EINVAL;
 595         }
 596
 597         for (i = 0; i < len; i++)
 598                 if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i])
 599                         break;
 600
 601         ctrl->index += len;
 602         return i == len && ctrl->status == LTESR_CC ? 0 : -EIO;
 603 }
 604
 605 /* This function is called after Program and Erase Operations to
 606  * check for success or failure.
 607  */
 608 static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 609 {
 610         struct fsl_elbc_mtd *priv = chip->priv;
 611         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 612         lbus83xx_t *lbc = ctrl->regs;
 613
 614         if (ctrl->status != LTESR_CC)
 615                 return NAND_STATUS_FAIL;
 616
 617         /* Use READ_STATUS command, but wait for the device to be ready */
 618         ctrl->use_mdr = 0;
 619         out_be32(&lbc->fir,
 620                  (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 621                  (FIR_OP_RBW << FIR_OP1_SHIFT));
 622         out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
 623         out_be32(&lbc->fbcr, 1);
 624         set_addr(mtd, 0, 0, 0);
 625         ctrl->read_bytes = 1;
 626
 627         fsl_elbc_run_command(mtd);
 628
 629         if (ctrl->status != LTESR_CC)
 630                 return NAND_STATUS_FAIL;
 631
 632         /* The chip always seems to report that it is
 633          * write-protected, even when it is not.
 634          */
 635         out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
 636         return fsl_elbc_read_byte(mtd);
 637 }
 638
 639 static int fsl_elbc_read_page(struct mtd_info *mtd,
 640                               struct nand_chip *chip,
 641                               uint8_t *buf)
 642 {
 643         fsl_elbc_read_buf(mtd, buf, mtd->writesize);
 644         fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
 645
 646         if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL)
 647                 mtd->ecc_stats.failed++;
 648
 649         return 0;
 650 }
 651
 652 /* ECC will be calculated automatically, and errors will be detected in
 653  * waitfunc.
 654  */
 655 static void fsl_elbc_write_page(struct mtd_info *mtd,
 656                                 struct nand_chip *chip,
 657                                 const uint8_t *buf)
 658 {
 659         struct fsl_elbc_mtd *priv = chip->priv;
 660         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 661
 662         fsl_elbc_write_buf(mtd, buf, mtd->writesize);
 663         fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 664
 665         ctrl->oob_poi = chip->oob_poi;
 666 }
 667
 668 static struct fsl_elbc_ctrl *elbc_ctrl;
 669
 670 static void fsl_elbc_ctrl_init(void)
 671 {
 672         immap_t *im = (immap_t *)CFG_IMMR;
 673
 674         elbc_ctrl = kzalloc(sizeof(*elbc_ctrl), GFP_KERNEL);
 675         if (!elbc_ctrl)
 676                 return;
 677
 678         elbc_ctrl->regs = &im->lbus;
 679
 680         /* clear event registers */
 681         out_be32(&elbc_ctrl->regs->ltesr, LTESR_NAND_MASK);
 682         out_be32(&elbc_ctrl->regs->lteatr, 0);
 683
 684         /* Enable interrupts for any detected events */
 685         out_be32(&elbc_ctrl->regs->lteir, LTESR_NAND_MASK);
 686
 687         elbc_ctrl->read_bytes = 0;
 688         elbc_ctrl->index = 0;
 689         elbc_ctrl->addr = NULL;
 690 }
 691
 692 int board_nand_init(struct nand_chip *nand)
 693 {
 694         struct fsl_elbc_mtd *priv;
 695         uint32_t br, or;
 696
 697         if (!elbc_ctrl) {
 698                 fsl_elbc_ctrl_init();
 699                 if (!elbc_ctrl)
 700                         return -1;
 701         }
 702
 703         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 704         if (!priv)
 705                 return -ENOMEM;
 706
 707         priv->ctrl = elbc_ctrl;
 708         priv->vbase = nand->IO_ADDR_R;
 709
 710         /* Find which chip select it is connected to.  It'd be nice
 711          * if we could pass more than one datum to the NAND driver...
 712          */
 713         for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
 714                 br = in_be32(&elbc_ctrl->regs->bank[priv->bank].br);
 715                 or = in_be32(&elbc_ctrl->regs->bank[priv->bank].or);
 716
 717                 if ((br & BR_V) && (br & BR_MSEL) == BR_MS_FCM &&
 718                     (br & or & BR_BA) == (phys_addr_t)nand->IO_ADDR_R)
 719                         break;
 720         }
 721
 722         if (priv->bank >= MAX_BANKS) {
 723                 printf("fsl_elbc_nand: address did not match any "
 724                        "chip selects\n");
 725                 return -ENODEV;
 726         }
 727
 728         elbc_ctrl->chips[priv->bank] = priv;
 729
 730         /* fill in nand_chip structure */
 731         /* set up function call table */
 732         nand->read_byte = fsl_elbc_read_byte;
 733         nand->write_buf = fsl_elbc_write_buf;
 734         nand->read_buf = fsl_elbc_read_buf;
 735         nand->verify_buf = fsl_elbc_verify_buf;
 736         nand->select_chip = fsl_elbc_select_chip;
 737         nand->cmdfunc = fsl_elbc_cmdfunc;
 738         nand->waitfunc = fsl_elbc_wait;
 739
 740         /* set up nand options */
 741         nand->options = NAND_NO_READRDY | NAND_NO_AUTOINCR;
 742
 743         nand->controller = &elbc_ctrl->controller;
 744         nand->priv = priv;
 745
 746         nand->ecc.read_page = fsl_elbc_read_page;
 747         nand->ecc.write_page = fsl_elbc_write_page;
 748
 749         /* If CS Base Register selects full hardware ECC then use it */
 750         if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
 751                 nand->ecc.mode = NAND_ECC_HW;
 752
 753                 nand->ecc.layout = (priv->fmr & FMR_ECCM) ?
 754                                    &fsl_elbc_oob_sp_eccm1 :
 755                                    &fsl_elbc_oob_sp_eccm0;
 756
 757                 nand->ecc.size = 512;
 758                 nand->ecc.bytes = 3;
 759                 nand->ecc.steps = 1;
 760         } else {
 761                 /* otherwise fall back to default software ECC */
 762                 nand->ecc.mode = NAND_ECC_SOFT;
 763         }
 764
 765         priv->fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT);
 766
 767         /* Large-page-specific setup */
 768         if (or & OR_FCM_PGS) {
 769                 priv->page_size = 1;
 770                 nand->badblock_pattern = &largepage_memorybased;
 771
 772                 /* adjust ecc setup if needed */
 773                 if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
 774                         nand->ecc.steps = 4;
 775                         nand->ecc.layout = (priv->fmr & FMR_ECCM) ?
 776                                            &fsl_elbc_oob_lp_eccm1 :
 777                                            &fsl_elbc_oob_lp_eccm0;
 778                 }
 779         }
 780
 781         return 0;
 782 }