1 // SPDX-License-Identifier: GPL-2.0+
3 * NAND boot for Freescale Enhanced Local Bus Controller, Flash Control Machine
5 * (C) Copyright 2006-2008
6 * Stefan Roese, DENX Software Engineering, sr@denx.de.
8 * Copyright (c) 2008 Freescale Semiconductor, Inc.
9 * Author: Scott Wood <scottwood@freescale.com>
14 #include <asm/fsl_lbc.h>
17 #define WINDOW_SIZE 8192
19 static void nand_wait(void)
21 fsl_lbc_t *regs = LBC_BASE_ADDR;
24 uint32_t status = in_be32(®s->ltesr);
30 puts("read failed (ltesr)\n");
36 #ifdef CONFIG_TPL_BUILD
37 int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
39 static int nand_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
42 fsl_lbc_t *regs = LBC_BASE_ADDR;
43 uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
44 const int large = CONFIG_SYS_NAND_OR_PRELIM & OR_FCM_PGS;
45 const int block_shift = large ? 17 : 14;
46 const int block_size = 1 << block_shift;
47 const int page_size = large ? 2048 : 512;
48 const int bad_marker = large ? page_size + 0 : page_size + 5;
49 int fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT) | 2;
53 if (offs & (block_size - 1)) {
60 out_be32(®s->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
61 (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
63 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
64 (FIR_OP_CA << FIR_OP1_SHIFT) |
65 (FIR_OP_PA << FIR_OP2_SHIFT) |
66 (FIR_OP_CW1 << FIR_OP3_SHIFT) |
67 (FIR_OP_RBW << FIR_OP4_SHIFT));
69 out_be32(®s->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
71 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
72 (FIR_OP_CA << FIR_OP1_SHIFT) |
73 (FIR_OP_PA << FIR_OP2_SHIFT) |
74 (FIR_OP_RBW << FIR_OP3_SHIFT));
77 out_be32(®s->fbcr, 0);
78 clrsetbits_be32(®s->bank[0].br, BR_DECC, BR_DECC_CHK_GEN);
80 while (pos < uboot_size) {
82 out_be32(®s->fbar, offs >> block_shift);
86 unsigned int page_offs = (offs & (block_size - 1)) << 1;
88 out_be32(®s->ltesr, ~0);
89 out_be32(®s->lteatr, 0);
90 out_be32(®s->fpar, page_offs);
91 out_be32(®s->fmr, fmr);
92 out_be32(®s->lsor, 0);
95 page_offs %= WINDOW_SIZE;
98 * If either of the first two pages are marked bad,
99 * continue to the next block.
101 if (i++ < 2 && buf[page_offs + bad_marker] != 0xff) {
103 offs = (offs + block_size) & ~(block_size - 1);
104 pos &= ~(block_size - 1);
108 for (j = 0; j < page_size; j++)
109 dst[pos + j] = buf[page_offs + j];
113 } while ((offs & (block_size - 1)) && (pos < uboot_size));
120 * Defines a static function nand_load_image() here, because non-static makes
121 * the code too large for certain SPLs(minimal SPL, maximum size <= 4Kbytes)
123 #ifndef CONFIG_TPL_BUILD
124 #define nand_spl_load_image(offs, uboot_size, vdst) \
125 nand_load_image(offs, uboot_size, vdst)
129 * The main entry for NAND booting. It's necessary that SDRAM is already
130 * configured and available since this code loads the main U-Boot image
131 * from NAND into SDRAM and starts it from there.
135 __attribute__((noreturn)) void (*uboot)(void);
137 * Load U-Boot image from NAND into RAM
139 nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
140 CONFIG_SYS_NAND_U_BOOT_SIZE,
141 (void *)CONFIG_SYS_NAND_U_BOOT_DST);
143 #ifdef CONFIG_NAND_ENV_DST
144 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
145 (void *)CONFIG_NAND_ENV_DST);
147 #ifdef CONFIG_ENV_OFFSET_REDUND
148 nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
149 (void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
153 #ifdef CONFIG_SPL_FLUSH_IMAGE
155 * Clean d-cache and invalidate i-cache, to
156 * make sure that no stale data is executed.
158 flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
161 puts("transfering control\n");
163 * Jump to U-Boot image
165 uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;