git.sur5r.net Git - u-boot/blob - drivers/mtd/nand/fsl_ifc_nand.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /* Integrated Flash Controller NAND Machine Driver
   3  *
   4  * Copyright (c) 2012 Freescale Semiconductor, Inc
   5  *
   6  * Authors: Dipen Dudhat <Dipen.Dudhat@freescale.com>
   7  */
   8
   9 #include <common.h>
  10 #include <malloc.h>
  11 #include <nand.h>
  12
  13 #include <linux/mtd/mtd.h>
  14 #include <linux/mtd/rawnand.h>
  15 #include <linux/mtd/nand_ecc.h>
  16
  17 #include <asm/io.h>
  18 #include <linux/errno.h>
  19 #include <fsl_ifc.h>
  20
  21 #ifndef CONFIG_SYS_FSL_IFC_BANK_COUNT
  22 #define CONFIG_SYS_FSL_IFC_BANK_COUNT   4
  23 #endif
  24
  25 #define MAX_BANKS       CONFIG_SYS_FSL_IFC_BANK_COUNT
  26 #define ERR_BYTE        0xFF /* Value returned for read bytes
  27                                 when read failed */
  28
  29 struct fsl_ifc_ctrl;
  30
  31 /* mtd information per set */
  32 struct fsl_ifc_mtd {
  33         struct nand_chip chip;
  34         struct fsl_ifc_ctrl *ctrl;
  35
  36         struct device *dev;
  37         int bank;               /* Chip select bank number                */
  38         unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
  39         u8 __iomem *vbase;      /* Chip select base virtual address       */
  40 };
  41
  42 /* overview of the fsl ifc controller */
  43 struct fsl_ifc_ctrl {
  44         struct nand_hw_control controller;
  45         struct fsl_ifc_mtd *chips[MAX_BANKS];
  46
  47         /* device info */
  48         struct fsl_ifc regs;
  49         void __iomem *addr;      /* Address of assigned IFC buffer        */
  50         unsigned int page;       /* Last page written to / read from      */
  51         unsigned int read_bytes; /* Number of bytes read during command   */
  52         unsigned int column;     /* Saved column from SEQIN               */
  53         unsigned int index;      /* Pointer to next byte to 'read'        */
  54         unsigned int status;     /* status read from NEESR after last op  */
  55         unsigned int oob;        /* Non zero if operating on OOB data     */
  56         unsigned int eccread;    /* Non zero for a full-page ECC read     */
  57 };
  58
  59 static struct fsl_ifc_ctrl *ifc_ctrl;
  60
  61 /* 512-byte page with 4-bit ECC, 8-bit */
  62 static struct nand_ecclayout oob_512_8bit_ecc4 = {
  63         .eccbytes = 8,
  64         .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
  65         .oobfree = { {0, 5}, {6, 2} },
  66 };
  67
  68 /* 512-byte page with 4-bit ECC, 16-bit */
  69 static struct nand_ecclayout oob_512_16bit_ecc4 = {
  70         .eccbytes = 8,
  71         .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
  72         .oobfree = { {2, 6}, },
  73 };
  74
  75 /* 2048-byte page size with 4-bit ECC */
  76 static struct nand_ecclayout oob_2048_ecc4 = {
  77         .eccbytes = 32,
  78         .eccpos = {
  79                 8, 9, 10, 11, 12, 13, 14, 15,
  80                 16, 17, 18, 19, 20, 21, 22, 23,
  81                 24, 25, 26, 27, 28, 29, 30, 31,
  82                 32, 33, 34, 35, 36, 37, 38, 39,
  83         },
  84         .oobfree = { {2, 6}, {40, 24} },
  85 };
  86
  87 /* 4096-byte page size with 4-bit ECC */
  88 static struct nand_ecclayout oob_4096_ecc4 = {
  89         .eccbytes = 64,
  90         .eccpos = {
  91                 8, 9, 10, 11, 12, 13, 14, 15,
  92                 16, 17, 18, 19, 20, 21, 22, 23,
  93                 24, 25, 26, 27, 28, 29, 30, 31,
  94                 32, 33, 34, 35, 36, 37, 38, 39,
  95                 40, 41, 42, 43, 44, 45, 46, 47,
  96                 48, 49, 50, 51, 52, 53, 54, 55,
  97                 56, 57, 58, 59, 60, 61, 62, 63,
  98                 64, 65, 66, 67, 68, 69, 70, 71,
  99         },
 100         .oobfree = { {2, 6}, {72, 56} },
 101 };
 102
 103 /* 4096-byte page size with 8-bit ECC -- requires 218-byte OOB */
 104 static struct nand_ecclayout oob_4096_ecc8 = {
 105         .eccbytes = 128,
 106         .eccpos = {
 107                 8, 9, 10, 11, 12, 13, 14, 15,
 108                 16, 17, 18, 19, 20, 21, 22, 23,
 109                 24, 25, 26, 27, 28, 29, 30, 31,
 110                 32, 33, 34, 35, 36, 37, 38, 39,
 111                 40, 41, 42, 43, 44, 45, 46, 47,
 112                 48, 49, 50, 51, 52, 53, 54, 55,
 113                 56, 57, 58, 59, 60, 61, 62, 63,
 114                 64, 65, 66, 67, 68, 69, 70, 71,
 115                 72, 73, 74, 75, 76, 77, 78, 79,
 116                 80, 81, 82, 83, 84, 85, 86, 87,
 117                 88, 89, 90, 91, 92, 93, 94, 95,
 118                 96, 97, 98, 99, 100, 101, 102, 103,
 119                 104, 105, 106, 107, 108, 109, 110, 111,
 120                 112, 113, 114, 115, 116, 117, 118, 119,
 121                 120, 121, 122, 123, 124, 125, 126, 127,
 122                 128, 129, 130, 131, 132, 133, 134, 135,
 123         },
 124         .oobfree = { {2, 6}, {136, 82} },
 125 };
 126
 127 /* 8192-byte page size with 4-bit ECC */
 128 static struct nand_ecclayout oob_8192_ecc4 = {
 129         .eccbytes = 128,
 130         .eccpos = {
 131                 8, 9, 10, 11, 12, 13, 14, 15,
 132                 16, 17, 18, 19, 20, 21, 22, 23,
 133                 24, 25, 26, 27, 28, 29, 30, 31,
 134                 32, 33, 34, 35, 36, 37, 38, 39,
 135                 40, 41, 42, 43, 44, 45, 46, 47,
 136                 48, 49, 50, 51, 52, 53, 54, 55,
 137                 56, 57, 58, 59, 60, 61, 62, 63,
 138                 64, 65, 66, 67, 68, 69, 70, 71,
 139                 72, 73, 74, 75, 76, 77, 78, 79,
 140                 80, 81, 82, 83, 84, 85, 86, 87,
 141                 88, 89, 90, 91, 92, 93, 94, 95,
 142                 96, 97, 98, 99, 100, 101, 102, 103,
 143                 104, 105, 106, 107, 108, 109, 110, 111,
 144                 112, 113, 114, 115, 116, 117, 118, 119,
 145                 120, 121, 122, 123, 124, 125, 126, 127,
 146                 128, 129, 130, 131, 132, 133, 134, 135,
 147         },
 148         .oobfree = { {2, 6}, {136, 208} },
 149 };
 150
 151 /* 8192-byte page size with 8-bit ECC -- requires 218-byte OOB */
 152 static struct nand_ecclayout oob_8192_ecc8 = {
 153         .eccbytes = 256,
 154         .eccpos = {
 155                 8, 9, 10, 11, 12, 13, 14, 15,
 156                 16, 17, 18, 19, 20, 21, 22, 23,
 157                 24, 25, 26, 27, 28, 29, 30, 31,
 158                 32, 33, 34, 35, 36, 37, 38, 39,
 159                 40, 41, 42, 43, 44, 45, 46, 47,
 160                 48, 49, 50, 51, 52, 53, 54, 55,
 161                 56, 57, 58, 59, 60, 61, 62, 63,
 162                 64, 65, 66, 67, 68, 69, 70, 71,
 163                 72, 73, 74, 75, 76, 77, 78, 79,
 164                 80, 81, 82, 83, 84, 85, 86, 87,
 165                 88, 89, 90, 91, 92, 93, 94, 95,
 166                 96, 97, 98, 99, 100, 101, 102, 103,
 167                 104, 105, 106, 107, 108, 109, 110, 111,
 168                 112, 113, 114, 115, 116, 117, 118, 119,
 169                 120, 121, 122, 123, 124, 125, 126, 127,
 170                 128, 129, 130, 131, 132, 133, 134, 135,
 171                 136, 137, 138, 139, 140, 141, 142, 143,
 172                 144, 145, 146, 147, 148, 149, 150, 151,
 173                 152, 153, 154, 155, 156, 157, 158, 159,
 174                 160, 161, 162, 163, 164, 165, 166, 167,
 175                 168, 169, 170, 171, 172, 173, 174, 175,
 176                 176, 177, 178, 179, 180, 181, 182, 183,
 177                 184, 185, 186, 187, 188, 189, 190, 191,
 178                 192, 193, 194, 195, 196, 197, 198, 199,
 179                 200, 201, 202, 203, 204, 205, 206, 207,
 180                 208, 209, 210, 211, 212, 213, 214, 215,
 181                 216, 217, 218, 219, 220, 221, 222, 223,
 182                 224, 225, 226, 227, 228, 229, 230, 231,
 183                 232, 233, 234, 235, 236, 237, 238, 239,
 184                 240, 241, 242, 243, 244, 245, 246, 247,
 185                 248, 249, 250, 251, 252, 253, 254, 255,
 186                 256, 257, 258, 259, 260, 261, 262, 263,
 187         },
 188         .oobfree = { {2, 6}, {264, 80} },
 189 };
 190
 191 /*
 192  * Generic flash bbt descriptors
 193  */
 194 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
 195 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
 196
 197 static struct nand_bbt_descr bbt_main_descr = {
 198         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 199                    NAND_BBT_2BIT | NAND_BBT_VERSION,
 200         .offs = 2, /* 0 on 8-bit small page */
 201         .len = 4,
 202         .veroffs = 6,
 203         .maxblocks = 4,
 204         .pattern = bbt_pattern,
 205 };
 206
 207 static struct nand_bbt_descr bbt_mirror_descr = {
 208         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 209                    NAND_BBT_2BIT | NAND_BBT_VERSION,
 210         .offs = 2, /* 0 on 8-bit small page */
 211         .len = 4,
 212         .veroffs = 6,
 213         .maxblocks = 4,
 214         .pattern = mirror_pattern,
 215 };
 216
 217 /*
 218  * Set up the IFC hardware block and page address fields, and the ifc nand
 219  * structure addr field to point to the correct IFC buffer in memory
 220  */
 221 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 222 {
 223         struct nand_chip *chip = mtd_to_nand(mtd);
 224         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 225         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 226         struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
 227         int buf_num;
 228
 229         ctrl->page = page_addr;
 230
 231         /* Program ROW0/COL0 */
 232         ifc_out32(&ifc->ifc_nand.row0, page_addr);
 233         ifc_out32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
 234
 235         buf_num = page_addr & priv->bufnum_mask;
 236
 237         ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
 238         ctrl->index = column;
 239
 240         /* for OOB data point to the second half of the buffer */
 241         if (oob)
 242                 ctrl->index += mtd->writesize;
 243 }
 244
 245 static int is_blank(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
 246                     unsigned int bufnum)
 247 {
 248         struct nand_chip *chip = mtd_to_nand(mtd);
 249         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 250         u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2);
 251         u32 __iomem *main = (u32 *)addr;
 252         u8 __iomem *oob = addr + mtd->writesize;
 253         int i;
 254
 255         for (i = 0; i < mtd->writesize / 4; i++) {
 256                 if (__raw_readl(&main[i]) != 0xffffffff)
 257                         return 0;
 258         }
 259
 260         for (i = 0; i < chip->ecc.layout->eccbytes; i++) {
 261                 int pos = chip->ecc.layout->eccpos[i];
 262
 263                 if (__raw_readb(&oob[pos]) != 0xff)
 264                         return 0;
 265         }
 266
 267         return 1;
 268 }
 269
 270 /* returns nonzero if entire page is blank */
 271 static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
 272                           u32 *eccstat, unsigned int bufnum)
 273 {
 274         u32 reg = eccstat[bufnum / 4];
 275         int errors;
 276
 277         errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
 278
 279         return errors;
 280 }
 281
 282 /*
 283  * execute IFC NAND command and wait for it to complete
 284  */
 285 static int fsl_ifc_run_command(struct mtd_info *mtd)
 286 {
 287         struct nand_chip *chip = mtd_to_nand(mtd);
 288         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 289         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 290         struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
 291         u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
 292         u32 time_start;
 293         u32 eccstat[8] = {0};
 294         int i;
 295
 296         /* set the chip select for NAND Transaction */
 297         ifc_out32(&ifc->ifc_nand.nand_csel, priv->bank << IFC_NAND_CSEL_SHIFT);
 298
 299         /* start read/write seq */
 300         ifc_out32(&ifc->ifc_nand.nandseq_strt,
 301                   IFC_NAND_SEQ_STRT_FIR_STRT);
 302
 303         /* wait for NAND Machine complete flag or timeout */
 304         time_start = get_timer(0);
 305
 306         while (get_timer(time_start) < timeo) {
 307                 ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
 308
 309                 if (ctrl->status & IFC_NAND_EVTER_STAT_OPC)
 310                         break;
 311         }
 312
 313         ifc_out32(&ifc->ifc_nand.nand_evter_stat, ctrl->status);
 314
 315         if (ctrl->status & IFC_NAND_EVTER_STAT_FTOER)
 316                 printf("%s: Flash Time Out Error\n", __func__);
 317         if (ctrl->status & IFC_NAND_EVTER_STAT_WPER)
 318                 printf("%s: Write Protect Error\n", __func__);
 319
 320         if (ctrl->eccread) {
 321                 int errors;
 322                 int bufnum = ctrl->page & priv->bufnum_mask;
 323                 int sector = bufnum * chip->ecc.steps;
 324                 int sector_end = sector + chip->ecc.steps - 1;
 325
 326                 for (i = sector / 4; i <= sector_end / 4; i++) {
 327                         if (i >= ARRAY_SIZE(eccstat)) {
 328                                 printf("%s: eccstat too small for %d\n",
 329                                        __func__, i);
 330                                 return -EIO;
 331                         }
 332
 333                         eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]);
 334                 }
 335
 336                 for (i = sector; i <= sector_end; i++) {
 337                         errors = check_read_ecc(mtd, ctrl, eccstat, i);
 338
 339                         if (errors == 15) {
 340                                 /*
 341                                  * Uncorrectable error.
 342                                  * OK only if the whole page is blank.
 343                                  *
 344                                  * We disable ECCER reporting due to erratum
 345                                  * IFC-A002770 -- so report it now if we
 346                                  * see an uncorrectable error in ECCSTAT.
 347                                  */
 348                                 if (!is_blank(mtd, ctrl, bufnum))
 349                                         ctrl->status |=
 350                                                 IFC_NAND_EVTER_STAT_ECCER;
 351                                 break;
 352                         }
 353
 354                         mtd->ecc_stats.corrected += errors;
 355                 }
 356
 357                 ctrl->eccread = 0;
 358         }
 359
 360         /* returns 0 on success otherwise non-zero) */
 361         return ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO;
 362 }
 363
 364 static void fsl_ifc_do_read(struct nand_chip *chip,
 365                             int oob,
 366                             struct mtd_info *mtd)
 367 {
 368         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 369         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 370         struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
 371
 372         /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
 373         if (mtd->writesize > 512) {
 374                 ifc_out32(&ifc->ifc_nand.nand_fir0,
 375                           (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 376                           (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 377                           (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
 378                           (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
 379                           (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
 380                 ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
 381
 382                 ifc_out32(&ifc->ifc_nand.nand_fcr0,
 383                           (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
 384                           (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
 385         } else {
 386                 ifc_out32(&ifc->ifc_nand.nand_fir0,
 387                           (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 388                           (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 389                           (IFC_FIR_OP_RA0  << IFC_NAND_FIR0_OP2_SHIFT) |
 390                           (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
 391
 392                 if (oob)
 393                         ifc_out32(&ifc->ifc_nand.nand_fcr0,
 394                                   NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
 395                 else
 396                         ifc_out32(&ifc->ifc_nand.nand_fcr0,
 397                                   NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
 398         }
 399 }
 400
 401 /* cmdfunc send commands to the IFC NAND Machine */
 402 static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 403                              int column, int page_addr)
 404 {
 405         struct nand_chip *chip = mtd_to_nand(mtd);
 406         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 407         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 408         struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
 409
 410         /* clear the read buffer */
 411         ctrl->read_bytes = 0;
 412         if (command != NAND_CMD_PAGEPROG)
 413                 ctrl->index = 0;
 414
 415         switch (command) {
 416         /* READ0 read the entire buffer to use hardware ECC. */
 417         case NAND_CMD_READ0: {
 418                 ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
 419                 set_addr(mtd, 0, page_addr, 0);
 420
 421                 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 422                 ctrl->index += column;
 423
 424                 if (chip->ecc.mode == NAND_ECC_HW)
 425                         ctrl->eccread = 1;
 426
 427                 fsl_ifc_do_read(chip, 0, mtd);
 428                 fsl_ifc_run_command(mtd);
 429                 return;
 430         }
 431
 432         /* READOOB reads only the OOB because no ECC is performed. */
 433         case NAND_CMD_READOOB:
 434                 ifc_out32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
 435                 set_addr(mtd, column, page_addr, 1);
 436
 437                 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 438
 439                 fsl_ifc_do_read(chip, 1, mtd);
 440                 fsl_ifc_run_command(mtd);
 441
 442                 return;
 443
 444         /* READID must read all possible bytes while CEB is active */
 445         case NAND_CMD_READID:
 446         case NAND_CMD_PARAM: {
 447                 int timing = IFC_FIR_OP_RB;
 448                 if (command == NAND_CMD_PARAM)
 449                         timing = IFC_FIR_OP_RBCD;
 450
 451                 ifc_out32(&ifc->ifc_nand.nand_fir0,
 452                           (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 453                           (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
 454                           (timing << IFC_NAND_FIR0_OP2_SHIFT));
 455                 ifc_out32(&ifc->ifc_nand.nand_fcr0,
 456                           command << IFC_NAND_FCR0_CMD0_SHIFT);
 457                 ifc_out32(&ifc->ifc_nand.row3, column);
 458
 459                 /*
 460                  * although currently it's 8 bytes for READID, we always read
 461                  * the maximum 256 bytes(for PARAM)
 462                  */
 463                 ifc_out32(&ifc->ifc_nand.nand_fbcr, 256);
 464                 ctrl->read_bytes = 256;
 465
 466                 set_addr(mtd, 0, 0, 0);
 467                 fsl_ifc_run_command(mtd);
 468                 return;
 469         }
 470
 471         /* ERASE1 stores the block and page address */
 472         case NAND_CMD_ERASE1:
 473                 set_addr(mtd, 0, page_addr, 0);
 474                 return;
 475
 476         /* ERASE2 uses the block and page address from ERASE1 */
 477         case NAND_CMD_ERASE2:
 478                 ifc_out32(&ifc->ifc_nand.nand_fir0,
 479                           (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 480                           (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 481                           (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
 482
 483                 ifc_out32(&ifc->ifc_nand.nand_fcr0,
 484                           (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
 485                           (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
 486
 487                 ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
 488                 ctrl->read_bytes = 0;
 489                 fsl_ifc_run_command(mtd);
 490                 return;
 491
 492         /* SEQIN sets up the addr buffer and all registers except the length */
 493         case NAND_CMD_SEQIN: {
 494                 u32 nand_fcr0;
 495                 ctrl->column = column;
 496                 ctrl->oob = 0;
 497
 498                 if (mtd->writesize > 512) {
 499                         nand_fcr0 =
 500                                 (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
 501                                 (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
 502                                 (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
 503
 504                         ifc_out32(&ifc->ifc_nand.nand_fir0,
 505                                   (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 506                                   (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 507                                   (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
 508                                   (IFC_FIR_OP_WBCD  <<
 509                                                 IFC_NAND_FIR0_OP3_SHIFT) |
 510                                   (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT));
 511                         ifc_out32(&ifc->ifc_nand.nand_fir1,
 512                                   (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
 513                                   (IFC_FIR_OP_RDSTAT <<
 514                                         IFC_NAND_FIR1_OP6_SHIFT) |
 515                                   (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT));
 516                 } else {
 517                         nand_fcr0 = ((NAND_CMD_PAGEPROG <<
 518                                         IFC_NAND_FCR0_CMD1_SHIFT) |
 519                                     (NAND_CMD_SEQIN <<
 520                                         IFC_NAND_FCR0_CMD2_SHIFT) |
 521                                     (NAND_CMD_STATUS <<
 522                                         IFC_NAND_FCR0_CMD3_SHIFT));
 523
 524                         ifc_out32(&ifc->ifc_nand.nand_fir0,
 525                                   (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 526                                   (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
 527                                   (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
 528                                   (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
 529                                   (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
 530                         ifc_out32(&ifc->ifc_nand.nand_fir1,
 531                                   (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
 532                                   (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
 533                                   (IFC_FIR_OP_RDSTAT <<
 534                                         IFC_NAND_FIR1_OP7_SHIFT) |
 535                                   (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT));
 536
 537                         if (column >= mtd->writesize)
 538                                 nand_fcr0 |=
 539                                 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
 540                         else
 541                                 nand_fcr0 |=
 542                                 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
 543                 }
 544
 545                 if (column >= mtd->writesize) {
 546                         /* OOB area --> READOOB */
 547                         column -= mtd->writesize;
 548                         ctrl->oob = 1;
 549                 }
 550                 ifc_out32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
 551                 set_addr(mtd, column, page_addr, ctrl->oob);
 552                 return;
 553         }
 554
 555         /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
 556         case NAND_CMD_PAGEPROG:
 557                 if (ctrl->oob)
 558                         ifc_out32(&ifc->ifc_nand.nand_fbcr,
 559                                   ctrl->index - ctrl->column);
 560                 else
 561                         ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
 562
 563                 fsl_ifc_run_command(mtd);
 564                 return;
 565
 566         case NAND_CMD_STATUS:
 567                 ifc_out32(&ifc->ifc_nand.nand_fir0,
 568                           (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 569                           (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
 570                 ifc_out32(&ifc->ifc_nand.nand_fcr0,
 571                           NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
 572                 ifc_out32(&ifc->ifc_nand.nand_fbcr, 1);
 573                 set_addr(mtd, 0, 0, 0);
 574                 ctrl->read_bytes = 1;
 575
 576                 fsl_ifc_run_command(mtd);
 577
 578                 /*
 579                  * The chip always seems to report that it is
 580                  * write-protected, even when it is not.
 581                  */
 582                 if (chip->options & NAND_BUSWIDTH_16)
 583                         ifc_out16(ctrl->addr,
 584                                   ifc_in16(ctrl->addr) | NAND_STATUS_WP);
 585                 else
 586                         out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
 587                 return;
 588
 589         case NAND_CMD_RESET:
 590                 ifc_out32(&ifc->ifc_nand.nand_fir0,
 591                           IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
 592                 ifc_out32(&ifc->ifc_nand.nand_fcr0,
 593                           NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
 594                 fsl_ifc_run_command(mtd);
 595                 return;
 596
 597         default:
 598                 printf("%s: error, unsupported command 0x%x.\n",
 599                         __func__, command);
 600         }
 601 }
 602
 603 /*
 604  * Write buf to the IFC NAND Controller Data Buffer
 605  */
 606 static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 607 {
 608         struct nand_chip *chip = mtd_to_nand(mtd);
 609         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 610         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 611         unsigned int bufsize = mtd->writesize + mtd->oobsize;
 612
 613         if (len <= 0) {
 614                 printf("%s of %d bytes", __func__, len);
 615                 ctrl->status = 0;
 616                 return;
 617         }
 618
 619         if ((unsigned int)len > bufsize - ctrl->index) {
 620                 printf("%s beyond end of buffer "
 621                        "(%d requested, %u available)\n",
 622                         __func__, len, bufsize - ctrl->index);
 623                 len = bufsize - ctrl->index;
 624         }
 625
 626         memcpy_toio(ctrl->addr + ctrl->index, buf, len);
 627         ctrl->index += len;
 628 }
 629
 630 /*
 631  * read a byte from either the IFC hardware buffer if it has any data left
 632  * otherwise issue a command to read a single byte.
 633  */
 634 static u8 fsl_ifc_read_byte(struct mtd_info *mtd)
 635 {
 636         struct nand_chip *chip = mtd_to_nand(mtd);
 637         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 638         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 639         unsigned int offset;
 640
 641         /*
 642          * If there are still bytes in the IFC buffer, then use the
 643          * next byte.
 644          */
 645         if (ctrl->index < ctrl->read_bytes) {
 646                 offset = ctrl->index++;
 647                 return in_8(ctrl->addr + offset);
 648         }
 649
 650         printf("%s beyond end of buffer\n", __func__);
 651         return ERR_BYTE;
 652 }
 653
 654 /*
 655  * Read two bytes from the IFC hardware buffer
 656  * read function for 16-bit buswith
 657  */
 658 static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
 659 {
 660         struct nand_chip *chip = mtd_to_nand(mtd);
 661         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 662         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 663         uint16_t data;
 664
 665         /*
 666          * If there are still bytes in the IFC buffer, then use the
 667          * next byte.
 668          */
 669         if (ctrl->index < ctrl->read_bytes) {
 670                 data = ifc_in16(ctrl->addr + ctrl->index);
 671                 ctrl->index += 2;
 672                 return (uint8_t)data;
 673         }
 674
 675         printf("%s beyond end of buffer\n", __func__);
 676         return ERR_BYTE;
 677 }
 678
 679 /*
 680  * Read from the IFC Controller Data Buffer
 681  */
 682 static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 683 {
 684         struct nand_chip *chip = mtd_to_nand(mtd);
 685         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 686         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 687         int avail;
 688
 689         if (len < 0)
 690                 return;
 691
 692         avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
 693         memcpy_fromio(buf, ctrl->addr + ctrl->index, avail);
 694         ctrl->index += avail;
 695
 696         if (len > avail)
 697                 printf("%s beyond end of buffer "
 698                        "(%d requested, %d available)\n",
 699                        __func__, len, avail);
 700 }
 701
 702 /* This function is called after Program and Erase Operations to
 703  * check for success or failure.
 704  */
 705 static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 706 {
 707         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 708         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 709         struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
 710         u32 nand_fsr;
 711
 712         if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
 713                 return NAND_STATUS_FAIL;
 714
 715         /* Use READ_STATUS command, but wait for the device to be ready */
 716         ifc_out32(&ifc->ifc_nand.nand_fir0,
 717                   (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 718                   (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
 719         ifc_out32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
 720                   IFC_NAND_FCR0_CMD0_SHIFT);
 721         ifc_out32(&ifc->ifc_nand.nand_fbcr, 1);
 722         set_addr(mtd, 0, 0, 0);
 723         ctrl->read_bytes = 1;
 724
 725         fsl_ifc_run_command(mtd);
 726
 727         if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
 728                 return NAND_STATUS_FAIL;
 729
 730         nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
 731
 732         /* Chip sometimes reporting write protect even when it's not */
 733         nand_fsr = nand_fsr | NAND_STATUS_WP;
 734         return nand_fsr;
 735 }
 736
 737 static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 738                              uint8_t *buf, int oob_required, int page)
 739 {
 740         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 741         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 742
 743         fsl_ifc_read_buf(mtd, buf, mtd->writesize);
 744         fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
 745
 746         if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
 747                 mtd->ecc_stats.failed++;
 748
 749         return 0;
 750 }
 751
 752 /* ECC will be calculated automatically, and errors will be detected in
 753  * waitfunc.
 754  */
 755 static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 756                                const uint8_t *buf, int oob_required, int page)
 757 {
 758         fsl_ifc_write_buf(mtd, buf, mtd->writesize);
 759         fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 760
 761         return 0;
 762 }
 763
 764 static void fsl_ifc_ctrl_init(void)
 765 {
 766         uint32_t ver = 0;
 767         ifc_ctrl = kzalloc(sizeof(*ifc_ctrl), GFP_KERNEL);
 768         if (!ifc_ctrl)
 769                 return;
 770
 771         ifc_ctrl->regs.gregs = IFC_FCM_BASE_ADDR;
 772
 773         ver = ifc_in32(&ifc_ctrl->regs.gregs->ifc_rev);
 774         if (ver >= FSL_IFC_V2_0_0)
 775                 ifc_ctrl->regs.rregs =
 776                         (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET;
 777         else
 778                 ifc_ctrl->regs.rregs =
 779                         (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET;
 780
 781         /* clear event registers */
 782         ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.nand_evter_stat, ~0U);
 783         ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.pgrdcmpl_evt_stat, ~0U);
 784
 785         /* Enable error and event for any detected errors */
 786         ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.nand_evter_en,
 787                   IFC_NAND_EVTER_EN_OPC_EN |
 788                   IFC_NAND_EVTER_EN_PGRDCMPL_EN |
 789                   IFC_NAND_EVTER_EN_FTOER_EN |
 790                   IFC_NAND_EVTER_EN_WPER_EN);
 791
 792         ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.ncfgr, 0x0);
 793 }
 794
 795 static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
 796 {
 797 }
 798
 799 static int fsl_ifc_sram_init(struct fsl_ifc_mtd *priv, uint32_t ver)
 800 {
 801         struct fsl_ifc_runtime *ifc = ifc_ctrl->regs.rregs;
 802         uint32_t cs = 0, csor = 0, csor_8k = 0, csor_ext = 0;
 803         uint32_t ncfgr = 0;
 804         u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
 805         u32 time_start;
 806
 807         if (ver > FSL_IFC_V1_1_0) {
 808                 ncfgr = ifc_in32(&ifc->ifc_nand.ncfgr);
 809                 ifc_out32(&ifc->ifc_nand.ncfgr, ncfgr | IFC_NAND_SRAM_INIT_EN);
 810
 811                 /* wait for  SRAM_INIT bit to be clear or timeout */
 812                 time_start = get_timer(0);
 813                 while (get_timer(time_start) < timeo) {
 814                         ifc_ctrl->status =
 815                                 ifc_in32(&ifc->ifc_nand.nand_evter_stat);
 816
 817                         if (!(ifc_ctrl->status & IFC_NAND_SRAM_INIT_EN))
 818                                 return 0;
 819                 }
 820                 printf("fsl-ifc: Failed to Initialise SRAM\n");
 821                 return 1;
 822         }
 823
 824         cs = priv->bank;
 825
 826         /* Save CSOR and CSOR_ext */
 827         csor = ifc_in32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor);
 828         csor_ext = ifc_in32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor_ext);
 829
 830         /* chage PageSize 8K and SpareSize 1K*/
 831         csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
 832         ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor, csor_8k);
 833         ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor_ext, 0x0000400);
 834
 835         /* READID */
 836         ifc_out32(&ifc->ifc_nand.nand_fir0,
 837                   (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 838                   (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
 839                   (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
 840         ifc_out32(&ifc->ifc_nand.nand_fcr0,
 841                   NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT);
 842         ifc_out32(&ifc->ifc_nand.row3, 0x0);
 843
 844         ifc_out32(&ifc->ifc_nand.nand_fbcr, 0x0);
 845
 846         /* Program ROW0/COL0 */
 847         ifc_out32(&ifc->ifc_nand.row0, 0x0);
 848         ifc_out32(&ifc->ifc_nand.col0, 0x0);
 849
 850         /* set the chip select for NAND Transaction */
 851         ifc_out32(&ifc->ifc_nand.nand_csel, priv->bank << IFC_NAND_CSEL_SHIFT);
 852
 853         /* start read seq */
 854         ifc_out32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
 855
 856         time_start = get_timer(0);
 857
 858         while (get_timer(time_start) < timeo) {
 859                 ifc_ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
 860
 861                 if (ifc_ctrl->status & IFC_NAND_EVTER_STAT_OPC)
 862                         break;
 863         }
 864
 865         if (ifc_ctrl->status != IFC_NAND_EVTER_STAT_OPC) {
 866                 printf("fsl-ifc: Failed to Initialise SRAM\n");
 867                 return 1;
 868         }
 869
 870         ifc_out32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status);
 871
 872         /* Restore CSOR and CSOR_ext */
 873         ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor, csor);
 874         ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor_ext, csor_ext);
 875
 876         return 0;
 877 }
 878
 879 static int fsl_ifc_chip_init(int devnum, u8 *addr)
 880 {
 881         struct mtd_info *mtd;
 882         struct nand_chip *nand;
 883         struct fsl_ifc_mtd *priv;
 884         struct nand_ecclayout *layout;
 885         struct fsl_ifc_fcm *gregs = NULL;
 886         uint32_t cspr = 0, csor = 0, ver = 0;
 887         int ret = 0;
 888
 889         if (!ifc_ctrl) {
 890                 fsl_ifc_ctrl_init();
 891                 if (!ifc_ctrl)
 892                         return -1;
 893         }
 894
 895         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 896         if (!priv)
 897                 return -ENOMEM;
 898
 899         priv->ctrl = ifc_ctrl;
 900         priv->vbase = addr;
 901         gregs = ifc_ctrl->regs.gregs;
 902
 903         /* Find which chip select it is connected to.
 904          */
 905         for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
 906                 phys_addr_t phys_addr = virt_to_phys(addr);
 907
 908                 cspr = ifc_in32(&gregs->cspr_cs[priv->bank].cspr);
 909                 csor = ifc_in32(&gregs->csor_cs[priv->bank].csor);
 910
 911                 if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND &&
 912                     (cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr))
 913                         break;
 914         }
 915
 916         if (priv->bank >= MAX_BANKS) {
 917                 printf("%s: address did not match any "
 918                        "chip selects\n", __func__);
 919                 kfree(priv);
 920                 return -ENODEV;
 921         }
 922
 923         nand = &priv->chip;
 924         mtd = nand_to_mtd(nand);
 925
 926         ifc_ctrl->chips[priv->bank] = priv;
 927
 928         /* fill in nand_chip structure */
 929         /* set up function call table */
 930
 931         nand->write_buf = fsl_ifc_write_buf;
 932         nand->read_buf = fsl_ifc_read_buf;
 933         nand->select_chip = fsl_ifc_select_chip;
 934         nand->cmdfunc = fsl_ifc_cmdfunc;
 935         nand->waitfunc = fsl_ifc_wait;
 936
 937         /* set up nand options */
 938         nand->bbt_td = &bbt_main_descr;
 939         nand->bbt_md = &bbt_mirror_descr;
 940
 941         /* set up nand options */
 942         nand->options = NAND_NO_SUBPAGE_WRITE;
 943         nand->bbt_options = NAND_BBT_USE_FLASH;
 944
 945         if (cspr & CSPR_PORT_SIZE_16) {
 946                 nand->read_byte = fsl_ifc_read_byte16;
 947                 nand->options |= NAND_BUSWIDTH_16;
 948         } else {
 949                 nand->read_byte = fsl_ifc_read_byte;
 950         }
 951
 952         nand->controller = &ifc_ctrl->controller;
 953         nand_set_controller_data(nand, priv);
 954
 955         nand->ecc.read_page = fsl_ifc_read_page;
 956         nand->ecc.write_page = fsl_ifc_write_page;
 957
 958         /* Hardware generates ECC per 512 Bytes */
 959         nand->ecc.size = 512;
 960         nand->ecc.bytes = 8;
 961
 962         switch (csor & CSOR_NAND_PGS_MASK) {
 963         case CSOR_NAND_PGS_512:
 964                 if (nand->options & NAND_BUSWIDTH_16) {
 965                         layout = &oob_512_16bit_ecc4;
 966                 } else {
 967                         layout = &oob_512_8bit_ecc4;
 968
 969                         /* Avoid conflict with bad block marker */
 970                         bbt_main_descr.offs = 0;
 971                         bbt_mirror_descr.offs = 0;
 972                 }
 973
 974                 nand->ecc.strength = 4;
 975                 priv->bufnum_mask = 15;
 976                 break;
 977
 978         case CSOR_NAND_PGS_2K:
 979                 layout = &oob_2048_ecc4;
 980                 nand->ecc.strength = 4;
 981                 priv->bufnum_mask = 3;
 982                 break;
 983
 984         case CSOR_NAND_PGS_4K:
 985                 if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
 986                     CSOR_NAND_ECC_MODE_4) {
 987                         layout = &oob_4096_ecc4;
 988                         nand->ecc.strength = 4;
 989                 } else {
 990                         layout = &oob_4096_ecc8;
 991                         nand->ecc.strength = 8;
 992                         nand->ecc.bytes = 16;
 993                 }
 994
 995                 priv->bufnum_mask = 1;
 996                 break;
 997
 998         case CSOR_NAND_PGS_8K:
 999                 if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
1000                     CSOR_NAND_ECC_MODE_4) {
1001                         layout = &oob_8192_ecc4;
1002                         nand->ecc.strength = 4;
1003                 } else {
1004                         layout = &oob_8192_ecc8;
1005                         nand->ecc.strength = 8;
1006                         nand->ecc.bytes = 16;
1007                 }
1008
1009                 priv->bufnum_mask = 0;
1010                 break;
1011
1012
1013         default:
1014                 printf("ifc nand: bad csor %#x: bad page size\n", csor);
1015                 return -ENODEV;
1016         }
1017
1018         /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
1019         if (csor & CSOR_NAND_ECC_DEC_EN) {
1020                 nand->ecc.mode = NAND_ECC_HW;
1021                 nand->ecc.layout = layout;
1022         } else {
1023                 nand->ecc.mode = NAND_ECC_SOFT;
1024         }
1025
1026         ver = ifc_in32(&gregs->ifc_rev);
1027         if (ver >= FSL_IFC_V1_1_0)
1028                 ret = fsl_ifc_sram_init(priv, ver);
1029         if (ret)
1030                 return ret;
1031
1032         if (ver >= FSL_IFC_V2_0_0)
1033                 priv->bufnum_mask = (priv->bufnum_mask * 2) + 1;
1034
1035         ret = nand_scan_ident(mtd, 1, NULL);
1036         if (ret)
1037                 return ret;
1038
1039         ret = nand_scan_tail(mtd);
1040         if (ret)
1041                 return ret;
1042
1043         ret = nand_register(devnum, mtd);
1044         if (ret)
1045                 return ret;
1046         return 0;
1047 }
1048
1049 #ifndef CONFIG_SYS_NAND_BASE_LIST
1050 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
1051 #endif
1052
1053 static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] =
1054         CONFIG_SYS_NAND_BASE_LIST;
1055
1056 void board_nand_init(void)
1057 {
1058         int i;
1059
1060         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
1061                 fsl_ifc_chip_init(i, (u8 *)base_address[i]);
1062 }