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nand: Embed mtd_info in struct nand_chip
[u-boot] / drivers / mtd / nand / fsl_ifc_nand.c
1 /* Integrated Flash Controller NAND Machine Driver
2  *
3  * Copyright (c) 2012 Freescale Semiconductor, Inc
4  *
5  * Authors: Dipen Dudhat <Dipen.Dudhat@freescale.com>
6  *
7  * SPDX-License-Identifier:     GPL-2.0+
8  */
9
10 #include <common.h>
11 #include <malloc.h>
12 #include <nand.h>
13
14 #include <linux/mtd/mtd.h>
15 #include <linux/mtd/nand.h>
16 #include <linux/mtd/nand_ecc.h>
17
18 #include <asm/io.h>
19 #include <asm/errno.h>
20 #include <fsl_ifc.h>
21
22 #ifndef CONFIG_SYS_FSL_IFC_BANK_COUNT
23 #define CONFIG_SYS_FSL_IFC_BANK_COUNT   4
24 #endif
25
26 #define MAX_BANKS       CONFIG_SYS_FSL_IFC_BANK_COUNT
27 #define ERR_BYTE        0xFF /* Value returned for read bytes
28                                 when read failed */
29
30 struct fsl_ifc_ctrl;
31
32 /* mtd information per set */
33 struct fsl_ifc_mtd {
34         struct nand_chip chip;
35         struct fsl_ifc_ctrl *ctrl;
36
37         struct device *dev;
38         int bank;               /* Chip select bank number                */
39         unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
40         u8 __iomem *vbase;      /* Chip select base virtual address       */
41 };
42
43 /* overview of the fsl ifc controller */
44 struct fsl_ifc_ctrl {
45         struct nand_hw_control controller;
46         struct fsl_ifc_mtd *chips[MAX_BANKS];
47
48         /* device info */
49         struct fsl_ifc regs;
50         void __iomem *addr;      /* Address of assigned IFC buffer        */
51         unsigned int cs_nand;    /* On which chipsel NAND is connected    */
52         unsigned int page;       /* Last page written to / read from      */
53         unsigned int read_bytes; /* Number of bytes read during command   */
54         unsigned int column;     /* Saved column from SEQIN               */
55         unsigned int index;      /* Pointer to next byte to 'read'        */
56         unsigned int status;     /* status read from NEESR after last op  */
57         unsigned int oob;        /* Non zero if operating on OOB data     */
58         unsigned int eccread;    /* Non zero for a full-page ECC read     */
59 };
60
61 static struct fsl_ifc_ctrl *ifc_ctrl;
62
63 /* 512-byte page with 4-bit ECC, 8-bit */
64 static struct nand_ecclayout oob_512_8bit_ecc4 = {
65         .eccbytes = 8,
66         .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
67         .oobfree = { {0, 5}, {6, 2} },
68 };
69
70 /* 512-byte page with 4-bit ECC, 16-bit */
71 static struct nand_ecclayout oob_512_16bit_ecc4 = {
72         .eccbytes = 8,
73         .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
74         .oobfree = { {2, 6}, },
75 };
76
77 /* 2048-byte page size with 4-bit ECC */
78 static struct nand_ecclayout oob_2048_ecc4 = {
79         .eccbytes = 32,
80         .eccpos = {
81                 8, 9, 10, 11, 12, 13, 14, 15,
82                 16, 17, 18, 19, 20, 21, 22, 23,
83                 24, 25, 26, 27, 28, 29, 30, 31,
84                 32, 33, 34, 35, 36, 37, 38, 39,
85         },
86         .oobfree = { {2, 6}, {40, 24} },
87 };
88
89 /* 4096-byte page size with 4-bit ECC */
90 static struct nand_ecclayout oob_4096_ecc4 = {
91         .eccbytes = 64,
92         .eccpos = {
93                 8, 9, 10, 11, 12, 13, 14, 15,
94                 16, 17, 18, 19, 20, 21, 22, 23,
95                 24, 25, 26, 27, 28, 29, 30, 31,
96                 32, 33, 34, 35, 36, 37, 38, 39,
97                 40, 41, 42, 43, 44, 45, 46, 47,
98                 48, 49, 50, 51, 52, 53, 54, 55,
99                 56, 57, 58, 59, 60, 61, 62, 63,
100                 64, 65, 66, 67, 68, 69, 70, 71,
101         },
102         .oobfree = { {2, 6}, {72, 56} },
103 };
104
105 /* 4096-byte page size with 8-bit ECC -- requires 218-byte OOB */
106 static struct nand_ecclayout oob_4096_ecc8 = {
107         .eccbytes = 128,
108         .eccpos = {
109                 8, 9, 10, 11, 12, 13, 14, 15,
110                 16, 17, 18, 19, 20, 21, 22, 23,
111                 24, 25, 26, 27, 28, 29, 30, 31,
112                 32, 33, 34, 35, 36, 37, 38, 39,
113                 40, 41, 42, 43, 44, 45, 46, 47,
114                 48, 49, 50, 51, 52, 53, 54, 55,
115                 56, 57, 58, 59, 60, 61, 62, 63,
116                 64, 65, 66, 67, 68, 69, 70, 71,
117                 72, 73, 74, 75, 76, 77, 78, 79,
118                 80, 81, 82, 83, 84, 85, 86, 87,
119                 88, 89, 90, 91, 92, 93, 94, 95,
120                 96, 97, 98, 99, 100, 101, 102, 103,
121                 104, 105, 106, 107, 108, 109, 110, 111,
122                 112, 113, 114, 115, 116, 117, 118, 119,
123                 120, 121, 122, 123, 124, 125, 126, 127,
124                 128, 129, 130, 131, 132, 133, 134, 135,
125         },
126         .oobfree = { {2, 6}, {136, 82} },
127 };
128
129 /* 8192-byte page size with 4-bit ECC */
130 static struct nand_ecclayout oob_8192_ecc4 = {
131         .eccbytes = 128,
132         .eccpos = {
133                 8, 9, 10, 11, 12, 13, 14, 15,
134                 16, 17, 18, 19, 20, 21, 22, 23,
135                 24, 25, 26, 27, 28, 29, 30, 31,
136                 32, 33, 34, 35, 36, 37, 38, 39,
137                 40, 41, 42, 43, 44, 45, 46, 47,
138                 48, 49, 50, 51, 52, 53, 54, 55,
139                 56, 57, 58, 59, 60, 61, 62, 63,
140                 64, 65, 66, 67, 68, 69, 70, 71,
141                 72, 73, 74, 75, 76, 77, 78, 79,
142                 80, 81, 82, 83, 84, 85, 86, 87,
143                 88, 89, 90, 91, 92, 93, 94, 95,
144                 96, 97, 98, 99, 100, 101, 102, 103,
145                 104, 105, 106, 107, 108, 109, 110, 111,
146                 112, 113, 114, 115, 116, 117, 118, 119,
147                 120, 121, 122, 123, 124, 125, 126, 127,
148                 128, 129, 130, 131, 132, 133, 134, 135,
149         },
150         .oobfree = { {2, 6}, {136, 208} },
151 };
152
153 /* 8192-byte page size with 8-bit ECC -- requires 218-byte OOB */
154 static struct nand_ecclayout oob_8192_ecc8 = {
155         .eccbytes = 256,
156         .eccpos = {
157                 8, 9, 10, 11, 12, 13, 14, 15,
158                 16, 17, 18, 19, 20, 21, 22, 23,
159                 24, 25, 26, 27, 28, 29, 30, 31,
160                 32, 33, 34, 35, 36, 37, 38, 39,
161                 40, 41, 42, 43, 44, 45, 46, 47,
162                 48, 49, 50, 51, 52, 53, 54, 55,
163                 56, 57, 58, 59, 60, 61, 62, 63,
164                 64, 65, 66, 67, 68, 69, 70, 71,
165                 72, 73, 74, 75, 76, 77, 78, 79,
166                 80, 81, 82, 83, 84, 85, 86, 87,
167                 88, 89, 90, 91, 92, 93, 94, 95,
168                 96, 97, 98, 99, 100, 101, 102, 103,
169                 104, 105, 106, 107, 108, 109, 110, 111,
170                 112, 113, 114, 115, 116, 117, 118, 119,
171                 120, 121, 122, 123, 124, 125, 126, 127,
172                 128, 129, 130, 131, 132, 133, 134, 135,
173                 136, 137, 138, 139, 140, 141, 142, 143,
174                 144, 145, 146, 147, 148, 149, 150, 151,
175                 152, 153, 154, 155, 156, 157, 158, 159,
176                 160, 161, 162, 163, 164, 165, 166, 167,
177                 168, 169, 170, 171, 172, 173, 174, 175,
178                 176, 177, 178, 179, 180, 181, 182, 183,
179                 184, 185, 186, 187, 188, 189, 190, 191,
180                 192, 193, 194, 195, 196, 197, 198, 199,
181                 200, 201, 202, 203, 204, 205, 206, 207,
182                 208, 209, 210, 211, 212, 213, 214, 215,
183                 216, 217, 218, 219, 220, 221, 222, 223,
184                 224, 225, 226, 227, 228, 229, 230, 231,
185                 232, 233, 234, 235, 236, 237, 238, 239,
186                 240, 241, 242, 243, 244, 245, 246, 247,
187                 248, 249, 250, 251, 252, 253, 254, 255,
188                 256, 257, 258, 259, 260, 261, 262, 263,
189         },
190         .oobfree = { {2, 6}, {264, 80} },
191 };
192
193 /*
194  * Generic flash bbt descriptors
195  */
196 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
197 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
198
199 static struct nand_bbt_descr bbt_main_descr = {
200         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
201                    NAND_BBT_2BIT | NAND_BBT_VERSION,
202         .offs = 2, /* 0 on 8-bit small page */
203         .len = 4,
204         .veroffs = 6,
205         .maxblocks = 4,
206         .pattern = bbt_pattern,
207 };
208
209 static struct nand_bbt_descr bbt_mirror_descr = {
210         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
211                    NAND_BBT_2BIT | NAND_BBT_VERSION,
212         .offs = 2, /* 0 on 8-bit small page */
213         .len = 4,
214         .veroffs = 6,
215         .maxblocks = 4,
216         .pattern = mirror_pattern,
217 };
218
219 /*
220  * Set up the IFC hardware block and page address fields, and the ifc nand
221  * structure addr field to point to the correct IFC buffer in memory
222  */
223 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
224 {
225         struct nand_chip *chip = mtd->priv;
226         struct fsl_ifc_mtd *priv = chip->priv;
227         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
228         struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
229         int buf_num;
230
231         ctrl->page = page_addr;
232
233         /* Program ROW0/COL0 */
234         ifc_out32(&ifc->ifc_nand.row0, page_addr);
235         ifc_out32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
236
237         buf_num = page_addr & priv->bufnum_mask;
238
239         ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
240         ctrl->index = column;
241
242         /* for OOB data point to the second half of the buffer */
243         if (oob)
244                 ctrl->index += mtd->writesize;
245 }
246
247 static int is_blank(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
248                     unsigned int bufnum)
249 {
250         struct nand_chip *chip = mtd->priv;
251         struct fsl_ifc_mtd *priv = chip->priv;
252         u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2);
253         u32 __iomem *main = (u32 *)addr;
254         u8 __iomem *oob = addr + mtd->writesize;
255         int i;
256
257         for (i = 0; i < mtd->writesize / 4; i++) {
258                 if (__raw_readl(&main[i]) != 0xffffffff)
259                         return 0;
260         }
261
262         for (i = 0; i < chip->ecc.layout->eccbytes; i++) {
263                 int pos = chip->ecc.layout->eccpos[i];
264
265                 if (__raw_readb(&oob[pos]) != 0xff)
266                         return 0;
267         }
268
269         return 1;
270 }
271
272 /* returns nonzero if entire page is blank */
273 static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
274                           u32 *eccstat, unsigned int bufnum)
275 {
276         u32 reg = eccstat[bufnum / 4];
277         int errors;
278
279         errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
280
281         return errors;
282 }
283
284 /*
285  * execute IFC NAND command and wait for it to complete
286  */
287 static int fsl_ifc_run_command(struct mtd_info *mtd)
288 {
289         struct nand_chip *chip = mtd->priv;
290         struct fsl_ifc_mtd *priv = chip->priv;
291         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
292         struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
293         u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
294         u32 time_start;
295         u32 eccstat[8] = {0};
296         int i;
297
298         /* set the chip select for NAND Transaction */
299         ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
300
301         /* start read/write seq */
302         ifc_out32(&ifc->ifc_nand.nandseq_strt,
303                   IFC_NAND_SEQ_STRT_FIR_STRT);
304
305         /* wait for NAND Machine complete flag or timeout */
306         time_start = get_timer(0);
307
308         while (get_timer(time_start) < timeo) {
309                 ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
310
311                 if (ctrl->status & IFC_NAND_EVTER_STAT_OPC)
312                         break;
313         }
314
315         ifc_out32(&ifc->ifc_nand.nand_evter_stat, ctrl->status);
316
317         if (ctrl->status & IFC_NAND_EVTER_STAT_FTOER)
318                 printf("%s: Flash Time Out Error\n", __func__);
319         if (ctrl->status & IFC_NAND_EVTER_STAT_WPER)
320                 printf("%s: Write Protect Error\n", __func__);
321
322         if (ctrl->eccread) {
323                 int errors;
324                 int bufnum = ctrl->page & priv->bufnum_mask;
325                 int sector = bufnum * chip->ecc.steps;
326                 int sector_end = sector + chip->ecc.steps - 1;
327
328                 for (i = sector / 4; i <= sector_end / 4; i++) {
329                         if (i >= ARRAY_SIZE(eccstat)) {
330                                 printf("%s: eccstat too small for %d\n",
331                                        __func__, i);
332                                 return -EIO;
333                         }
334
335                         eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]);
336                 }
337
338                 for (i = sector; i <= sector_end; i++) {
339                         errors = check_read_ecc(mtd, ctrl, eccstat, i);
340
341                         if (errors == 15) {
342                                 /*
343                                  * Uncorrectable error.
344                                  * OK only if the whole page is blank.
345                                  *
346                                  * We disable ECCER reporting due to erratum
347                                  * IFC-A002770 -- so report it now if we
348                                  * see an uncorrectable error in ECCSTAT.
349                                  */
350                                 if (!is_blank(mtd, ctrl, bufnum))
351                                         ctrl->status |=
352                                                 IFC_NAND_EVTER_STAT_ECCER;
353                                 break;
354                         }
355
356                         mtd->ecc_stats.corrected += errors;
357                 }
358
359                 ctrl->eccread = 0;
360         }
361
362         /* returns 0 on success otherwise non-zero) */
363         return ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO;
364 }
365
366 static void fsl_ifc_do_read(struct nand_chip *chip,
367                             int oob,
368                             struct mtd_info *mtd)
369 {
370         struct fsl_ifc_mtd *priv = chip->priv;
371         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
372         struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
373
374         /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
375         if (mtd->writesize > 512) {
376                 ifc_out32(&ifc->ifc_nand.nand_fir0,
377                           (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
378                           (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
379                           (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
380                           (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
381                           (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
382                 ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
383
384                 ifc_out32(&ifc->ifc_nand.nand_fcr0,
385                           (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
386                           (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
387         } else {
388                 ifc_out32(&ifc->ifc_nand.nand_fir0,
389                           (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
390                           (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
391                           (IFC_FIR_OP_RA0  << IFC_NAND_FIR0_OP2_SHIFT) |
392                           (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
393
394                 if (oob)
395                         ifc_out32(&ifc->ifc_nand.nand_fcr0,
396                                   NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
397                 else
398                         ifc_out32(&ifc->ifc_nand.nand_fcr0,
399                                   NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
400         }
401 }
402
403 /* cmdfunc send commands to the IFC NAND Machine */
404 static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
405                              int column, int page_addr)
406 {
407         struct nand_chip *chip = mtd->priv;
408         struct fsl_ifc_mtd *priv = chip->priv;
409         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
410         struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
411
412         /* clear the read buffer */
413         ctrl->read_bytes = 0;
414         if (command != NAND_CMD_PAGEPROG)
415                 ctrl->index = 0;
416
417         switch (command) {
418         /* READ0 read the entire buffer to use hardware ECC. */
419         case NAND_CMD_READ0: {
420                 ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
421                 set_addr(mtd, 0, page_addr, 0);
422
423                 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
424                 ctrl->index += column;
425
426                 if (chip->ecc.mode == NAND_ECC_HW)
427                         ctrl->eccread = 1;
428
429                 fsl_ifc_do_read(chip, 0, mtd);
430                 fsl_ifc_run_command(mtd);
431                 return;
432         }
433
434         /* READOOB reads only the OOB because no ECC is performed. */
435         case NAND_CMD_READOOB:
436                 ifc_out32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
437                 set_addr(mtd, column, page_addr, 1);
438
439                 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
440
441                 fsl_ifc_do_read(chip, 1, mtd);
442                 fsl_ifc_run_command(mtd);
443
444                 return;
445
446         /* READID must read all possible bytes while CEB is active */
447         case NAND_CMD_READID:
448         case NAND_CMD_PARAM: {
449                 int timing = IFC_FIR_OP_RB;
450                 if (command == NAND_CMD_PARAM)
451                         timing = IFC_FIR_OP_RBCD;
452
453                 ifc_out32(&ifc->ifc_nand.nand_fir0,
454                           (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
455                           (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
456                           (timing << IFC_NAND_FIR0_OP2_SHIFT));
457                 ifc_out32(&ifc->ifc_nand.nand_fcr0,
458                           command << IFC_NAND_FCR0_CMD0_SHIFT);
459                 ifc_out32(&ifc->ifc_nand.row3, column);
460
461                 /*
462                  * although currently it's 8 bytes for READID, we always read
463                  * the maximum 256 bytes(for PARAM)
464                  */
465                 ifc_out32(&ifc->ifc_nand.nand_fbcr, 256);
466                 ctrl->read_bytes = 256;
467
468                 set_addr(mtd, 0, 0, 0);
469                 fsl_ifc_run_command(mtd);
470                 return;
471         }
472
473         /* ERASE1 stores the block and page address */
474         case NAND_CMD_ERASE1:
475                 set_addr(mtd, 0, page_addr, 0);
476                 return;
477
478         /* ERASE2 uses the block and page address from ERASE1 */
479         case NAND_CMD_ERASE2:
480                 ifc_out32(&ifc->ifc_nand.nand_fir0,
481                           (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
482                           (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
483                           (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
484
485                 ifc_out32(&ifc->ifc_nand.nand_fcr0,
486                           (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
487                           (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
488
489                 ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
490                 ctrl->read_bytes = 0;
491                 fsl_ifc_run_command(mtd);
492                 return;
493
494         /* SEQIN sets up the addr buffer and all registers except the length */
495         case NAND_CMD_SEQIN: {
496                 u32 nand_fcr0;
497                 ctrl->column = column;
498                 ctrl->oob = 0;
499
500                 if (mtd->writesize > 512) {
501                         nand_fcr0 =
502                                 (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
503                                 (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
504                                 (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
505
506                         ifc_out32(&ifc->ifc_nand.nand_fir0,
507                                   (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
508                                   (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
509                                   (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
510                                   (IFC_FIR_OP_WBCD  <<
511                                                 IFC_NAND_FIR0_OP3_SHIFT) |
512                                   (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT));
513                         ifc_out32(&ifc->ifc_nand.nand_fir1,
514                                   (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
515                                   (IFC_FIR_OP_RDSTAT <<
516                                         IFC_NAND_FIR1_OP6_SHIFT) |
517                                   (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT));
518                 } else {
519                         nand_fcr0 = ((NAND_CMD_PAGEPROG <<
520                                         IFC_NAND_FCR0_CMD1_SHIFT) |
521                                     (NAND_CMD_SEQIN <<
522                                         IFC_NAND_FCR0_CMD2_SHIFT) |
523                                     (NAND_CMD_STATUS <<
524                                         IFC_NAND_FCR0_CMD3_SHIFT));
525
526                         ifc_out32(&ifc->ifc_nand.nand_fir0,
527                                   (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
528                                   (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
529                                   (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
530                                   (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
531                                   (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
532                         ifc_out32(&ifc->ifc_nand.nand_fir1,
533                                   (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
534                                   (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
535                                   (IFC_FIR_OP_RDSTAT <<
536                                         IFC_NAND_FIR1_OP7_SHIFT) |
537                                   (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT));
538
539                         if (column >= mtd->writesize)
540                                 nand_fcr0 |=
541                                 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
542                         else
543                                 nand_fcr0 |=
544                                 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
545                 }
546
547                 if (column >= mtd->writesize) {
548                         /* OOB area --> READOOB */
549                         column -= mtd->writesize;
550                         ctrl->oob = 1;
551                 }
552                 ifc_out32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
553                 set_addr(mtd, column, page_addr, ctrl->oob);
554                 return;
555         }
556
557         /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
558         case NAND_CMD_PAGEPROG:
559                 if (ctrl->oob)
560                         ifc_out32(&ifc->ifc_nand.nand_fbcr,
561                                   ctrl->index - ctrl->column);
562                 else
563                         ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
564
565                 fsl_ifc_run_command(mtd);
566                 return;
567
568         case NAND_CMD_STATUS:
569                 ifc_out32(&ifc->ifc_nand.nand_fir0,
570                           (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
571                           (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
572                 ifc_out32(&ifc->ifc_nand.nand_fcr0,
573                           NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
574                 ifc_out32(&ifc->ifc_nand.nand_fbcr, 1);
575                 set_addr(mtd, 0, 0, 0);
576                 ctrl->read_bytes = 1;
577
578                 fsl_ifc_run_command(mtd);
579
580                 /*
581                  * The chip always seems to report that it is
582                  * write-protected, even when it is not.
583                  */
584                 if (chip->options & NAND_BUSWIDTH_16)
585                         ifc_out16(ctrl->addr,
586                                   ifc_in16(ctrl->addr) | NAND_STATUS_WP);
587                 else
588                         out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
589                 return;
590
591         case NAND_CMD_RESET:
592                 ifc_out32(&ifc->ifc_nand.nand_fir0,
593                           IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
594                 ifc_out32(&ifc->ifc_nand.nand_fcr0,
595                           NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
596                 fsl_ifc_run_command(mtd);
597                 return;
598
599         default:
600                 printf("%s: error, unsupported command 0x%x.\n",
601                         __func__, command);
602         }
603 }
604
605 /*
606  * Write buf to the IFC NAND Controller Data Buffer
607  */
608 static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
609 {
610         struct nand_chip *chip = mtd->priv;
611         struct fsl_ifc_mtd *priv = chip->priv;
612         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
613         unsigned int bufsize = mtd->writesize + mtd->oobsize;
614
615         if (len <= 0) {
616                 printf("%s of %d bytes", __func__, len);
617                 ctrl->status = 0;
618                 return;
619         }
620
621         if ((unsigned int)len > bufsize - ctrl->index) {
622                 printf("%s beyond end of buffer "
623                        "(%d requested, %u available)\n",
624                         __func__, len, bufsize - ctrl->index);
625                 len = bufsize - ctrl->index;
626         }
627
628         memcpy_toio(ctrl->addr + ctrl->index, buf, len);
629         ctrl->index += len;
630 }
631
632 /*
633  * read a byte from either the IFC hardware buffer if it has any data left
634  * otherwise issue a command to read a single byte.
635  */
636 static u8 fsl_ifc_read_byte(struct mtd_info *mtd)
637 {
638         struct nand_chip *chip = mtd->priv;
639         struct fsl_ifc_mtd *priv = chip->priv;
640         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
641         unsigned int offset;
642
643         /*
644          * If there are still bytes in the IFC buffer, then use the
645          * next byte.
646          */
647         if (ctrl->index < ctrl->read_bytes) {
648                 offset = ctrl->index++;
649                 return in_8(ctrl->addr + offset);
650         }
651
652         printf("%s beyond end of buffer\n", __func__);
653         return ERR_BYTE;
654 }
655
656 /*
657  * Read two bytes from the IFC hardware buffer
658  * read function for 16-bit buswith
659  */
660 static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
661 {
662         struct nand_chip *chip = mtd->priv;
663         struct fsl_ifc_mtd *priv = chip->priv;
664         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
665         uint16_t data;
666
667         /*
668          * If there are still bytes in the IFC buffer, then use the
669          * next byte.
670          */
671         if (ctrl->index < ctrl->read_bytes) {
672                 data = ifc_in16(ctrl->addr + ctrl->index);
673                 ctrl->index += 2;
674                 return (uint8_t)data;
675         }
676
677         printf("%s beyond end of buffer\n", __func__);
678         return ERR_BYTE;
679 }
680
681 /*
682  * Read from the IFC Controller Data Buffer
683  */
684 static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
685 {
686         struct nand_chip *chip = mtd->priv;
687         struct fsl_ifc_mtd *priv = chip->priv;
688         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
689         int avail;
690
691         if (len < 0)
692                 return;
693
694         avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
695         memcpy_fromio(buf, ctrl->addr + ctrl->index, avail);
696         ctrl->index += avail;
697
698         if (len > avail)
699                 printf("%s beyond end of buffer "
700                        "(%d requested, %d available)\n",
701                        __func__, len, avail);
702 }
703
704 /* This function is called after Program and Erase Operations to
705  * check for success or failure.
706  */
707 static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
708 {
709         struct fsl_ifc_mtd *priv = chip->priv;
710         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
711         struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
712         u32 nand_fsr;
713
714         if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
715                 return NAND_STATUS_FAIL;
716
717         /* Use READ_STATUS command, but wait for the device to be ready */
718         ifc_out32(&ifc->ifc_nand.nand_fir0,
719                   (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
720                   (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
721         ifc_out32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
722                   IFC_NAND_FCR0_CMD0_SHIFT);
723         ifc_out32(&ifc->ifc_nand.nand_fbcr, 1);
724         set_addr(mtd, 0, 0, 0);
725         ctrl->read_bytes = 1;
726
727         fsl_ifc_run_command(mtd);
728
729         if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
730                 return NAND_STATUS_FAIL;
731
732         nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
733
734         /* Chip sometimes reporting write protect even when it's not */
735         nand_fsr = nand_fsr | NAND_STATUS_WP;
736         return nand_fsr;
737 }
738
739 static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
740                              uint8_t *buf, int oob_required, int page)
741 {
742         struct fsl_ifc_mtd *priv = chip->priv;
743         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
744
745         fsl_ifc_read_buf(mtd, buf, mtd->writesize);
746         fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
747
748         if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
749                 mtd->ecc_stats.failed++;
750
751         return 0;
752 }
753
754 /* ECC will be calculated automatically, and errors will be detected in
755  * waitfunc.
756  */
757 static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
758                                const uint8_t *buf, int oob_required)
759 {
760         fsl_ifc_write_buf(mtd, buf, mtd->writesize);
761         fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
762
763         return 0;
764 }
765
766 static void fsl_ifc_ctrl_init(void)
767 {
768         uint32_t ver = 0;
769         ifc_ctrl = kzalloc(sizeof(*ifc_ctrl), GFP_KERNEL);
770         if (!ifc_ctrl)
771                 return;
772
773         ifc_ctrl->regs.gregs = IFC_FCM_BASE_ADDR;
774
775         ver = ifc_in32(&ifc_ctrl->regs.gregs->ifc_rev);
776         if (ver >= FSL_IFC_V2_0_0)
777                 ifc_ctrl->regs.rregs =
778                         (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET;
779         else
780                 ifc_ctrl->regs.rregs =
781                         (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET;
782
783         /* clear event registers */
784         ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.nand_evter_stat, ~0U);
785         ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.pgrdcmpl_evt_stat, ~0U);
786
787         /* Enable error and event for any detected errors */
788         ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.nand_evter_en,
789                   IFC_NAND_EVTER_EN_OPC_EN |
790                   IFC_NAND_EVTER_EN_PGRDCMPL_EN |
791                   IFC_NAND_EVTER_EN_FTOER_EN |
792                   IFC_NAND_EVTER_EN_WPER_EN);
793
794         ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.ncfgr, 0x0);
795 }
796
797 static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
798 {
799 }
800
801 static int fsl_ifc_sram_init(uint32_t ver)
802 {
803         struct fsl_ifc_runtime *ifc = ifc_ctrl->regs.rregs;
804         uint32_t cs = 0, csor = 0, csor_8k = 0, csor_ext = 0;
805         uint32_t ncfgr = 0;
806         u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
807         u32 time_start;
808
809         if (ver > FSL_IFC_V1_1_0) {
810                 ncfgr = ifc_in32(&ifc->ifc_nand.ncfgr);
811                 ifc_out32(&ifc->ifc_nand.ncfgr, ncfgr | IFC_NAND_SRAM_INIT_EN);
812
813                 /* wait for  SRAM_INIT bit to be clear or timeout */
814                 time_start = get_timer(0);
815                 while (get_timer(time_start) < timeo) {
816                         ifc_ctrl->status =
817                                 ifc_in32(&ifc->ifc_nand.nand_evter_stat);
818
819                         if (!(ifc_ctrl->status & IFC_NAND_SRAM_INIT_EN))
820                                 return 0;
821                 }
822                 printf("fsl-ifc: Failed to Initialise SRAM\n");
823                 return 1;
824         }
825
826         cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT;
827
828         /* Save CSOR and CSOR_ext */
829         csor = ifc_in32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor);
830         csor_ext = ifc_in32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor_ext);
831
832         /* chage PageSize 8K and SpareSize 1K*/
833         csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
834         ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor, csor_8k);
835         ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor_ext, 0x0000400);
836
837         /* READID */
838         ifc_out32(&ifc->ifc_nand.nand_fir0,
839                   (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
840                   (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
841                   (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
842         ifc_out32(&ifc->ifc_nand.nand_fcr0,
843                   NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT);
844         ifc_out32(&ifc->ifc_nand.row3, 0x0);
845
846         ifc_out32(&ifc->ifc_nand.nand_fbcr, 0x0);
847
848         /* Program ROW0/COL0 */
849         ifc_out32(&ifc->ifc_nand.row0, 0x0);
850         ifc_out32(&ifc->ifc_nand.col0, 0x0);
851
852         /* set the chip select for NAND Transaction */
853         ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
854
855         /* start read seq */
856         ifc_out32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
857
858         time_start = get_timer(0);
859
860         while (get_timer(time_start) < timeo) {
861                 ifc_ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
862
863                 if (ifc_ctrl->status & IFC_NAND_EVTER_STAT_OPC)
864                         break;
865         }
866
867         if (ifc_ctrl->status != IFC_NAND_EVTER_STAT_OPC) {
868                 printf("fsl-ifc: Failed to Initialise SRAM\n");
869                 return 1;
870         }
871
872         ifc_out32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status);
873
874         /* Restore CSOR and CSOR_ext */
875         ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor, csor);
876         ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor_ext, csor_ext);
877
878         return 0;
879 }
880
881 static int fsl_ifc_chip_init(int devnum, u8 *addr)
882 {
883         struct mtd_info *mtd;
884         struct nand_chip *nand;
885         struct fsl_ifc_mtd *priv;
886         struct nand_ecclayout *layout;
887         struct fsl_ifc_fcm *gregs = NULL;
888         uint32_t cspr = 0, csor = 0, ver = 0;
889         int ret = 0;
890
891         if (!ifc_ctrl) {
892                 fsl_ifc_ctrl_init();
893                 if (!ifc_ctrl)
894                         return -1;
895         }
896
897         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
898         if (!priv)
899                 return -ENOMEM;
900
901         priv->ctrl = ifc_ctrl;
902         priv->vbase = addr;
903         gregs = ifc_ctrl->regs.gregs;
904
905         /* Find which chip select it is connected to.
906          */
907         for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
908                 phys_addr_t phys_addr = virt_to_phys(addr);
909
910                 cspr = ifc_in32(&gregs->cspr_cs[priv->bank].cspr);
911                 csor = ifc_in32(&gregs->csor_cs[priv->bank].csor);
912
913                 if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND &&
914                     (cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr)) {
915                         ifc_ctrl->cs_nand = priv->bank << IFC_NAND_CSEL_SHIFT;
916                         break;
917                 }
918         }
919
920         if (priv->bank >= MAX_BANKS) {
921                 printf("%s: address did not match any "
922                        "chip selects\n", __func__);
923                 kfree(priv);
924                 return -ENODEV;
925         }
926
927         nand = &priv->chip;
928         mtd = &nand->mtd;
929         mtd->priv = nand;
930
931         ifc_ctrl->chips[priv->bank] = priv;
932
933         /* fill in nand_chip structure */
934         /* set up function call table */
935
936         nand->write_buf = fsl_ifc_write_buf;
937         nand->read_buf = fsl_ifc_read_buf;
938         nand->select_chip = fsl_ifc_select_chip;
939         nand->cmdfunc = fsl_ifc_cmdfunc;
940         nand->waitfunc = fsl_ifc_wait;
941
942         /* set up nand options */
943         nand->bbt_td = &bbt_main_descr;
944         nand->bbt_md = &bbt_mirror_descr;
945
946         /* set up nand options */
947         nand->options = NAND_NO_SUBPAGE_WRITE;
948         nand->bbt_options = NAND_BBT_USE_FLASH;
949
950         if (cspr & CSPR_PORT_SIZE_16) {
951                 nand->read_byte = fsl_ifc_read_byte16;
952                 nand->options |= NAND_BUSWIDTH_16;
953         } else {
954                 nand->read_byte = fsl_ifc_read_byte;
955         }
956
957         nand->controller = &ifc_ctrl->controller;
958         nand->priv = priv;
959
960         nand->ecc.read_page = fsl_ifc_read_page;
961         nand->ecc.write_page = fsl_ifc_write_page;
962
963         /* Hardware generates ECC per 512 Bytes */
964         nand->ecc.size = 512;
965         nand->ecc.bytes = 8;
966
967         switch (csor & CSOR_NAND_PGS_MASK) {
968         case CSOR_NAND_PGS_512:
969                 if (nand->options & NAND_BUSWIDTH_16) {
970                         layout = &oob_512_16bit_ecc4;
971                 } else {
972                         layout = &oob_512_8bit_ecc4;
973
974                         /* Avoid conflict with bad block marker */
975                         bbt_main_descr.offs = 0;
976                         bbt_mirror_descr.offs = 0;
977                 }
978
979                 nand->ecc.strength = 4;
980                 priv->bufnum_mask = 15;
981                 break;
982
983         case CSOR_NAND_PGS_2K:
984                 layout = &oob_2048_ecc4;
985                 nand->ecc.strength = 4;
986                 priv->bufnum_mask = 3;
987                 break;
988
989         case CSOR_NAND_PGS_4K:
990                 if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
991                     CSOR_NAND_ECC_MODE_4) {
992                         layout = &oob_4096_ecc4;
993                         nand->ecc.strength = 4;
994                 } else {
995                         layout = &oob_4096_ecc8;
996                         nand->ecc.strength = 8;
997                         nand->ecc.bytes = 16;
998                 }
999
1000                 priv->bufnum_mask = 1;
1001                 break;
1002
1003         case CSOR_NAND_PGS_8K:
1004                 if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
1005                     CSOR_NAND_ECC_MODE_4) {
1006                         layout = &oob_8192_ecc4;
1007                         nand->ecc.strength = 4;
1008                 } else {
1009                         layout = &oob_8192_ecc8;
1010                         nand->ecc.strength = 8;
1011                         nand->ecc.bytes = 16;
1012                 }
1013
1014                 priv->bufnum_mask = 0;
1015                 break;
1016
1017
1018         default:
1019                 printf("ifc nand: bad csor %#x: bad page size\n", csor);
1020                 return -ENODEV;
1021         }
1022
1023         /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
1024         if (csor & CSOR_NAND_ECC_DEC_EN) {
1025                 nand->ecc.mode = NAND_ECC_HW;
1026                 nand->ecc.layout = layout;
1027         } else {
1028                 nand->ecc.mode = NAND_ECC_SOFT;
1029         }
1030
1031         ver = ifc_in32(&gregs->ifc_rev);
1032         if (ver >= FSL_IFC_V1_1_0)
1033                 ret = fsl_ifc_sram_init(ver);
1034         if (ret)
1035                 return ret;
1036
1037         if (ver >= FSL_IFC_V2_0_0)
1038                 priv->bufnum_mask = (priv->bufnum_mask * 2) + 1;
1039
1040         ret = nand_scan_ident(mtd, 1, NULL);
1041         if (ret)
1042                 return ret;
1043
1044         ret = nand_scan_tail(mtd);
1045         if (ret)
1046                 return ret;
1047
1048         ret = nand_register(devnum, mtd);
1049         if (ret)
1050                 return ret;
1051         return 0;
1052 }
1053
1054 #ifndef CONFIG_SYS_NAND_BASE_LIST
1055 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
1056 #endif
1057
1058 static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] =
1059         CONFIG_SYS_NAND_BASE_LIST;
1060
1061 void board_nand_init(void)
1062 {
1063         int i;
1064
1065         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
1066                 fsl_ifc_chip_init(i, (u8 *)base_address[i]);
1067 }