1 /* Integrated Flash Controller NAND Machine Driver
3 * Copyright (c) 2012 Freescale Semiconductor, Inc
5 * Authors: Dipen Dudhat <Dipen.Dudhat@freescale.com>
7 * SPDX-License-Identifier: GPL-2.0+
14 #include <linux/mtd/mtd.h>
15 #include <linux/mtd/nand.h>
16 #include <linux/mtd/nand_ecc.h>
19 #include <asm/errno.h>
22 #ifndef CONFIG_SYS_FSL_IFC_BANK_COUNT
23 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
26 #define FSL_IFC_V1_1_0 0x01010000
27 #define MAX_BANKS CONFIG_SYS_FSL_IFC_BANK_COUNT
28 #define ERR_BYTE 0xFF /* Value returned for read bytes
30 #define IFC_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for IFC
35 /* mtd information per set */
37 struct nand_chip chip;
38 struct fsl_ifc_ctrl *ctrl;
41 int bank; /* Chip select bank number */
42 unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
43 u8 __iomem *vbase; /* Chip select base virtual address */
46 /* overview of the fsl ifc controller */
48 struct nand_hw_control controller;
49 struct fsl_ifc_mtd *chips[MAX_BANKS];
53 uint8_t __iomem *addr; /* Address of assigned IFC buffer */
54 unsigned int cs_nand; /* On which chipsel NAND is connected */
55 unsigned int page; /* Last page written to / read from */
56 unsigned int read_bytes; /* Number of bytes read during command */
57 unsigned int column; /* Saved column from SEQIN */
58 unsigned int index; /* Pointer to next byte to 'read' */
59 unsigned int status; /* status read from NEESR after last op */
60 unsigned int oob; /* Non zero if operating on OOB data */
61 unsigned int eccread; /* Non zero for a full-page ECC read */
64 static struct fsl_ifc_ctrl *ifc_ctrl;
66 /* 512-byte page with 4-bit ECC, 8-bit */
67 static struct nand_ecclayout oob_512_8bit_ecc4 = {
69 .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
70 .oobfree = { {0, 5}, {6, 2} },
73 /* 512-byte page with 4-bit ECC, 16-bit */
74 static struct nand_ecclayout oob_512_16bit_ecc4 = {
76 .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
77 .oobfree = { {2, 6}, },
80 /* 2048-byte page size with 4-bit ECC */
81 static struct nand_ecclayout oob_2048_ecc4 = {
84 8, 9, 10, 11, 12, 13, 14, 15,
85 16, 17, 18, 19, 20, 21, 22, 23,
86 24, 25, 26, 27, 28, 29, 30, 31,
87 32, 33, 34, 35, 36, 37, 38, 39,
89 .oobfree = { {2, 6}, {40, 24} },
92 /* 4096-byte page size with 4-bit ECC */
93 static struct nand_ecclayout oob_4096_ecc4 = {
96 8, 9, 10, 11, 12, 13, 14, 15,
97 16, 17, 18, 19, 20, 21, 22, 23,
98 24, 25, 26, 27, 28, 29, 30, 31,
99 32, 33, 34, 35, 36, 37, 38, 39,
100 40, 41, 42, 43, 44, 45, 46, 47,
101 48, 49, 50, 51, 52, 53, 54, 55,
102 56, 57, 58, 59, 60, 61, 62, 63,
103 64, 65, 66, 67, 68, 69, 70, 71,
105 .oobfree = { {2, 6}, {72, 56} },
108 /* 4096-byte page size with 8-bit ECC -- requires 218-byte OOB */
109 static struct nand_ecclayout oob_4096_ecc8 = {
112 8, 9, 10, 11, 12, 13, 14, 15,
113 16, 17, 18, 19, 20, 21, 22, 23,
114 24, 25, 26, 27, 28, 29, 30, 31,
115 32, 33, 34, 35, 36, 37, 38, 39,
116 40, 41, 42, 43, 44, 45, 46, 47,
117 48, 49, 50, 51, 52, 53, 54, 55,
118 56, 57, 58, 59, 60, 61, 62, 63,
119 64, 65, 66, 67, 68, 69, 70, 71,
120 72, 73, 74, 75, 76, 77, 78, 79,
121 80, 81, 82, 83, 84, 85, 86, 87,
122 88, 89, 90, 91, 92, 93, 94, 95,
123 96, 97, 98, 99, 100, 101, 102, 103,
124 104, 105, 106, 107, 108, 109, 110, 111,
125 112, 113, 114, 115, 116, 117, 118, 119,
126 120, 121, 122, 123, 124, 125, 126, 127,
127 128, 129, 130, 131, 132, 133, 134, 135,
129 .oobfree = { {2, 6}, {136, 82} },
132 /* 8192-byte page size with 4-bit ECC */
133 static struct nand_ecclayout oob_8192_ecc4 = {
136 8, 9, 10, 11, 12, 13, 14, 15,
137 16, 17, 18, 19, 20, 21, 22, 23,
138 24, 25, 26, 27, 28, 29, 30, 31,
139 32, 33, 34, 35, 36, 37, 38, 39,
140 40, 41, 42, 43, 44, 45, 46, 47,
141 48, 49, 50, 51, 52, 53, 54, 55,
142 56, 57, 58, 59, 60, 61, 62, 63,
143 64, 65, 66, 67, 68, 69, 70, 71,
144 72, 73, 74, 75, 76, 77, 78, 79,
145 80, 81, 82, 83, 84, 85, 86, 87,
146 88, 89, 90, 91, 92, 93, 94, 95,
147 96, 97, 98, 99, 100, 101, 102, 103,
148 104, 105, 106, 107, 108, 109, 110, 111,
149 112, 113, 114, 115, 116, 117, 118, 119,
150 120, 121, 122, 123, 124, 125, 126, 127,
151 128, 129, 130, 131, 132, 133, 134, 135,
153 .oobfree = { {2, 6}, {136, 208} },
156 /* 8192-byte page size with 8-bit ECC -- requires 218-byte OOB */
157 static struct nand_ecclayout oob_8192_ecc8 = {
160 8, 9, 10, 11, 12, 13, 14, 15,
161 16, 17, 18, 19, 20, 21, 22, 23,
162 24, 25, 26, 27, 28, 29, 30, 31,
163 32, 33, 34, 35, 36, 37, 38, 39,
164 40, 41, 42, 43, 44, 45, 46, 47,
165 48, 49, 50, 51, 52, 53, 54, 55,
166 56, 57, 58, 59, 60, 61, 62, 63,
167 64, 65, 66, 67, 68, 69, 70, 71,
168 72, 73, 74, 75, 76, 77, 78, 79,
169 80, 81, 82, 83, 84, 85, 86, 87,
170 88, 89, 90, 91, 92, 93, 94, 95,
171 96, 97, 98, 99, 100, 101, 102, 103,
172 104, 105, 106, 107, 108, 109, 110, 111,
173 112, 113, 114, 115, 116, 117, 118, 119,
174 120, 121, 122, 123, 124, 125, 126, 127,
175 128, 129, 130, 131, 132, 133, 134, 135,
176 136, 137, 138, 139, 140, 141, 142, 143,
177 144, 145, 146, 147, 148, 149, 150, 151,
178 152, 153, 154, 155, 156, 157, 158, 159,
179 160, 161, 162, 163, 164, 165, 166, 167,
180 168, 169, 170, 171, 172, 173, 174, 175,
181 176, 177, 178, 179, 180, 181, 182, 183,
182 184, 185, 186, 187, 188, 189, 190, 191,
183 192, 193, 194, 195, 196, 197, 198, 199,
184 200, 201, 202, 203, 204, 205, 206, 207,
185 208, 209, 210, 211, 212, 213, 214, 215,
186 216, 217, 218, 219, 220, 221, 222, 223,
187 224, 225, 226, 227, 228, 229, 230, 231,
188 232, 233, 234, 235, 236, 237, 238, 239,
189 240, 241, 242, 243, 244, 245, 246, 247,
190 248, 249, 250, 251, 252, 253, 254, 255,
191 256, 257, 258, 259, 260, 261, 262, 263,
193 .oobfree = { {2, 6}, {264, 80} },
197 * Generic flash bbt descriptors
199 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
200 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
202 static struct nand_bbt_descr bbt_main_descr = {
203 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
204 NAND_BBT_2BIT | NAND_BBT_VERSION,
205 .offs = 2, /* 0 on 8-bit small page */
209 .pattern = bbt_pattern,
212 static struct nand_bbt_descr bbt_mirror_descr = {
213 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
214 NAND_BBT_2BIT | NAND_BBT_VERSION,
215 .offs = 2, /* 0 on 8-bit small page */
219 .pattern = mirror_pattern,
223 * Set up the IFC hardware block and page address fields, and the ifc nand
224 * structure addr field to point to the correct IFC buffer in memory
226 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
228 struct nand_chip *chip = mtd->priv;
229 struct fsl_ifc_mtd *priv = chip->priv;
230 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
231 struct fsl_ifc *ifc = ctrl->regs;
234 ctrl->page = page_addr;
236 /* Program ROW0/COL0 */
237 ifc_out32(&ifc->ifc_nand.row0, page_addr);
238 ifc_out32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
240 buf_num = page_addr & priv->bufnum_mask;
242 ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
243 ctrl->index = column;
245 /* for OOB data point to the second half of the buffer */
247 ctrl->index += mtd->writesize;
250 static int is_blank(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
253 struct nand_chip *chip = mtd->priv;
254 struct fsl_ifc_mtd *priv = chip->priv;
255 u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2);
256 u32 __iomem *main = (u32 *)addr;
257 u8 __iomem *oob = addr + mtd->writesize;
260 for (i = 0; i < mtd->writesize / 4; i++) {
261 if (__raw_readl(&main[i]) != 0xffffffff)
265 for (i = 0; i < chip->ecc.layout->eccbytes; i++) {
266 int pos = chip->ecc.layout->eccpos[i];
268 if (__raw_readb(&oob[pos]) != 0xff)
275 /* returns nonzero if entire page is blank */
276 static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
277 u32 *eccstat, unsigned int bufnum)
279 u32 reg = eccstat[bufnum / 4];
282 errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
288 * execute IFC NAND command and wait for it to complete
290 static int fsl_ifc_run_command(struct mtd_info *mtd)
292 struct nand_chip *chip = mtd->priv;
293 struct fsl_ifc_mtd *priv = chip->priv;
294 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
295 struct fsl_ifc *ifc = ctrl->regs;
300 /* set the chip select for NAND Transaction */
301 ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
303 /* start read/write seq */
304 ifc_out32(&ifc->ifc_nand.nandseq_strt,
305 IFC_NAND_SEQ_STRT_FIR_STRT);
307 /* wait for NAND Machine complete flag or timeout */
308 end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
310 while (end_tick > get_ticks()) {
311 ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
313 if (ctrl->status & IFC_NAND_EVTER_STAT_OPC)
317 ifc_out32(&ifc->ifc_nand.nand_evter_stat, ctrl->status);
319 if (ctrl->status & IFC_NAND_EVTER_STAT_FTOER)
320 printf("%s: Flash Time Out Error\n", __func__);
321 if (ctrl->status & IFC_NAND_EVTER_STAT_WPER)
322 printf("%s: Write Protect Error\n", __func__);
326 int bufnum = ctrl->page & priv->bufnum_mask;
327 int sector = bufnum * chip->ecc.steps;
328 int sector_end = sector + chip->ecc.steps - 1;
330 for (i = sector / 4; i <= sector_end / 4; i++)
331 eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]);
333 for (i = sector; i <= sector_end; i++) {
334 errors = check_read_ecc(mtd, ctrl, eccstat, i);
338 * Uncorrectable error.
339 * OK only if the whole page is blank.
341 * We disable ECCER reporting due to erratum
342 * IFC-A002770 -- so report it now if we
343 * see an uncorrectable error in ECCSTAT.
345 if (!is_blank(mtd, ctrl, bufnum))
347 IFC_NAND_EVTER_STAT_ECCER;
351 mtd->ecc_stats.corrected += errors;
357 /* returns 0 on success otherwise non-zero) */
358 return ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO;
361 static void fsl_ifc_do_read(struct nand_chip *chip,
363 struct mtd_info *mtd)
365 struct fsl_ifc_mtd *priv = chip->priv;
366 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
367 struct fsl_ifc *ifc = ctrl->regs;
369 /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
370 if (mtd->writesize > 512) {
371 ifc_out32(&ifc->ifc_nand.nand_fir0,
372 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
373 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
374 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
375 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
376 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
377 ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
379 ifc_out32(&ifc->ifc_nand.nand_fcr0,
380 (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
381 (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
383 ifc_out32(&ifc->ifc_nand.nand_fir0,
384 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
385 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
386 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
387 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
390 ifc_out32(&ifc->ifc_nand.nand_fcr0,
391 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
393 ifc_out32(&ifc->ifc_nand.nand_fcr0,
394 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
398 /* cmdfunc send commands to the IFC NAND Machine */
399 static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
400 int column, int page_addr)
402 struct nand_chip *chip = mtd->priv;
403 struct fsl_ifc_mtd *priv = chip->priv;
404 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
405 struct fsl_ifc *ifc = ctrl->regs;
407 /* clear the read buffer */
408 ctrl->read_bytes = 0;
409 if (command != NAND_CMD_PAGEPROG)
413 /* READ0 read the entire buffer to use hardware ECC. */
414 case NAND_CMD_READ0: {
415 ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
416 set_addr(mtd, 0, page_addr, 0);
418 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
419 ctrl->index += column;
421 if (chip->ecc.mode == NAND_ECC_HW)
424 fsl_ifc_do_read(chip, 0, mtd);
425 fsl_ifc_run_command(mtd);
429 /* READOOB reads only the OOB because no ECC is performed. */
430 case NAND_CMD_READOOB:
431 ifc_out32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
432 set_addr(mtd, column, page_addr, 1);
434 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
436 fsl_ifc_do_read(chip, 1, mtd);
437 fsl_ifc_run_command(mtd);
441 /* READID must read all possible bytes while CEB is active */
442 case NAND_CMD_READID:
443 case NAND_CMD_PARAM: {
444 int timing = IFC_FIR_OP_RB;
445 if (command == NAND_CMD_PARAM)
446 timing = IFC_FIR_OP_RBCD;
448 ifc_out32(&ifc->ifc_nand.nand_fir0,
449 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
450 (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
451 (timing << IFC_NAND_FIR0_OP2_SHIFT));
452 ifc_out32(&ifc->ifc_nand.nand_fcr0,
453 command << IFC_NAND_FCR0_CMD0_SHIFT);
454 ifc_out32(&ifc->ifc_nand.row3, column);
457 * although currently it's 8 bytes for READID, we always read
458 * the maximum 256 bytes(for PARAM)
460 ifc_out32(&ifc->ifc_nand.nand_fbcr, 256);
461 ctrl->read_bytes = 256;
463 set_addr(mtd, 0, 0, 0);
464 fsl_ifc_run_command(mtd);
468 /* ERASE1 stores the block and page address */
469 case NAND_CMD_ERASE1:
470 set_addr(mtd, 0, page_addr, 0);
473 /* ERASE2 uses the block and page address from ERASE1 */
474 case NAND_CMD_ERASE2:
475 ifc_out32(&ifc->ifc_nand.nand_fir0,
476 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
477 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
478 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
480 ifc_out32(&ifc->ifc_nand.nand_fcr0,
481 (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
482 (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
484 ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
485 ctrl->read_bytes = 0;
486 fsl_ifc_run_command(mtd);
489 /* SEQIN sets up the addr buffer and all registers except the length */
490 case NAND_CMD_SEQIN: {
492 ctrl->column = column;
495 if (mtd->writesize > 512) {
497 (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
498 (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
499 (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
501 ifc_out32(&ifc->ifc_nand.nand_fir0,
502 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
503 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
504 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
506 IFC_NAND_FIR0_OP3_SHIFT) |
507 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT));
508 ifc_out32(&ifc->ifc_nand.nand_fir1,
509 (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
510 (IFC_FIR_OP_RDSTAT <<
511 IFC_NAND_FIR1_OP6_SHIFT) |
512 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT));
514 nand_fcr0 = ((NAND_CMD_PAGEPROG <<
515 IFC_NAND_FCR0_CMD1_SHIFT) |
517 IFC_NAND_FCR0_CMD2_SHIFT) |
519 IFC_NAND_FCR0_CMD3_SHIFT));
521 ifc_out32(&ifc->ifc_nand.nand_fir0,
522 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
523 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
524 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
525 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
526 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
527 ifc_out32(&ifc->ifc_nand.nand_fir1,
528 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
529 (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
530 (IFC_FIR_OP_RDSTAT <<
531 IFC_NAND_FIR1_OP7_SHIFT) |
532 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT));
534 if (column >= mtd->writesize)
536 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
539 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
542 if (column >= mtd->writesize) {
543 /* OOB area --> READOOB */
544 column -= mtd->writesize;
547 ifc_out32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
548 set_addr(mtd, column, page_addr, ctrl->oob);
552 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
553 case NAND_CMD_PAGEPROG:
555 ifc_out32(&ifc->ifc_nand.nand_fbcr,
556 ctrl->index - ctrl->column);
558 ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
560 fsl_ifc_run_command(mtd);
563 case NAND_CMD_STATUS:
564 ifc_out32(&ifc->ifc_nand.nand_fir0,
565 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
566 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
567 ifc_out32(&ifc->ifc_nand.nand_fcr0,
568 NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
569 ifc_out32(&ifc->ifc_nand.nand_fbcr, 1);
570 set_addr(mtd, 0, 0, 0);
571 ctrl->read_bytes = 1;
573 fsl_ifc_run_command(mtd);
575 /* Chip sometimes reporting write protect even when it's not */
576 out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
580 ifc_out32(&ifc->ifc_nand.nand_fir0,
581 IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
582 ifc_out32(&ifc->ifc_nand.nand_fcr0,
583 NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
584 fsl_ifc_run_command(mtd);
588 printf("%s: error, unsupported command 0x%x.\n",
594 * Write buf to the IFC NAND Controller Data Buffer
596 static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
598 struct nand_chip *chip = mtd->priv;
599 struct fsl_ifc_mtd *priv = chip->priv;
600 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
601 unsigned int bufsize = mtd->writesize + mtd->oobsize;
604 printf("%s of %d bytes", __func__, len);
609 if ((unsigned int)len > bufsize - ctrl->index) {
610 printf("%s beyond end of buffer "
611 "(%d requested, %u available)\n",
612 __func__, len, bufsize - ctrl->index);
613 len = bufsize - ctrl->index;
616 memcpy_toio(&ctrl->addr[ctrl->index], buf, len);
621 * read a byte from either the IFC hardware buffer if it has any data left
622 * otherwise issue a command to read a single byte.
624 static u8 fsl_ifc_read_byte(struct mtd_info *mtd)
626 struct nand_chip *chip = mtd->priv;
627 struct fsl_ifc_mtd *priv = chip->priv;
628 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
630 /* If there are still bytes in the IFC buffer, then use the
632 if (ctrl->index < ctrl->read_bytes)
633 return in_8(&ctrl->addr[ctrl->index++]);
635 printf("%s beyond end of buffer\n", __func__);
640 * Read two bytes from the IFC hardware buffer
641 * read function for 16-bit buswith
643 static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
645 struct nand_chip *chip = mtd->priv;
646 struct fsl_ifc_mtd *priv = chip->priv;
647 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
651 * If there are still bytes in the IFC buffer, then use the
654 if (ctrl->index < ctrl->read_bytes) {
655 data = ifc_in16((uint16_t *)&ctrl->
658 return (uint8_t)data;
661 printf("%s beyond end of buffer\n", __func__);
666 * Read from the IFC Controller Data Buffer
668 static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
670 struct nand_chip *chip = mtd->priv;
671 struct fsl_ifc_mtd *priv = chip->priv;
672 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
678 avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
679 memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail);
680 ctrl->index += avail;
683 printf("%s beyond end of buffer "
684 "(%d requested, %d available)\n",
685 __func__, len, avail);
689 * Verify buffer against the IFC Controller Data Buffer
691 static int fsl_ifc_verify_buf(struct mtd_info *mtd,
692 const u_char *buf, int len)
694 struct nand_chip *chip = mtd->priv;
695 struct fsl_ifc_mtd *priv = chip->priv;
696 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
700 printf("%s of %d bytes", __func__, len);
704 if ((unsigned int)len > ctrl->read_bytes - ctrl->index) {
705 printf("%s beyond end of buffer "
706 "(%d requested, %u available)\n",
707 __func__, len, ctrl->read_bytes - ctrl->index);
709 ctrl->index = ctrl->read_bytes;
713 for (i = 0; i < len; i++)
714 if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i])
718 return i == len && ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO;
721 /* This function is called after Program and Erase Operations to
722 * check for success or failure.
724 static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
726 struct fsl_ifc_mtd *priv = chip->priv;
727 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
728 struct fsl_ifc *ifc = ctrl->regs;
731 if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
732 return NAND_STATUS_FAIL;
734 /* Use READ_STATUS command, but wait for the device to be ready */
735 ifc_out32(&ifc->ifc_nand.nand_fir0,
736 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
737 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
738 ifc_out32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
739 IFC_NAND_FCR0_CMD0_SHIFT);
740 ifc_out32(&ifc->ifc_nand.nand_fbcr, 1);
741 set_addr(mtd, 0, 0, 0);
742 ctrl->read_bytes = 1;
744 fsl_ifc_run_command(mtd);
746 if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
747 return NAND_STATUS_FAIL;
749 nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
751 /* Chip sometimes reporting write protect even when it's not */
752 nand_fsr = nand_fsr | NAND_STATUS_WP;
756 static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
757 uint8_t *buf, int oob_required, int page)
759 struct fsl_ifc_mtd *priv = chip->priv;
760 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
762 fsl_ifc_read_buf(mtd, buf, mtd->writesize);
763 fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
765 if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
766 mtd->ecc_stats.failed++;
771 /* ECC will be calculated automatically, and errors will be detected in
774 static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
775 const uint8_t *buf, int oob_required)
777 fsl_ifc_write_buf(mtd, buf, mtd->writesize);
778 fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
783 static void fsl_ifc_ctrl_init(void)
785 ifc_ctrl = kzalloc(sizeof(*ifc_ctrl), GFP_KERNEL);
789 ifc_ctrl->regs = IFC_BASE_ADDR;
791 /* clear event registers */
792 ifc_out32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U);
793 ifc_out32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U);
795 /* Enable error and event for any detected errors */
796 ifc_out32(&ifc_ctrl->regs->ifc_nand.nand_evter_en,
797 IFC_NAND_EVTER_EN_OPC_EN |
798 IFC_NAND_EVTER_EN_PGRDCMPL_EN |
799 IFC_NAND_EVTER_EN_FTOER_EN |
800 IFC_NAND_EVTER_EN_WPER_EN);
802 ifc_out32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0);
805 static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
809 static int fsl_ifc_sram_init(uint32_t ver)
811 struct fsl_ifc *ifc = ifc_ctrl->regs;
812 uint32_t cs = 0, csor = 0, csor_8k = 0, csor_ext = 0;
816 if (ver > FSL_IFC_V1_1_0) {
817 ncfgr = ifc_in32(&ifc->ifc_nand.ncfgr);
818 ifc_out32(&ifc->ifc_nand.ncfgr, ncfgr | IFC_NAND_SRAM_INIT_EN);
820 /* wait for SRAM_INIT bit to be clear or timeout */
821 end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
822 while (end_tick > get_ticks()) {
824 ifc_in32(&ifc->ifc_nand.nand_evter_stat);
826 if (!(ifc_ctrl->status & IFC_NAND_SRAM_INIT_EN))
829 printf("fsl-ifc: Failed to Initialise SRAM\n");
833 cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT;
835 /* Save CSOR and CSOR_ext */
836 csor = ifc_in32(&ifc_ctrl->regs->csor_cs[cs].csor);
837 csor_ext = ifc_in32(&ifc_ctrl->regs->csor_cs[cs].csor_ext);
839 /* chage PageSize 8K and SpareSize 1K*/
840 csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
841 ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor_8k);
842 ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, 0x0000400);
845 ifc_out32(&ifc->ifc_nand.nand_fir0,
846 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
847 (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
848 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
849 ifc_out32(&ifc->ifc_nand.nand_fcr0,
850 NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT);
851 ifc_out32(&ifc->ifc_nand.row3, 0x0);
853 ifc_out32(&ifc->ifc_nand.nand_fbcr, 0x0);
855 /* Program ROW0/COL0 */
856 ifc_out32(&ifc->ifc_nand.row0, 0x0);
857 ifc_out32(&ifc->ifc_nand.col0, 0x0);
859 /* set the chip select for NAND Transaction */
860 ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
863 ifc_out32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
865 /* wait for NAND Machine complete flag or timeout */
866 end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
868 while (end_tick > get_ticks()) {
869 ifc_ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
871 if (ifc_ctrl->status & IFC_NAND_EVTER_STAT_OPC)
875 if (ifc_ctrl->status != IFC_NAND_EVTER_STAT_OPC) {
876 printf("fsl-ifc: Failed to Initialise SRAM\n");
880 ifc_out32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status);
882 /* Restore CSOR and CSOR_ext */
883 ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor);
884 ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext);
889 static int fsl_ifc_chip_init(int devnum, u8 *addr)
891 struct mtd_info *mtd = &nand_info[devnum];
892 struct nand_chip *nand;
893 struct fsl_ifc_mtd *priv;
894 struct nand_ecclayout *layout;
895 uint32_t cspr = 0, csor = 0, ver = 0;
904 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
908 priv->ctrl = ifc_ctrl;
911 /* Find which chip select it is connected to.
913 for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
914 phys_addr_t phys_addr = virt_to_phys(addr);
916 cspr = ifc_in32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr);
917 csor = ifc_in32(&ifc_ctrl->regs->csor_cs[priv->bank].csor);
919 if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND &&
920 (cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr)) {
921 ifc_ctrl->cs_nand = priv->bank << IFC_NAND_CSEL_SHIFT;
926 if (priv->bank >= MAX_BANKS) {
927 printf("%s: address did not match any "
928 "chip selects\n", __func__);
936 ifc_ctrl->chips[priv->bank] = priv;
938 /* fill in nand_chip structure */
939 /* set up function call table */
941 nand->write_buf = fsl_ifc_write_buf;
942 nand->read_buf = fsl_ifc_read_buf;
943 nand->verify_buf = fsl_ifc_verify_buf;
944 nand->select_chip = fsl_ifc_select_chip;
945 nand->cmdfunc = fsl_ifc_cmdfunc;
946 nand->waitfunc = fsl_ifc_wait;
948 /* set up nand options */
949 nand->bbt_td = &bbt_main_descr;
950 nand->bbt_md = &bbt_mirror_descr;
952 /* set up nand options */
953 nand->options = NAND_NO_SUBPAGE_WRITE;
954 nand->bbt_options = NAND_BBT_USE_FLASH;
956 if (cspr & CSPR_PORT_SIZE_16) {
957 nand->read_byte = fsl_ifc_read_byte16;
958 nand->options |= NAND_BUSWIDTH_16;
960 nand->read_byte = fsl_ifc_read_byte;
963 nand->controller = &ifc_ctrl->controller;
966 nand->ecc.read_page = fsl_ifc_read_page;
967 nand->ecc.write_page = fsl_ifc_write_page;
969 /* Hardware generates ECC per 512 Bytes */
970 nand->ecc.size = 512;
973 switch (csor & CSOR_NAND_PGS_MASK) {
974 case CSOR_NAND_PGS_512:
975 if (nand->options & NAND_BUSWIDTH_16) {
976 layout = &oob_512_16bit_ecc4;
978 layout = &oob_512_8bit_ecc4;
980 /* Avoid conflict with bad block marker */
981 bbt_main_descr.offs = 0;
982 bbt_mirror_descr.offs = 0;
985 nand->ecc.strength = 4;
986 priv->bufnum_mask = 15;
989 case CSOR_NAND_PGS_2K:
990 layout = &oob_2048_ecc4;
991 nand->ecc.strength = 4;
992 priv->bufnum_mask = 3;
995 case CSOR_NAND_PGS_4K:
996 if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
997 CSOR_NAND_ECC_MODE_4) {
998 layout = &oob_4096_ecc4;
999 nand->ecc.strength = 4;
1001 layout = &oob_4096_ecc8;
1002 nand->ecc.strength = 8;
1003 nand->ecc.bytes = 16;
1006 priv->bufnum_mask = 1;
1009 case CSOR_NAND_PGS_8K:
1010 if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
1011 CSOR_NAND_ECC_MODE_4) {
1012 layout = &oob_8192_ecc4;
1013 nand->ecc.strength = 4;
1015 layout = &oob_8192_ecc8;
1016 nand->ecc.strength = 8;
1017 nand->ecc.bytes = 16;
1020 priv->bufnum_mask = 0;
1025 printf("ifc nand: bad csor %#x: bad page size\n", csor);
1029 /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
1030 if (csor & CSOR_NAND_ECC_DEC_EN) {
1031 nand->ecc.mode = NAND_ECC_HW;
1032 nand->ecc.layout = layout;
1034 nand->ecc.mode = NAND_ECC_SOFT;
1037 ver = ifc_in32(&ifc_ctrl->regs->ifc_rev);
1038 if (ver >= FSL_IFC_V1_1_0)
1039 ret = fsl_ifc_sram_init(ver);
1043 ret = nand_scan_ident(mtd, 1, NULL);
1047 ret = nand_scan_tail(mtd);
1051 ret = nand_register(devnum);
1057 #ifndef CONFIG_SYS_NAND_BASE_LIST
1058 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
1061 static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] =
1062 CONFIG_SYS_NAND_BASE_LIST;
1064 void board_nand_init(void)
1068 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
1069 fsl_ifc_chip_init(i, (u8 *)base_address[i]);