1 /* Integrated Flash Controller NAND Machine Driver
3 * Copyright (c) 2012 Freescale Semiconductor, Inc
5 * Authors: Dipen Dudhat <Dipen.Dudhat@freescale.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/mtd/mtd.h>
26 #include <linux/mtd/nand.h>
27 #include <linux/mtd/nand_ecc.h>
30 #include <asm/errno.h>
31 #include <asm/fsl_ifc.h>
34 #define ERR_BYTE 0xFF /* Value returned for read bytes
36 #define IFC_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for IFC
41 /* mtd information per set */
44 struct nand_chip chip;
45 struct fsl_ifc_ctrl *ctrl;
48 int bank; /* Chip select bank number */
49 unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
50 u8 __iomem *vbase; /* Chip select base virtual address */
53 /* overview of the fsl ifc controller */
55 struct nand_hw_control controller;
56 struct fsl_ifc_mtd *chips[MAX_BANKS];
60 uint8_t __iomem *addr; /* Address of assigned IFC buffer */
61 unsigned int cs_nand; /* On which chipsel NAND is connected */
62 unsigned int page; /* Last page written to / read from */
63 unsigned int read_bytes; /* Number of bytes read during command */
64 unsigned int column; /* Saved column from SEQIN */
65 unsigned int index; /* Pointer to next byte to 'read' */
66 unsigned int status; /* status read from NEESR after last op */
67 unsigned int oob; /* Non zero if operating on OOB data */
68 unsigned int eccread; /* Non zero for a full-page ECC read */
71 static struct fsl_ifc_ctrl *ifc_ctrl;
73 /* 512-byte page with 4-bit ECC, 8-bit */
74 static struct nand_ecclayout oob_512_8bit_ecc4 = {
76 .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
77 .oobfree = { {0, 5}, {6, 2} },
80 /* 512-byte page with 4-bit ECC, 16-bit */
81 static struct nand_ecclayout oob_512_16bit_ecc4 = {
83 .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
84 .oobfree = { {2, 6}, },
87 /* 2048-byte page size with 4-bit ECC */
88 static struct nand_ecclayout oob_2048_ecc4 = {
91 8, 9, 10, 11, 12, 13, 14, 15,
92 16, 17, 18, 19, 20, 21, 22, 23,
93 24, 25, 26, 27, 28, 29, 30, 31,
94 32, 33, 34, 35, 36, 37, 38, 39,
96 .oobfree = { {2, 6}, {40, 24} },
99 /* 4096-byte page size with 4-bit ECC */
100 static struct nand_ecclayout oob_4096_ecc4 = {
103 8, 9, 10, 11, 12, 13, 14, 15,
104 16, 17, 18, 19, 20, 21, 22, 23,
105 24, 25, 26, 27, 28, 29, 30, 31,
106 32, 33, 34, 35, 36, 37, 38, 39,
107 40, 41, 42, 43, 44, 45, 46, 47,
108 48, 49, 50, 51, 52, 53, 54, 55,
109 56, 57, 58, 59, 60, 61, 62, 63,
110 64, 65, 66, 67, 68, 69, 70, 71,
112 .oobfree = { {2, 6}, {72, 56} },
115 /* 4096-byte page size with 8-bit ECC -- requires 218-byte OOB */
116 static struct nand_ecclayout oob_4096_ecc8 = {
119 8, 9, 10, 11, 12, 13, 14, 15,
120 16, 17, 18, 19, 20, 21, 22, 23,
121 24, 25, 26, 27, 28, 29, 30, 31,
122 32, 33, 34, 35, 36, 37, 38, 39,
123 40, 41, 42, 43, 44, 45, 46, 47,
124 48, 49, 50, 51, 52, 53, 54, 55,
125 56, 57, 58, 59, 60, 61, 62, 63,
126 64, 65, 66, 67, 68, 69, 70, 71,
127 72, 73, 74, 75, 76, 77, 78, 79,
128 80, 81, 82, 83, 84, 85, 86, 87,
129 88, 89, 90, 91, 92, 93, 94, 95,
130 96, 97, 98, 99, 100, 101, 102, 103,
131 104, 105, 106, 107, 108, 109, 110, 111,
132 112, 113, 114, 115, 116, 117, 118, 119,
133 120, 121, 122, 123, 124, 125, 126, 127,
134 128, 129, 130, 131, 132, 133, 134, 135,
136 .oobfree = { {2, 6}, {136, 82} },
141 * Generic flash bbt descriptors
143 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
144 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
146 static struct nand_bbt_descr bbt_main_descr = {
147 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
148 NAND_BBT_2BIT | NAND_BBT_VERSION,
149 .offs = 2, /* 0 on 8-bit small page */
153 .pattern = bbt_pattern,
156 static struct nand_bbt_descr bbt_mirror_descr = {
157 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
158 NAND_BBT_2BIT | NAND_BBT_VERSION,
159 .offs = 2, /* 0 on 8-bit small page */
163 .pattern = mirror_pattern,
167 * Set up the IFC hardware block and page address fields, and the ifc nand
168 * structure addr field to point to the correct IFC buffer in memory
170 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
172 struct nand_chip *chip = mtd->priv;
173 struct fsl_ifc_mtd *priv = chip->priv;
174 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
175 struct fsl_ifc *ifc = ctrl->regs;
178 ctrl->page = page_addr;
180 /* Program ROW0/COL0 */
181 out_be32(&ifc->ifc_nand.row0, page_addr);
182 out_be32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
184 buf_num = page_addr & priv->bufnum_mask;
186 ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
187 ctrl->index = column;
189 /* for OOB data point to the second half of the buffer */
191 ctrl->index += mtd->writesize;
194 static int is_blank(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
197 struct nand_chip *chip = mtd->priv;
198 struct fsl_ifc_mtd *priv = chip->priv;
199 u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2);
200 u32 __iomem *main = (u32 *)addr;
201 u8 __iomem *oob = addr + mtd->writesize;
204 for (i = 0; i < mtd->writesize / 4; i++) {
205 if (__raw_readl(&main[i]) != 0xffffffff)
209 for (i = 0; i < chip->ecc.layout->eccbytes; i++) {
210 int pos = chip->ecc.layout->eccpos[i];
212 if (__raw_readb(&oob[pos]) != 0xff)
219 /* returns nonzero if entire page is blank */
220 static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
221 u32 *eccstat, unsigned int bufnum)
223 u32 reg = eccstat[bufnum / 4];
226 errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
232 * execute IFC NAND command and wait for it to complete
234 static int fsl_ifc_run_command(struct mtd_info *mtd)
236 struct nand_chip *chip = mtd->priv;
237 struct fsl_ifc_mtd *priv = chip->priv;
238 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
239 struct fsl_ifc *ifc = ctrl->regs;
244 /* set the chip select for NAND Transaction */
245 out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
247 /* start read/write seq */
248 out_be32(&ifc->ifc_nand.nandseq_strt,
249 IFC_NAND_SEQ_STRT_FIR_STRT);
251 /* wait for NAND Machine complete flag or timeout */
252 end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
254 while (end_tick > get_ticks()) {
255 ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat);
257 if (ctrl->status & IFC_NAND_EVTER_STAT_OPC)
261 out_be32(&ifc->ifc_nand.nand_evter_stat, ctrl->status);
263 if (ctrl->status & IFC_NAND_EVTER_STAT_FTOER)
264 printf("%s: Flash Time Out Error\n", __func__);
265 if (ctrl->status & IFC_NAND_EVTER_STAT_WPER)
266 printf("%s: Write Protect Error\n", __func__);
270 int bufnum = ctrl->page & priv->bufnum_mask;
271 int sector = bufnum * chip->ecc.steps;
272 int sector_end = sector + chip->ecc.steps - 1;
274 for (i = sector / 4; i <= sector_end / 4; i++)
275 eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]);
277 for (i = sector; i <= sector_end; i++) {
278 errors = check_read_ecc(mtd, ctrl, eccstat, i);
282 * Uncorrectable error.
283 * OK only if the whole page is blank.
285 * We disable ECCER reporting due to erratum
286 * IFC-A002770 -- so report it now if we
287 * see an uncorrectable error in ECCSTAT.
289 if (!is_blank(mtd, ctrl, bufnum))
291 IFC_NAND_EVTER_STAT_ECCER;
295 mtd->ecc_stats.corrected += errors;
301 /* returns 0 on success otherwise non-zero) */
302 return ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO;
305 static void fsl_ifc_do_read(struct nand_chip *chip,
307 struct mtd_info *mtd)
309 struct fsl_ifc_mtd *priv = chip->priv;
310 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
311 struct fsl_ifc *ifc = ctrl->regs;
313 /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
314 if (mtd->writesize > 512) {
315 out_be32(&ifc->ifc_nand.nand_fir0,
316 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
317 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
318 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
319 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
320 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
321 out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
323 out_be32(&ifc->ifc_nand.nand_fcr0,
324 (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
325 (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
327 out_be32(&ifc->ifc_nand.nand_fir0,
328 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
329 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
330 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
331 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
334 out_be32(&ifc->ifc_nand.nand_fcr0,
335 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
337 out_be32(&ifc->ifc_nand.nand_fcr0,
338 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
342 /* cmdfunc send commands to the IFC NAND Machine */
343 static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
344 int column, int page_addr)
346 struct nand_chip *chip = mtd->priv;
347 struct fsl_ifc_mtd *priv = chip->priv;
348 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
349 struct fsl_ifc *ifc = ctrl->regs;
351 /* clear the read buffer */
352 ctrl->read_bytes = 0;
353 if (command != NAND_CMD_PAGEPROG)
357 /* READ0 read the entire buffer to use hardware ECC. */
358 case NAND_CMD_READ0: {
359 out_be32(&ifc->ifc_nand.nand_fbcr, 0);
360 set_addr(mtd, 0, page_addr, 0);
362 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
363 ctrl->index += column;
365 if (chip->ecc.mode == NAND_ECC_HW)
368 fsl_ifc_do_read(chip, 0, mtd);
369 fsl_ifc_run_command(mtd);
373 /* READOOB reads only the OOB because no ECC is performed. */
374 case NAND_CMD_READOOB:
375 out_be32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
376 set_addr(mtd, column, page_addr, 1);
378 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
380 fsl_ifc_do_read(chip, 1, mtd);
381 fsl_ifc_run_command(mtd);
385 /* READID must read all possible bytes while CEB is active */
386 case NAND_CMD_READID:
387 case NAND_CMD_PARAM: {
388 int timing = IFC_FIR_OP_RB;
389 if (command == NAND_CMD_PARAM)
390 timing = IFC_FIR_OP_RBCD;
392 out_be32(&ifc->ifc_nand.nand_fir0,
393 (IFC_FIR_OP_CMD0 << IFC_NAND_FIR0_OP0_SHIFT) |
394 (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
395 (timing << IFC_NAND_FIR0_OP2_SHIFT));
396 out_be32(&ifc->ifc_nand.nand_fcr0,
397 command << IFC_NAND_FCR0_CMD0_SHIFT);
398 out_be32(&ifc->ifc_nand.row3, column);
401 * although currently it's 8 bytes for READID, we always read
402 * the maximum 256 bytes(for PARAM)
404 out_be32(&ifc->ifc_nand.nand_fbcr, 256);
405 ctrl->read_bytes = 256;
407 set_addr(mtd, 0, 0, 0);
408 fsl_ifc_run_command(mtd);
412 /* ERASE1 stores the block and page address */
413 case NAND_CMD_ERASE1:
414 set_addr(mtd, 0, page_addr, 0);
417 /* ERASE2 uses the block and page address from ERASE1 */
418 case NAND_CMD_ERASE2:
419 out_be32(&ifc->ifc_nand.nand_fir0,
420 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
421 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
422 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
424 out_be32(&ifc->ifc_nand.nand_fcr0,
425 (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
426 (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
428 out_be32(&ifc->ifc_nand.nand_fbcr, 0);
429 ctrl->read_bytes = 0;
430 fsl_ifc_run_command(mtd);
433 /* SEQIN sets up the addr buffer and all registers except the length */
434 case NAND_CMD_SEQIN: {
436 ctrl->column = column;
439 if (mtd->writesize > 512) {
441 (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
442 (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD1_SHIFT);
444 out_be32(&ifc->ifc_nand.nand_fir0,
445 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
446 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
447 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
448 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
449 (IFC_FIR_OP_CW1 << IFC_NAND_FIR0_OP4_SHIFT));
450 out_be32(&ifc->ifc_nand.nand_fir1, 0);
452 nand_fcr0 = ((NAND_CMD_PAGEPROG <<
453 IFC_NAND_FCR0_CMD1_SHIFT) |
455 IFC_NAND_FCR0_CMD2_SHIFT));
457 out_be32(&ifc->ifc_nand.nand_fir0,
458 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
459 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
460 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
461 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
462 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
463 out_be32(&ifc->ifc_nand.nand_fir1,
464 (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT));
466 if (column >= mtd->writesize)
468 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
471 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
474 if (column >= mtd->writesize) {
475 /* OOB area --> READOOB */
476 column -= mtd->writesize;
479 out_be32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
480 set_addr(mtd, column, page_addr, ctrl->oob);
484 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
485 case NAND_CMD_PAGEPROG:
487 out_be32(&ifc->ifc_nand.nand_fbcr,
488 ctrl->index - ctrl->column);
490 out_be32(&ifc->ifc_nand.nand_fbcr, 0);
492 fsl_ifc_run_command(mtd);
495 case NAND_CMD_STATUS:
496 out_be32(&ifc->ifc_nand.nand_fir0,
497 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
498 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
499 out_be32(&ifc->ifc_nand.nand_fcr0,
500 NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
501 out_be32(&ifc->ifc_nand.nand_fbcr, 1);
502 set_addr(mtd, 0, 0, 0);
503 ctrl->read_bytes = 1;
505 fsl_ifc_run_command(mtd);
507 /* Chip sometimes reporting write protect even when it's not */
508 out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
512 out_be32(&ifc->ifc_nand.nand_fir0,
513 IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
514 out_be32(&ifc->ifc_nand.nand_fcr0,
515 NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
516 fsl_ifc_run_command(mtd);
520 printf("%s: error, unsupported command 0x%x.\n",
526 * Write buf to the IFC NAND Controller Data Buffer
528 static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
530 struct nand_chip *chip = mtd->priv;
531 struct fsl_ifc_mtd *priv = chip->priv;
532 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
533 unsigned int bufsize = mtd->writesize + mtd->oobsize;
536 printf("%s of %d bytes", __func__, len);
541 if ((unsigned int)len > bufsize - ctrl->index) {
542 printf("%s beyond end of buffer "
543 "(%d requested, %u available)\n",
544 __func__, len, bufsize - ctrl->index);
545 len = bufsize - ctrl->index;
548 memcpy_toio(&ctrl->addr[ctrl->index], buf, len);
553 * read a byte from either the IFC hardware buffer if it has any data left
554 * otherwise issue a command to read a single byte.
556 static u8 fsl_ifc_read_byte(struct mtd_info *mtd)
558 struct nand_chip *chip = mtd->priv;
559 struct fsl_ifc_mtd *priv = chip->priv;
560 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
562 /* If there are still bytes in the IFC buffer, then use the
564 if (ctrl->index < ctrl->read_bytes)
565 return in_8(&ctrl->addr[ctrl->index++]);
567 printf("%s beyond end of buffer\n", __func__);
572 * Read two bytes from the IFC hardware buffer
573 * read function for 16-bit buswith
575 static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
577 struct nand_chip *chip = mtd->priv;
578 struct fsl_ifc_mtd *priv = chip->priv;
579 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
583 * If there are still bytes in the IFC buffer, then use the
586 if (ctrl->index < ctrl->read_bytes) {
587 data = in_be16((uint16_t *)&ctrl->
590 return (uint8_t)data;
593 printf("%s beyond end of buffer\n", __func__);
598 * Read from the IFC Controller Data Buffer
600 static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
602 struct nand_chip *chip = mtd->priv;
603 struct fsl_ifc_mtd *priv = chip->priv;
604 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
610 avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
611 memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail);
612 ctrl->index += avail;
615 printf("%s beyond end of buffer "
616 "(%d requested, %d available)\n",
617 __func__, len, avail);
621 * Verify buffer against the IFC Controller Data Buffer
623 static int fsl_ifc_verify_buf(struct mtd_info *mtd,
624 const u_char *buf, int len)
626 struct nand_chip *chip = mtd->priv;
627 struct fsl_ifc_mtd *priv = chip->priv;
628 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
632 printf("%s of %d bytes", __func__, len);
636 if ((unsigned int)len > ctrl->read_bytes - ctrl->index) {
637 printf("%s beyond end of buffer "
638 "(%d requested, %u available)\n",
639 __func__, len, ctrl->read_bytes - ctrl->index);
641 ctrl->index = ctrl->read_bytes;
645 for (i = 0; i < len; i++)
646 if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i])
650 return i == len && ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO;
653 /* This function is called after Program and Erase Operations to
654 * check for success or failure.
656 static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
658 struct fsl_ifc_mtd *priv = chip->priv;
659 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
660 struct fsl_ifc *ifc = ctrl->regs;
663 if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
664 return NAND_STATUS_FAIL;
666 /* Use READ_STATUS command, but wait for the device to be ready */
667 out_be32(&ifc->ifc_nand.nand_fir0,
668 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
669 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
670 out_be32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
671 IFC_NAND_FCR0_CMD0_SHIFT);
672 out_be32(&ifc->ifc_nand.nand_fbcr, 1);
673 set_addr(mtd, 0, 0, 0);
674 ctrl->read_bytes = 1;
676 fsl_ifc_run_command(mtd);
678 if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
679 return NAND_STATUS_FAIL;
681 nand_fsr = in_be32(&ifc->ifc_nand.nand_fsr);
683 /* Chip sometimes reporting write protect even when it's not */
684 nand_fsr = nand_fsr | NAND_STATUS_WP;
688 static int fsl_ifc_read_page(struct mtd_info *mtd,
689 struct nand_chip *chip,
690 uint8_t *buf, int page)
692 struct fsl_ifc_mtd *priv = chip->priv;
693 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
695 fsl_ifc_read_buf(mtd, buf, mtd->writesize);
696 fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
698 if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
699 mtd->ecc_stats.failed++;
704 /* ECC will be calculated automatically, and errors will be detected in
707 static void fsl_ifc_write_page(struct mtd_info *mtd,
708 struct nand_chip *chip,
711 fsl_ifc_write_buf(mtd, buf, mtd->writesize);
712 fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
715 static void fsl_ifc_ctrl_init(void)
717 ifc_ctrl = kzalloc(sizeof(*ifc_ctrl), GFP_KERNEL);
721 ifc_ctrl->regs = IFC_BASE_ADDR;
723 /* clear event registers */
724 out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U);
725 out_be32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U);
727 /* Enable error and event for any detected errors */
728 out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_en,
729 IFC_NAND_EVTER_EN_OPC_EN |
730 IFC_NAND_EVTER_EN_PGRDCMPL_EN |
731 IFC_NAND_EVTER_EN_FTOER_EN |
732 IFC_NAND_EVTER_EN_WPER_EN);
734 out_be32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0);
737 static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
741 int board_nand_init(struct nand_chip *nand)
743 struct fsl_ifc_mtd *priv;
744 struct nand_ecclayout *layout;
745 uint32_t cspr = 0, csor = 0;
753 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
757 priv->ctrl = ifc_ctrl;
758 priv->vbase = nand->IO_ADDR_R;
760 /* Find which chip select it is connected to.
762 for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
763 phys_addr_t base_addr = virt_to_phys(nand->IO_ADDR_R);
765 cspr = in_be32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr);
766 csor = in_be32(&ifc_ctrl->regs->csor_cs[priv->bank].csor);
768 if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND &&
769 (cspr & CSPR_BA) == CSPR_PHYS_ADDR(base_addr)) {
770 ifc_ctrl->cs_nand = priv->bank << IFC_NAND_CSEL_SHIFT;
775 if (priv->bank >= MAX_BANKS) {
776 printf("%s: address did not match any "
777 "chip selects\n", __func__);
782 ifc_ctrl->chips[priv->bank] = priv;
784 /* fill in nand_chip structure */
785 /* set up function call table */
787 nand->write_buf = fsl_ifc_write_buf;
788 nand->read_buf = fsl_ifc_read_buf;
789 nand->verify_buf = fsl_ifc_verify_buf;
790 nand->select_chip = fsl_ifc_select_chip;
791 nand->cmdfunc = fsl_ifc_cmdfunc;
792 nand->waitfunc = fsl_ifc_wait;
794 /* set up nand options */
795 nand->bbt_td = &bbt_main_descr;
796 nand->bbt_md = &bbt_mirror_descr;
798 /* set up nand options */
799 nand->options = NAND_NO_READRDY | NAND_NO_AUTOINCR |
802 if (cspr & CSPR_PORT_SIZE_16) {
803 nand->read_byte = fsl_ifc_read_byte16;
804 nand->options |= NAND_BUSWIDTH_16;
806 nand->read_byte = fsl_ifc_read_byte;
809 nand->controller = &ifc_ctrl->controller;
812 nand->ecc.read_page = fsl_ifc_read_page;
813 nand->ecc.write_page = fsl_ifc_write_page;
815 /* Hardware generates ECC per 512 Bytes */
816 nand->ecc.size = 512;
819 switch (csor & CSOR_NAND_PGS_MASK) {
820 case CSOR_NAND_PGS_512:
821 if (nand->options & NAND_BUSWIDTH_16) {
822 layout = &oob_512_16bit_ecc4;
824 layout = &oob_512_8bit_ecc4;
826 /* Avoid conflict with bad block marker */
827 bbt_main_descr.offs = 0;
828 bbt_mirror_descr.offs = 0;
831 priv->bufnum_mask = 15;
834 case CSOR_NAND_PGS_2K:
835 layout = &oob_2048_ecc4;
836 priv->bufnum_mask = 3;
839 case CSOR_NAND_PGS_4K:
840 if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
841 CSOR_NAND_ECC_MODE_4) {
842 layout = &oob_4096_ecc4;
844 layout = &oob_4096_ecc8;
845 nand->ecc.bytes = 16;
848 priv->bufnum_mask = 1;
852 printf("ifc nand: bad csor %#x: bad page size\n", csor);
856 /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
857 if (csor & CSOR_NAND_ECC_DEC_EN) {
858 nand->ecc.mode = NAND_ECC_HW;
859 nand->ecc.layout = layout;
861 nand->ecc.mode = NAND_ECC_SOFT;