2 * NAND boot for Freescale Integrated Flash Controller, NAND FCM
4 * Copyright 2011 Freescale Semiconductor, Inc.
5 * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <linux/mtd/nand.h>
14 #ifdef CONFIG_CHAIN_OF_TRUST
15 #include <fsl_validate.h>
18 static inline int is_blank(uchar *addr, int page_size)
22 for (i = 0; i < page_size; i++) {
23 if (__raw_readb(&addr[i]) != 0xff)
28 * For the SPL, don't worry about uncorrectable errors
29 * where the main area is all FFs but shouldn't be.
34 /* returns nonzero if entire page is blank */
35 static inline int check_read_ecc(uchar *buf, u32 *eccstat,
36 unsigned int bufnum, int page_size)
38 u32 reg = eccstat[bufnum / 4];
39 int errors = (reg >> ((3 - bufnum % 4) * 8)) & 0xf;
41 if (errors == 0xf) { /* uncorrectable */
42 /* Blank pages fail hw ECC checks */
43 if (is_blank(buf, page_size))
54 static inline struct fsl_ifc_runtime *runtime_regs_address(void)
56 struct fsl_ifc regs = {(void *)CONFIG_SYS_IFC_ADDR, NULL};
59 ver = ifc_in32(®s.gregs->ifc_rev);
60 if (ver >= FSL_IFC_V2_0_0)
61 regs.rregs = (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET;
63 regs.rregs = (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET;
68 static inline void nand_wait(uchar *buf, int bufnum, int page_size)
70 struct fsl_ifc_runtime *ifc = runtime_regs_address();
73 int bufperpage = page_size / 512;
77 bufnum_end = bufnum + bufperpage - 1;
80 status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
81 } while (!(status & IFC_NAND_EVTER_STAT_OPC));
83 if (status & IFC_NAND_EVTER_STAT_FTOER) {
84 puts("flash time out error\n");
89 for (i = bufnum / 4; i <= bufnum_end / 4; i++)
90 eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]);
92 for (i = bufnum; i <= bufnum_end; i++) {
93 if (check_read_ecc(buf, eccstat, i, page_size))
97 ifc_out32(&ifc->ifc_nand.nand_evter_stat, status);
100 static inline int bad_block(uchar *marker, int port_size)
103 return __raw_readb(marker) != 0xff;
105 return __raw_readw((u16 *)marker) != 0xffff;
108 int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
110 struct fsl_ifc_fcm *gregs = (void *)CONFIG_SYS_IFC_ADDR;
111 struct fsl_ifc_runtime *ifc = NULL;
112 uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
118 int bufnum_mask, bufnum, ver = 0;
128 ifc = runtime_regs_address();
130 /* Get NAND Flash configuration */
131 csor = CONFIG_SYS_NAND_CSOR;
132 cspr = CONFIG_SYS_NAND_CSPR;
134 port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8;
136 if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_8K) {
139 } else if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_4K) {
142 } else if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_2K) {
153 ver = ifc_in32(&gregs->ifc_rev);
154 if (ver >= FSL_IFC_V2_0_0)
155 bufnum_mask = (bufnum_mask * 2) + 1;
158 32 << ((csor & CSOR_NAND_PB_MASK) >> CSOR_NAND_PB_SHIFT);
160 blk_size = pages_per_blk * page_size;
162 /* Open Full SRAM mapping for spare are access */
163 ifc_out32(&ifc->ifc_nand.ncfgr, 0x0);
165 /* Clear Boot events */
166 ifc_out32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff);
168 /* Program FIR/FCR for Large/Small page */
169 if (page_size > 512) {
170 ifc_out32(&ifc->ifc_nand.nand_fir0,
171 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
172 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
173 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
174 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
175 (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT));
176 ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
178 ifc_out32(&ifc->ifc_nand.nand_fcr0,
179 (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
180 (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
182 ifc_out32(&ifc->ifc_nand.nand_fir0,
183 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
184 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
185 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
186 (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT));
187 ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
189 ifc_out32(&ifc->ifc_nand.nand_fcr0,
190 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
193 /* Program FBCR = 0 for full page read */
194 ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
196 /* Read and copy u-boot on SDRAM from NAND device, In parallel
197 * check for Bad block if found skip it and read continue to
200 while (pos < uboot_size) {
203 pg_no = offs / page_size;
204 bufnum = pg_no & bufnum_mask;
205 sram_addr = bufnum * page_size * 2;
207 ifc_out32(&ifc->ifc_nand.row0, pg_no);
208 ifc_out32(&ifc->ifc_nand.col0, 0);
210 ifc_out32(&ifc->ifc_nand.nandseq_strt,
211 IFC_NAND_SEQ_STRT_FIR_STRT);
213 /* wait for read to complete */
214 nand_wait(&buf[sram_addr], bufnum, page_size);
217 * If either of the first two pages are marked bad,
218 * continue to the next block.
221 bad_block(&buf[sram_addr + page_size + bad_marker],
224 offs = (offs + blk_size) & ~(blk_size - 1);
225 pos &= ~(blk_size - 1);
229 for (j = 0; j < page_size; j++)
230 dst[pos + j] = __raw_readb(&buf[sram_addr + j]);
234 } while ((offs & (blk_size - 1)) && (pos < uboot_size));
241 * Main entrypoint for NAND Boot. It's necessary that SDRAM is already
242 * configured and available since this code loads the main U-Boot image
243 * from NAND into SDRAM and starts from there.
247 __attribute__((noreturn)) void (*uboot)(void);
249 * Load U-Boot image from NAND into RAM
251 nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
252 CONFIG_SYS_NAND_U_BOOT_SIZE,
253 (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
255 #ifdef CONFIG_NAND_ENV_DST
256 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
257 (uchar *)CONFIG_NAND_ENV_DST);
259 #ifdef CONFIG_ENV_OFFSET_REDUND
260 nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
261 (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
265 * Jump to U-Boot image
267 #ifdef CONFIG_SPL_FLUSH_IMAGE
269 * Clean d-cache and invalidate i-cache, to
270 * make sure that no stale data is executed.
272 flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
275 #ifdef CONFIG_CHAIN_OF_TRUST
277 * U-Boot header is appended at end of U-boot image, so
278 * calculate U-boot header address using U-boot header size.
280 #define CONFIG_U_BOOT_HDR_ADDR \
281 ((CONFIG_SYS_NAND_U_BOOT_START + \
282 CONFIG_SYS_NAND_U_BOOT_SIZE) - \
283 CONFIG_U_BOOT_HDR_SIZE)
284 spl_validate_uboot(CONFIG_U_BOOT_HDR_ADDR,
285 CONFIG_SYS_NAND_U_BOOT_START);
287 * In case of failure in validation, spl_validate_uboot would
288 * not return back in case of Production environment with ITS=1.
289 * Thus U-Boot will not start.
290 * In Development environment (ITS=0 and SB_EN=1), the function
291 * may return back in case of non-fatal failures.
295 uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
299 #ifndef CONFIG_SPL_NAND_INIT
304 void nand_deselect(void)