2 * NAND boot for Freescale Integrated Flash Controller, NAND FCM
4 * Copyright 2011 Freescale Semiconductor, Inc.
5 * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/fsl_ifc.h>
26 #include <linux/mtd/nand.h>
28 static inline int is_blank(uchar *addr, int page_size)
32 for (i = 0; i < page_size; i++) {
33 if (__raw_readb(&addr[i]) != 0xff)
38 * For the SPL, don't worry about uncorrectable errors
39 * where the main area is all FFs but shouldn't be.
44 /* returns nonzero if entire page is blank */
45 static inline int check_read_ecc(uchar *buf, u32 *eccstat,
46 unsigned int bufnum, int page_size)
48 u32 reg = eccstat[bufnum / 4];
49 int errors = (reg >> ((3 - bufnum % 4) * 8)) & 0xf;
51 if (errors == 0xf) { /* uncorrectable */
52 /* Blank pages fail hw ECC checks */
53 if (is_blank(buf, page_size))
64 static inline void nand_wait(uchar *buf, int bufnum, int page_size)
66 struct fsl_ifc *ifc = IFC_BASE_ADDR;
69 int bufperpage = page_size / 512;
73 bufnum_end = bufnum + bufperpage - 1;
76 status = in_be32(&ifc->ifc_nand.nand_evter_stat);
77 } while (!(status & IFC_NAND_EVTER_STAT_OPC));
79 if (status & IFC_NAND_EVTER_STAT_FTOER) {
80 puts("flash time out error\n");
85 for (i = bufnum / 4; i <= bufnum_end / 4; i++)
86 eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]);
88 for (i = bufnum; i <= bufnum_end; i++) {
89 if (check_read_ecc(buf, eccstat, i, page_size))
93 out_be32(&ifc->ifc_nand.nand_evter_stat, status);
96 static inline int bad_block(uchar *marker, int port_size)
99 return __raw_readb(marker) != 0xff;
101 return __raw_readw((u16 *)marker) != 0xffff;
104 static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
106 struct fsl_ifc *ifc = IFC_BASE_ADDR;
107 uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
113 int bufnum_mask, bufnum;
122 /* Get NAND Flash configuration */
123 csor = CONFIG_SYS_NAND_CSOR;
124 cspr = CONFIG_SYS_NAND_CSPR;
126 port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8;
128 if (csor & CSOR_NAND_PGS_4K) {
131 } else if (csor & CSOR_NAND_PGS_2K) {
143 32 << ((csor & CSOR_NAND_PB_MASK) >> CSOR_NAND_PB_SHIFT);
145 blk_size = pages_per_blk * page_size;
147 /* Open Full SRAM mapping for spare are access */
148 out_be32(&ifc->ifc_nand.ncfgr, 0x0);
150 /* Clear Boot events */
151 out_be32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff);
153 /* Program FIR/FCR for Large/Small page */
154 if (page_size > 512) {
155 out_be32(&ifc->ifc_nand.nand_fir0,
156 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
157 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
158 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
159 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
160 (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT));
161 out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
163 out_be32(&ifc->ifc_nand.nand_fcr0,
164 (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
165 (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
167 out_be32(&ifc->ifc_nand.nand_fir0,
168 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
169 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
170 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
171 (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT));
172 out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
174 out_be32(&ifc->ifc_nand.nand_fcr0,
175 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
178 /* Program FBCR = 0 for full page read */
179 out_be32(&ifc->ifc_nand.nand_fbcr, 0);
181 /* Read and copy u-boot on SDRAM from NAND device, In parallel
182 * check for Bad block if found skip it and read continue to
185 while (pos < uboot_size) {
188 pg_no = offs / page_size;
189 bufnum = pg_no & bufnum_mask;
190 sram_addr = bufnum * page_size * 2;
192 out_be32(&ifc->ifc_nand.row0, pg_no);
193 out_be32(&ifc->ifc_nand.col0, 0);
195 out_be32(&ifc->ifc_nand.nandseq_strt,
196 IFC_NAND_SEQ_STRT_FIR_STRT);
198 /* wait for read to complete */
199 nand_wait(&buf[sram_addr], bufnum, page_size);
202 * If either of the first two pages are marked bad,
203 * continue to the next block.
206 bad_block(&buf[sram_addr + page_size + bad_marker],
209 offs = (offs + blk_size) & ~(blk_size - 1);
210 pos &= ~(blk_size - 1);
214 for (j = 0; j < page_size; j++)
215 dst[pos + j] = __raw_readb(&buf[sram_addr + j]);
219 } while ((offs & (blk_size - 1)) && (pos < uboot_size));
224 * Main entrypoint for NAND Boot. It's necessary that SDRAM is already
225 * configured and available since this code loads the main U-boot image
226 * from NAND into SDRAM and starts from there.
230 __attribute__((noreturn)) void (*uboot)(void);
232 * Load U-Boot image from NAND into RAM
234 nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
235 (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
237 #ifdef CONFIG_NAND_ENV_DST
238 nand_load(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
239 (uchar *)CONFIG_NAND_ENV_DST);
241 #ifdef CONFIG_ENV_OFFSET_REDUND
242 nand_load(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
243 (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
247 * Jump to U-Boot image
249 #ifdef CONFIG_SPL_FLUSH_IMAGE
251 * Clean d-cache and invalidate i-cache, to
252 * make sure that no stale data is executed.
254 flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
256 uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;