2 * Platform independend driver for JZ4740.
4 * Copyright (c) 2007 Ingenic Semiconductor Inc.
5 * Author: <jlwei@ingenic.cn>
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/jz4740.h>
15 #define JZ_NAND_DATA_ADDR ((void __iomem *)0xB8000000)
16 #define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000)
17 #define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x10000)
19 #define JZ_NAND_ECC_CTRL_ENCODING BIT(3)
20 #define JZ_NAND_ECC_CTRL_RS BIT(2)
21 #define JZ_NAND_ECC_CTRL_RESET BIT(1)
22 #define JZ_NAND_ECC_CTRL_ENABLE BIT(0)
24 #define EMC_SMCR1_OPT_NAND 0x094c4400
25 /* Optimize the timing of nand */
27 static struct jz4740_emc * emc = (struct jz4740_emc *)JZ4740_EMC_BASE;
29 static struct nand_ecclayout qi_lb60_ecclayout_2gb = {
32 12, 13, 14, 15, 16, 17, 18, 19,
33 20, 21, 22, 23, 24, 25, 26, 27,
34 28, 29, 30, 31, 32, 33, 34, 35,
35 36, 37, 38, 39, 40, 41, 42, 43,
36 44, 45, 46, 47, 48, 49, 50, 51,
37 52, 53, 54, 55, 56, 57, 58, 59,
38 60, 61, 62, 63, 64, 65, 66, 67,
39 68, 69, 70, 71, 72, 73, 74, 75,
40 76, 77, 78, 79, 80, 81, 82, 83 },
48 static int is_reading;
50 static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
52 struct nand_chip *this = mtd->priv;
55 if (ctrl & NAND_CTRL_CHANGE) {
57 this->IO_ADDR_W = JZ_NAND_ADDR_ADDR;
58 else if (ctrl & NAND_CLE)
59 this->IO_ADDR_W = JZ_NAND_CMD_ADDR;
61 this->IO_ADDR_W = JZ_NAND_DATA_ADDR;
63 reg = readl(&emc->nfcsr);
65 reg |= EMC_NFCSR_NFCE1;
67 reg &= ~EMC_NFCSR_NFCE1;
68 writel(reg, &emc->nfcsr);
71 if (cmd != NAND_CMD_NONE)
72 writeb(cmd, this->IO_ADDR_W);
75 static int jz_nand_device_ready(struct mtd_info *mtd)
77 return (readl(GPIO_PXPIN(2)) & 0x40000000) ? 1 : 0;
80 void board_nand_select_device(struct nand_chip *nand, int chip)
83 * Don't use "chip" to address the NAND device,
84 * generate the cs from the address where it is encoded.
88 static int jz_nand_rs_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
98 status = readl(&emc->nfints);
99 } while (!(status & EMC_NFINTS_ENCF));
102 writel(readl(&emc->nfecr) & ~EMC_NFECR_ECCE, &emc->nfecr);
104 for (i = 0; i < 9; i++)
105 ecc_code[i] = readb(&emc->nfpar[i]);
110 static void jz_nand_hwctl(struct mtd_info *mtd, int mode)
114 writel(0, &emc->nfints);
115 reg = readl(&emc->nfecr);
116 reg |= JZ_NAND_ECC_CTRL_RESET;
117 reg |= JZ_NAND_ECC_CTRL_ENABLE;
118 reg |= JZ_NAND_ECC_CTRL_RS;
122 reg &= ~JZ_NAND_ECC_CTRL_ENCODING;
126 reg |= JZ_NAND_ECC_CTRL_ENCODING;
133 writel(reg, &emc->nfecr);
136 /* Correct 1~9-bit errors in 512-bytes data */
137 static void jz_rs_correct(unsigned char *dat, int idx, int mask)
143 i = idx + (idx >> 3);
147 mask <<= (idx & 0x7);
149 dat[i] ^= mask & 0xff;
151 dat[i + 1] ^= (mask >> 8) & 0xff;
154 static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
155 u_char *read_ecc, u_char *calc_ecc)
158 uint32_t errcnt, index, mask, status;
161 const uint8_t all_ff_ecc[] = {
162 0xcd, 0x9d, 0x90, 0x58, 0xf4, 0x8b, 0xff, 0xb7, 0x6f };
164 if (read_ecc[0] == 0xff && read_ecc[1] == 0xff &&
165 read_ecc[2] == 0xff && read_ecc[3] == 0xff &&
166 read_ecc[4] == 0xff && read_ecc[5] == 0xff &&
167 read_ecc[6] == 0xff && read_ecc[7] == 0xff &&
168 read_ecc[8] == 0xff) {
169 for (k = 0; k < 9; k++)
170 writeb(all_ff_ecc[k], &emc->nfpar[k]);
172 for (k = 0; k < 9; k++)
173 writeb(read_ecc[k], &emc->nfpar[k]);
176 writel(readl(&emc->nfecr) | EMC_NFECR_PRDY, &emc->nfecr);
178 /* Wait for completion */
180 status = readl(&emc->nfints);
181 } while (!(status & EMC_NFINTS_DECF));
184 writel(readl(&emc->nfecr) & ~EMC_NFECR_ECCE, &emc->nfecr);
187 if (!(status & EMC_NFINTS_ERR))
190 if (status & EMC_NFINTS_UNCOR) {
191 printf("uncorrectable ecc\n");
195 errcnt = (status & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT;
199 index = (readl(&emc->nferr[3]) & EMC_NFERR_INDEX_MASK) >>
201 mask = (readl(&emc->nferr[3]) & EMC_NFERR_MASK_MASK) >>
203 jz_rs_correct(dat, index, mask);
205 index = (readl(&emc->nferr[2]) & EMC_NFERR_INDEX_MASK) >>
207 mask = (readl(&emc->nferr[2]) & EMC_NFERR_MASK_MASK) >>
209 jz_rs_correct(dat, index, mask);
211 index = (readl(&emc->nferr[1]) & EMC_NFERR_INDEX_MASK) >>
213 mask = (readl(&emc->nferr[1]) & EMC_NFERR_MASK_MASK) >>
215 jz_rs_correct(dat, index, mask);
217 index = (readl(&emc->nferr[0]) & EMC_NFERR_INDEX_MASK) >>
219 mask = (readl(&emc->nferr[0]) & EMC_NFERR_MASK_MASK) >>
221 jz_rs_correct(dat, index, mask);
230 * Main initialization routine
232 int board_nand_init(struct nand_chip *nand)
236 reg = readl(&emc->nfcsr);
237 reg |= EMC_NFCSR_NFE1; /* EMC setup, Set NFE bit */
238 writel(reg, &emc->nfcsr);
240 writel(EMC_SMCR1_OPT_NAND, &emc->smcr[1]);
242 nand->IO_ADDR_R = JZ_NAND_DATA_ADDR;
243 nand->IO_ADDR_W = JZ_NAND_DATA_ADDR;
244 nand->cmd_ctrl = jz_nand_cmd_ctrl;
245 nand->dev_ready = jz_nand_device_ready;
246 nand->ecc.hwctl = jz_nand_hwctl;
247 nand->ecc.correct = jz_nand_rs_correct_data;
248 nand->ecc.calculate = jz_nand_rs_calculate_ecc;
249 nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
250 nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
251 nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
252 nand->ecc.strength = 4;
253 nand->ecc.layout = &qi_lb60_ecclayout_2gb;
254 nand->chip_delay = 50;
255 nand->bbt_options |= NAND_BBT_USE_FLASH;