3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/soc.h>
12 #include <asm/arch/mpp.h>
15 /* NAND Flash Soc registers */
16 struct kwnandf_registers {
17 u32 rd_params; /* 0x10418 */
18 u32 wr_param; /* 0x1041c */
19 u8 pad[0x10470 - 0x1041c - 4];
20 u32 ctrl; /* 0x10470 */
23 static struct kwnandf_registers *nf_reg =
24 (struct kwnandf_registers *)KW_NANDF_BASE;
26 static u32 nand_mpp_backup[9] = { 0 };
29 * hardware specific access to control-lines/bits
31 #define NAND_ACTCEBOOT_BIT 0x02
33 static void kw_nand_hwcontrol(struct mtd_info *mtd, int cmd,
36 struct nand_chip *nc = mtd_to_nand(mtd);
39 if (cmd == NAND_CMD_NONE)
43 offs = (1 << 0); /* Commands with A[1:0] == 01 */
44 else if (ctrl & NAND_ALE)
45 offs = (1 << 1); /* Addresses with A[1:0] == 10 */
49 writeb(cmd, nc->IO_ADDR_W + offs);
52 void kw_nand_select_chip(struct mtd_info *mtd, int chip)
55 static const u32 nand_config[] = {
68 kirkwood_mpp_conf(nand_config, nand_mpp_backup);
70 kirkwood_mpp_conf(nand_mpp_backup, NULL);
72 data = readl(&nf_reg->ctrl);
73 data |= NAND_ACTCEBOOT_BIT;
74 writel(data, &nf_reg->ctrl);
77 int board_nand_init(struct nand_chip *nand)
79 nand->options = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING;
80 #if defined(CONFIG_SYS_NAND_NO_SUBPAGE_WRITE)
81 nand->options |= NAND_NO_SUBPAGE_WRITE;
83 #if defined(CONFIG_NAND_ECC_BCH)
84 nand->ecc.mode = NAND_ECC_SOFT_BCH;
86 nand->ecc.mode = NAND_ECC_SOFT;
88 nand->cmd_ctrl = kw_nand_hwcontrol;
89 nand->chip_delay = 40;
90 nand->select_chip = kw_nand_select_chip;