git.sur5r.net Git - u-boot/blob - drivers/mtd/nand/kirkwood_nand.c

   1 /*
   2  * (C) Copyright 2009
   3  * Marvell Semiconductor <www.marvell.com>
   4  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/soc.h>
  12 #include <asm/arch/mpp.h>
  13 #include <nand.h>
  14
  15 /* NAND Flash Soc registers */
  16 struct kwnandf_registers {
  17         u32 rd_params;  /* 0x10418 */
  18         u32 wr_param;   /* 0x1041c */
  19         u8  pad[0x10470 - 0x1041c - 4];
  20         u32 ctrl;       /* 0x10470 */
  21 };
  22
  23 static struct kwnandf_registers *nf_reg =
  24         (struct kwnandf_registers *)KW_NANDF_BASE;
  25
  26 static u32 nand_mpp_backup[9] = { 0 };
  27
  28 /*
  29  * hardware specific access to control-lines/bits
  30  */
  31 #define NAND_ACTCEBOOT_BIT              0x02
  32
  33 static void kw_nand_hwcontrol(struct mtd_info *mtd, int cmd,
  34                               unsigned int ctrl)
  35 {
  36         struct nand_chip *nc = mtd_to_nand(mtd);
  37         u32 offs;
  38
  39         if (cmd == NAND_CMD_NONE)
  40                 return;
  41
  42         if (ctrl & NAND_CLE)
  43                 offs = (1 << 0);        /* Commands with A[1:0] == 01 */
  44         else if (ctrl & NAND_ALE)
  45                 offs = (1 << 1);        /* Addresses with A[1:0] == 10 */
  46         else
  47                 return;
  48
  49         writeb(cmd, nc->IO_ADDR_W + offs);
  50 }
  51
  52 void kw_nand_select_chip(struct mtd_info *mtd, int chip)
  53 {
  54         u32 data;
  55         static const u32 nand_config[] = {
  56                 MPP0_NF_IO2,
  57                 MPP1_NF_IO3,
  58                 MPP2_NF_IO4,
  59                 MPP3_NF_IO5,
  60                 MPP4_NF_IO6,
  61                 MPP5_NF_IO7,
  62                 MPP18_NF_IO0,
  63                 MPP19_NF_IO1,
  64                 0
  65         };
  66
  67         if (chip >= 0)
  68                 kirkwood_mpp_conf(nand_config, nand_mpp_backup);
  69         else
  70                 kirkwood_mpp_conf(nand_mpp_backup, NULL);
  71
  72         data = readl(&nf_reg->ctrl);
  73         data |= NAND_ACTCEBOOT_BIT;
  74         writel(data, &nf_reg->ctrl);
  75 }
  76
  77 int board_nand_init(struct nand_chip *nand)
  78 {
  79         nand->options = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING;
  80 #if defined(CONFIG_SYS_NAND_NO_SUBPAGE_WRITE)
  81         nand->options |= NAND_NO_SUBPAGE_WRITE;
  82 #endif
  83 #if defined(CONFIG_NAND_ECC_BCH)
  84         nand->ecc.mode = NAND_ECC_SOFT_BCH;
  85 #else
  86         nand->ecc.mode = NAND_ECC_SOFT;
  87 #endif
  88         nand->cmd_ctrl = kw_nand_hwcontrol;
  89         nand->chip_delay = 40;
  90         nand->select_chip = kw_nand_select_chip;
  91         return 0;
  92 }