1 // SPDX-License-Identifier: GPL-2.0+
3 * LPC32xx SLC NAND flash controller driver
5 * (C) Copyright 2015 Vladimir Zapolskiy <vz@mleia.com>
7 * Hardware ECC support original source code
8 * Copyright (C) 2008 by NXP Semiconductors
11 * Copyright (c) 2015 Tyco Fire Protection Products.
16 #include <linux/mtd/nand_ecc.h>
17 #include <linux/errno.h>
19 #include <asm/arch/config.h>
20 #include <asm/arch/clk.h>
21 #include <asm/arch/sys_proto.h>
22 #include <asm/arch/dma.h>
23 #include <asm/arch/cpu.h>
25 #if defined(CONFIG_DMA_LPC32XX) && defined(CONFIG_SPL_BUILD)
26 #warning "DMA support in SPL image is not tested"
29 struct lpc32xx_nand_slc_regs {
48 #define CFG_CE_LOW (1 << 5)
49 #define CFG_DMA_ECC (1 << 4) /* Enable DMA ECC bit */
50 #define CFG_ECC_EN (1 << 3) /* ECC enable bit */
51 #define CFG_DMA_BURST (1 << 2) /* DMA burst bit */
52 #define CFG_DMA_DIR (1 << 1) /* DMA write(0)/read(1) bit */
55 #define CTRL_SW_RESET (1 << 2)
56 #define CTRL_ECC_CLEAR (1 << 1) /* Reset ECC bit */
57 #define CTRL_DMA_START (1 << 0) /* Start DMA channel bit */
60 #define STAT_DMA_FIFO (1 << 2) /* DMA FIFO has data bit */
61 #define STAT_NAND_READY (1 << 0)
63 /* INT_STAT register */
64 #define INT_STAT_TC (1 << 1)
65 #define INT_STAT_RDY (1 << 0)
67 /* TAC register bits, be aware of overflows */
68 #define TAC_W_RDY(n) (max_t(uint32_t, (n), 0xF) << 28)
69 #define TAC_W_WIDTH(n) (max_t(uint32_t, (n), 0xF) << 24)
70 #define TAC_W_HOLD(n) (max_t(uint32_t, (n), 0xF) << 20)
71 #define TAC_W_SETUP(n) (max_t(uint32_t, (n), 0xF) << 16)
72 #define TAC_R_RDY(n) (max_t(uint32_t, (n), 0xF) << 12)
73 #define TAC_R_WIDTH(n) (max_t(uint32_t, (n), 0xF) << 8)
74 #define TAC_R_HOLD(n) (max_t(uint32_t, (n), 0xF) << 4)
75 #define TAC_R_SETUP(n) (max_t(uint32_t, (n), 0xF) << 0)
77 /* NAND ECC Layout for small page NAND devices
78 * Note: For large page devices, the default layouts are used. */
79 static struct nand_ecclayout lpc32xx_nand_oob_16 = {
81 .eccpos = {10, 11, 12, 13, 14, 15},
90 #if defined(CONFIG_DMA_LPC32XX)
91 #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
95 * For Large Block: 17 descriptors = ((16 Data and ECC Read) + 1 Spare Area)
96 * For Small Block: 5 descriptors = ((4 Data and ECC Read) + 1 Spare Area)
98 static struct lpc32xx_dmac_ll dmalist[ECCSTEPS * 2 + 1];
99 static u32 ecc_buffer[8]; /* MAX ECC size */
100 static unsigned int dmachan = (unsigned int)-1; /* Invalid channel */
103 * Helper macro for the DMA client (i.e. NAND SLC):
104 * - to write the next DMA linked list item address
105 * (see arch/include/asm/arch-lpc32xx/dma.h).
106 * - to assign the DMA data register to DMA source or destination address.
107 * - to assign the ECC register to DMA source or destination address.
109 #define lpc32xx_dmac_next_lli(x) ((u32)x)
110 #define lpc32xx_dmac_set_dma_data() ((u32)&lpc32xx_nand_slc_regs->dma_data)
111 #define lpc32xx_dmac_set_ecc() ((u32)&lpc32xx_nand_slc_regs->ecc)
114 static struct lpc32xx_nand_slc_regs __iomem *lpc32xx_nand_slc_regs
115 = (struct lpc32xx_nand_slc_regs __iomem *)SLC_NAND_BASE;
117 static void lpc32xx_nand_init(void)
119 uint32_t hclk = get_hclk_clk_rate();
121 /* Reset SLC NAND controller */
122 writel(CTRL_SW_RESET, &lpc32xx_nand_slc_regs->ctrl);
124 /* 8-bit bus, no DMA, no ECC, ordinary CE signal */
125 writel(0, &lpc32xx_nand_slc_regs->cfg);
127 /* Interrupts disabled and cleared */
128 writel(0, &lpc32xx_nand_slc_regs->ien);
129 writel(INT_STAT_TC | INT_STAT_RDY,
130 &lpc32xx_nand_slc_regs->icr);
132 /* Configure NAND flash timings */
133 writel(TAC_W_RDY(CONFIG_LPC32XX_NAND_SLC_WDR_CLKS) |
134 TAC_W_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_WWIDTH) |
135 TAC_W_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_WHOLD) |
136 TAC_W_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_WSETUP) |
137 TAC_R_RDY(CONFIG_LPC32XX_NAND_SLC_RDR_CLKS) |
138 TAC_R_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_RWIDTH) |
139 TAC_R_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_RHOLD) |
140 TAC_R_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_RSETUP),
141 &lpc32xx_nand_slc_regs->tac);
144 static void lpc32xx_nand_cmd_ctrl(struct mtd_info *mtd,
145 int cmd, unsigned int ctrl)
147 debug("ctrl: 0x%08x, cmd: 0x%08x\n", ctrl, cmd);
150 setbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_CE_LOW);
152 clrbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_CE_LOW);
154 if (cmd == NAND_CMD_NONE)
158 writel(cmd & 0xFF, &lpc32xx_nand_slc_regs->cmd);
159 else if (ctrl & NAND_ALE)
160 writel(cmd & 0xFF, &lpc32xx_nand_slc_regs->addr);
163 static int lpc32xx_nand_dev_ready(struct mtd_info *mtd)
165 return readl(&lpc32xx_nand_slc_regs->stat) & STAT_NAND_READY;
168 #if defined(CONFIG_DMA_LPC32XX)
170 * Prepares DMA descriptors for NAND RD/WR operations
171 * If the size is < 256 Bytes then it is assumed to be
174 static void lpc32xx_nand_dma_configure(struct nand_chip *chip,
175 const u8 *buffer, int size,
178 u32 i, dmasrc, ctrl, ecc_ctrl, oob_ctrl, dmadst;
179 struct lpc32xx_dmac_ll *dmalist_cur;
180 struct lpc32xx_dmac_ll *dmalist_cur_ecc;
183 * CTRL descriptor entry for reading ECC
184 * Copy Multiple times to sync DMA with Flash Controller
187 DMAC_CHAN_SRC_BURST_1 |
188 DMAC_CHAN_DEST_BURST_1 |
189 DMAC_CHAN_SRC_WIDTH_32 |
190 DMAC_CHAN_DEST_WIDTH_32 |
193 /* CTRL descriptor entry for reading/writing Data */
194 ctrl = (CONFIG_SYS_NAND_ECCSIZE / 4) |
195 DMAC_CHAN_SRC_BURST_4 |
196 DMAC_CHAN_DEST_BURST_4 |
197 DMAC_CHAN_SRC_WIDTH_32 |
198 DMAC_CHAN_DEST_WIDTH_32 |
201 /* CTRL descriptor entry for reading/writing Spare Area */
202 oob_ctrl = (CONFIG_SYS_NAND_OOBSIZE / 4) |
203 DMAC_CHAN_SRC_BURST_4 |
204 DMAC_CHAN_DEST_BURST_4 |
205 DMAC_CHAN_SRC_WIDTH_32 |
206 DMAC_CHAN_DEST_WIDTH_32 |
210 dmasrc = lpc32xx_dmac_set_dma_data();
211 dmadst = (u32)buffer;
212 ctrl |= DMAC_CHAN_DEST_AUTOINC;
214 dmadst = lpc32xx_dmac_set_dma_data();
215 dmasrc = (u32)buffer;
216 ctrl |= DMAC_CHAN_SRC_AUTOINC;
220 * Write Operation Sequence for Small Block NAND
221 * ----------------------------------------------------------
222 * 1. X'fer 256 bytes of data from Memory to Flash.
223 * 2. Copy generated ECC data from Register to Spare Area
224 * 3. X'fer next 256 bytes of data from Memory to Flash.
225 * 4. Copy generated ECC data from Register to Spare Area.
226 * 5. X'fer 16 byets of Spare area from Memory to Flash.
227 * Read Operation Sequence for Small Block NAND
228 * ----------------------------------------------------------
229 * 1. X'fer 256 bytes of data from Flash to Memory.
230 * 2. Copy generated ECC data from Register to ECC calc Buffer.
231 * 3. X'fer next 256 bytes of data from Flash to Memory.
232 * 4. Copy generated ECC data from Register to ECC calc Buffer.
233 * 5. X'fer 16 bytes of Spare area from Flash to Memory.
234 * Write Operation Sequence for Large Block NAND
235 * ----------------------------------------------------------
236 * 1. Steps(1-4) of Write Operations repeate for four times
237 * which generates 16 DMA descriptors to X'fer 2048 bytes of
238 * data & 32 bytes of ECC data.
239 * 2. X'fer 64 bytes of Spare area from Memory to Flash.
240 * Read Operation Sequence for Large Block NAND
241 * ----------------------------------------------------------
242 * 1. Steps(1-4) of Read Operations repeate for four times
243 * which generates 16 DMA descriptors to X'fer 2048 bytes of
244 * data & 32 bytes of ECC data.
245 * 2. X'fer 64 bytes of Spare area from Flash to Memory.
248 for (i = 0; i < size/CONFIG_SYS_NAND_ECCSIZE; i++) {
249 dmalist_cur = &dmalist[i * 2];
250 dmalist_cur_ecc = &dmalist[(i * 2) + 1];
252 dmalist_cur->dma_src = (read ? (dmasrc) : (dmasrc + (i*256)));
253 dmalist_cur->dma_dest = (read ? (dmadst + (i*256)) : dmadst);
254 dmalist_cur->next_lli = lpc32xx_dmac_next_lli(dmalist_cur_ecc);
255 dmalist_cur->next_ctrl = ctrl;
257 dmalist_cur_ecc->dma_src = lpc32xx_dmac_set_ecc();
258 dmalist_cur_ecc->dma_dest = (u32)&ecc_buffer[i];
259 dmalist_cur_ecc->next_lli =
260 lpc32xx_dmac_next_lli(&dmalist[(i * 2) + 2]);
261 dmalist_cur_ecc->next_ctrl = ecc_ctrl;
264 if (i) { /* Data only transfer */
265 dmalist_cur_ecc = &dmalist[(i * 2) - 1];
266 dmalist_cur_ecc->next_lli = 0;
267 dmalist_cur_ecc->next_ctrl |= DMAC_CHAN_INT_TC_EN;
271 /* OOB only transfer */
273 dmasrc = lpc32xx_dmac_set_dma_data();
274 dmadst = (u32)buffer;
275 oob_ctrl |= DMAC_CHAN_DEST_AUTOINC;
277 dmadst = lpc32xx_dmac_set_dma_data();
278 dmasrc = (u32)buffer;
279 oob_ctrl |= DMAC_CHAN_SRC_AUTOINC;
282 /* Read/ Write Spare Area Data To/From Flash */
283 dmalist_cur = &dmalist[i * 2];
284 dmalist_cur->dma_src = dmasrc;
285 dmalist_cur->dma_dest = dmadst;
286 dmalist_cur->next_lli = 0;
287 dmalist_cur->next_ctrl = (oob_ctrl | DMAC_CHAN_INT_TC_EN);
290 static void lpc32xx_nand_xfer(struct mtd_info *mtd, const u8 *buf,
293 struct nand_chip *chip = mtd_to_nand(mtd);
297 /* DMA Channel Configuration */
298 config = (read ? DMAC_CHAN_FLOW_D_P2M : DMAC_CHAN_FLOW_D_M2P) |
299 (read ? DMAC_DEST_PERIP(0) : DMAC_DEST_PERIP(DMA_PERID_NAND1)) |
300 (read ? DMAC_SRC_PERIP(DMA_PERID_NAND1) : DMAC_SRC_PERIP(0)) |
303 /* Prepare DMA descriptors */
304 lpc32xx_nand_dma_configure(chip, buf, len, read);
306 /* Setup SLC controller and start transfer */
308 setbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_DMA_DIR);
309 else /* NAND_ECC_WRITE */
310 clrbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_DMA_DIR);
311 setbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_DMA_BURST);
313 /* Write length for new transfers */
314 if (!((readl(&lpc32xx_nand_slc_regs->stat) & STAT_DMA_FIFO) |
315 readl(&lpc32xx_nand_slc_regs->tc))) {
316 int tmp = (len != mtd->oobsize) ? mtd->oobsize : 0;
317 writel(len + tmp, &lpc32xx_nand_slc_regs->tc);
320 setbits_le32(&lpc32xx_nand_slc_regs->ctrl, CTRL_DMA_START);
322 /* Start DMA transfers */
323 ret = lpc32xx_dma_start_xfer(dmachan, dmalist, config);
324 if (unlikely(ret < 0))
328 /* Wait for NAND to be ready */
329 while (!lpc32xx_nand_dev_ready(mtd))
332 /* Wait till DMA transfer is DONE */
333 if (lpc32xx_dma_wait_status(dmachan))
334 pr_err("NAND DMA transfer error!\r\n");
336 /* Stop DMA & HW ECC */
337 clrbits_le32(&lpc32xx_nand_slc_regs->ctrl, CTRL_DMA_START);
338 clrbits_le32(&lpc32xx_nand_slc_regs->cfg,
339 CFG_DMA_DIR | CFG_DMA_BURST | CFG_ECC_EN | CFG_DMA_ECC);
342 static u32 slc_ecc_copy_to_buffer(u8 *spare, const u32 *ecc, int count)
345 for (i = 0; i < (count * CONFIG_SYS_NAND_ECCBYTES);
346 i += CONFIG_SYS_NAND_ECCBYTES) {
347 u32 ce = ecc[i / CONFIG_SYS_NAND_ECCBYTES];
348 ce = ~(ce << 2) & 0xFFFFFF;
349 spare[i+2] = (u8)(ce & 0xFF); ce >>= 8;
350 spare[i+1] = (u8)(ce & 0xFF); ce >>= 8;
351 spare[i] = (u8)(ce & 0xFF);
356 static int lpc32xx_ecc_calculate(struct mtd_info *mtd, const uint8_t *dat,
359 return slc_ecc_copy_to_buffer(ecc_code, ecc_buffer, ECCSTEPS);
363 * Enables and prepares SLC NAND controller
364 * for doing data transfers with H/W ECC enabled.
366 static void lpc32xx_hwecc_enable(struct mtd_info *mtd, int mode)
369 writel(CTRL_ECC_CLEAR, &lpc32xx_nand_slc_regs->ctrl);
371 /* Setup SLC controller for H/W ECC operations */
372 setbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_ECC_EN | CFG_DMA_ECC);
376 * lpc32xx_correct_data - [NAND Interface] Detect and correct bit error(s)
377 * mtd: MTD block structure
378 * dat: raw data read from the chip
379 * read_ecc: ECC from the chip
380 * calc_ecc: the ECC calculated from raw data
382 * Detect and correct a 1 bit error for 256 byte block
384 int lpc32xx_correct_data(struct mtd_info *mtd, u_char *dat,
385 u_char *read_ecc, u_char *calc_ecc)
389 u_char *r = read_ecc;
390 u_char *c = calc_ecc;
393 for (i = 0 ; i < ECCSTEPS ; i++) {
394 r += CONFIG_SYS_NAND_ECCBYTES;
395 c += CONFIG_SYS_NAND_ECCBYTES;
396 data_offset += CONFIG_SYS_NAND_ECCSIZE;
398 ret1 = nand_correct_data(mtd, dat + data_offset, r, c);
409 #if defined(CONFIG_DMA_LPC32XX)
410 static void lpc32xx_dma_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
412 lpc32xx_nand_xfer(mtd, buf, len, 1);
415 static void lpc32xx_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
418 *buf++ = readl(&lpc32xx_nand_slc_regs->data);
422 static uint8_t lpc32xx_read_byte(struct mtd_info *mtd)
424 return readl(&lpc32xx_nand_slc_regs->data);
427 #if defined(CONFIG_DMA_LPC32XX)
428 static void lpc32xx_dma_write_buf(struct mtd_info *mtd, const uint8_t *buf,
431 lpc32xx_nand_xfer(mtd, buf, len, 0);
434 static void lpc32xx_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
437 writel(*buf++, &lpc32xx_nand_slc_regs->data);
441 static void lpc32xx_write_byte(struct mtd_info *mtd, uint8_t byte)
443 writel(byte, &lpc32xx_nand_slc_regs->data);
446 #if defined(CONFIG_DMA_LPC32XX)
447 /* Reuse the logic from "nand_read_page_hwecc()" */
448 static int lpc32xx_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
449 uint8_t *buf, int oob_required, int page)
454 uint8_t *ecc_calc = chip->buffers->ecccalc;
455 uint8_t *ecc_code = chip->buffers->ecccode;
456 uint32_t *eccpos = chip->ecc.layout->eccpos;
457 unsigned int max_bitflips = 0;
460 * As per the "LPC32x0 and LPC32x0/01 User manual" table 173 notes
461 * and section 9.7, the NAND SLC & DMA allowed single DMA transaction
462 * of a page size using DMA controller scatter/gather mode through
463 * linked list; the ECC read is done without any software intervention.
466 lpc32xx_hwecc_enable(mtd, NAND_ECC_READ);
467 lpc32xx_dma_read_buf(mtd, p, chip->ecc.size * chip->ecc.steps);
468 lpc32xx_ecc_calculate(mtd, p, &ecc_calc[0]);
469 lpc32xx_dma_read_buf(mtd, chip->oob_poi, mtd->oobsize);
471 for (i = 0; i < chip->ecc.total; i++)
472 ecc_code[i] = chip->oob_poi[eccpos[i]];
474 stat = chip->ecc.correct(mtd, p, &ecc_code[0], &ecc_calc[0]);
476 mtd->ecc_stats.failed++;
478 mtd->ecc_stats.corrected += stat;
479 max_bitflips = max_t(unsigned int, max_bitflips, stat);
485 /* Reuse the logic from "nand_write_page_hwecc()" */
486 static int lpc32xx_write_page_hwecc(struct mtd_info *mtd,
487 struct nand_chip *chip,
488 const uint8_t *buf, int oob_required,
492 uint8_t *ecc_calc = chip->buffers->ecccalc;
493 const uint8_t *p = buf;
494 uint32_t *eccpos = chip->ecc.layout->eccpos;
497 * As per the "LPC32x0 and LPC32x0/01 User manual" table 173 notes
498 * and section 9.7, the NAND SLC & DMA allowed single DMA transaction
499 * of a page size using DMA controller scatter/gather mode through
500 * linked list; the ECC read is done without any software intervention.
503 lpc32xx_hwecc_enable(mtd, NAND_ECC_WRITE);
504 lpc32xx_dma_write_buf(mtd, p, chip->ecc.size * chip->ecc.steps);
505 lpc32xx_ecc_calculate(mtd, p, &ecc_calc[0]);
507 for (i = 0; i < chip->ecc.total; i++)
508 chip->oob_poi[eccpos[i]] = ecc_calc[i];
510 lpc32xx_dma_write_buf(mtd, chip->oob_poi, mtd->oobsize);
517 * LPC32xx has only one SLC NAND controller, don't utilize
518 * CONFIG_SYS_NAND_SELF_INIT to be able to reuse this function
519 * both in SPL NAND and U-Boot images.
521 int board_nand_init(struct nand_chip *lpc32xx_chip)
523 #if defined(CONFIG_DMA_LPC32XX)
526 /* Acquire a channel for our use */
527 ret = lpc32xx_dma_get_channel();
528 if (unlikely(ret < 0)) {
529 pr_info("Unable to get free DMA channel for NAND transfers\n");
532 dmachan = (unsigned int)ret;
535 lpc32xx_chip->cmd_ctrl = lpc32xx_nand_cmd_ctrl;
536 lpc32xx_chip->dev_ready = lpc32xx_nand_dev_ready;
539 * The implementation of these functions is quite common, but
540 * they MUST be defined, because access to data register
541 * is strictly 32-bit aligned.
543 lpc32xx_chip->read_byte = lpc32xx_read_byte;
544 lpc32xx_chip->write_byte = lpc32xx_write_byte;
546 #if defined(CONFIG_DMA_LPC32XX)
547 /* Hardware ECC calculation is supported when DMA driver is selected */
548 lpc32xx_chip->ecc.mode = NAND_ECC_HW;
550 lpc32xx_chip->read_buf = lpc32xx_dma_read_buf;
551 lpc32xx_chip->write_buf = lpc32xx_dma_write_buf;
553 lpc32xx_chip->ecc.calculate = lpc32xx_ecc_calculate;
554 lpc32xx_chip->ecc.correct = lpc32xx_correct_data;
555 lpc32xx_chip->ecc.hwctl = lpc32xx_hwecc_enable;
556 lpc32xx_chip->chip_delay = 2000;
558 lpc32xx_chip->ecc.read_page = lpc32xx_read_page_hwecc;
559 lpc32xx_chip->ecc.write_page = lpc32xx_write_page_hwecc;
560 lpc32xx_chip->options |= NAND_NO_SUBPAGE_WRITE;
563 * Hardware ECC calculation is not supported by the driver,
564 * because it requires DMA support, see LPC32x0 User Manual,
565 * note after SLC_ECC register description (UM10326, p.198)
567 lpc32xx_chip->ecc.mode = NAND_ECC_SOFT;
570 * The implementation of these functions is quite common, but
571 * they MUST be defined, because access to data register
572 * is strictly 32-bit aligned.
574 lpc32xx_chip->read_buf = lpc32xx_read_buf;
575 lpc32xx_chip->write_buf = lpc32xx_write_buf;
579 * These values are predefined
580 * for both small and large page NAND flash devices.
582 lpc32xx_chip->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
583 lpc32xx_chip->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
584 lpc32xx_chip->ecc.strength = 1;
586 if (CONFIG_SYS_NAND_PAGE_SIZE != NAND_LARGE_BLOCK_PAGE_SIZE)
587 lpc32xx_chip->ecc.layout = &lpc32xx_nand_oob_16;
589 #if defined(CONFIG_SYS_NAND_USE_FLASH_BBT)
590 lpc32xx_chip->bbt_options |= NAND_BBT_USE_FLASH;
593 /* Initialize NAND interface */