2 * LPC32xx SLC NAND flash controller driver
4 * (C) Copyright 2015 Vladimir Zapolskiy <vz@mleia.com>
6 * Hardware ECC support original source code
7 * Copyright (C) 2008 by NXP Semiconductors
10 * Copyright (c) 2015 Tyco Fire Protection Products.
12 * SPDX-License-Identifier: GPL-2.0+
17 #include <linux/mtd/nand_ecc.h>
18 #include <asm/errno.h>
20 #include <asm/arch/config.h>
21 #include <asm/arch/clk.h>
22 #include <asm/arch/sys_proto.h>
23 #include <asm/arch/dma.h>
24 #include <asm/arch/cpu.h>
26 #if defined(CONFIG_DMA_LPC32XX) && defined(CONFIG_SPL_BUILD)
27 #warning "DMA support in SPL image is not tested"
30 struct lpc32xx_nand_slc_regs {
49 #define CFG_CE_LOW (1 << 5)
50 #define CFG_DMA_ECC (1 << 4) /* Enable DMA ECC bit */
51 #define CFG_ECC_EN (1 << 3) /* ECC enable bit */
52 #define CFG_DMA_BURST (1 << 2) /* DMA burst bit */
53 #define CFG_DMA_DIR (1 << 1) /* DMA write(0)/read(1) bit */
56 #define CTRL_SW_RESET (1 << 2)
57 #define CTRL_ECC_CLEAR (1 << 1) /* Reset ECC bit */
58 #define CTRL_DMA_START (1 << 0) /* Start DMA channel bit */
61 #define STAT_DMA_FIFO (1 << 2) /* DMA FIFO has data bit */
62 #define STAT_NAND_READY (1 << 0)
64 /* INT_STAT register */
65 #define INT_STAT_TC (1 << 1)
66 #define INT_STAT_RDY (1 << 0)
68 /* TAC register bits, be aware of overflows */
69 #define TAC_W_RDY(n) (max_t(uint32_t, (n), 0xF) << 28)
70 #define TAC_W_WIDTH(n) (max_t(uint32_t, (n), 0xF) << 24)
71 #define TAC_W_HOLD(n) (max_t(uint32_t, (n), 0xF) << 20)
72 #define TAC_W_SETUP(n) (max_t(uint32_t, (n), 0xF) << 16)
73 #define TAC_R_RDY(n) (max_t(uint32_t, (n), 0xF) << 12)
74 #define TAC_R_WIDTH(n) (max_t(uint32_t, (n), 0xF) << 8)
75 #define TAC_R_HOLD(n) (max_t(uint32_t, (n), 0xF) << 4)
76 #define TAC_R_SETUP(n) (max_t(uint32_t, (n), 0xF) << 0)
78 #if defined(CONFIG_DMA_LPC32XX)
79 #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
83 * For Large Block: 17 descriptors = ((16 Data and ECC Read) + 1 Spare Area)
84 * For Small Block: 5 descriptors = ((4 Data and ECC Read) + 1 Spare Area)
86 static struct lpc32xx_dmac_ll dmalist[ECCSTEPS * 2 + 1];
87 static u32 ecc_buffer[8]; /* MAX ECC size */
88 static unsigned int dmachan = (unsigned int)-1; /* Invalid channel */
91 * Helper macro for the DMA client (i.e. NAND SLC):
92 * - to write the next DMA linked list item address
93 * (see arch/include/asm/arch-lpc32xx/dma.h).
94 * - to assign the DMA data register to DMA source or destination address.
95 * - to assign the ECC register to DMA source or destination address.
97 #define lpc32xx_dmac_next_lli(x) ((u32)x)
98 #define lpc32xx_dmac_set_dma_data() ((u32)&lpc32xx_nand_slc_regs->dma_data)
99 #define lpc32xx_dmac_set_ecc() ((u32)&lpc32xx_nand_slc_regs->ecc)
102 static struct lpc32xx_nand_slc_regs __iomem *lpc32xx_nand_slc_regs
103 = (struct lpc32xx_nand_slc_regs __iomem *)SLC_NAND_BASE;
105 static void lpc32xx_nand_init(void)
107 uint32_t hclk = get_hclk_clk_rate();
109 /* Reset SLC NAND controller */
110 writel(CTRL_SW_RESET, &lpc32xx_nand_slc_regs->ctrl);
112 /* 8-bit bus, no DMA, no ECC, ordinary CE signal */
113 writel(0, &lpc32xx_nand_slc_regs->cfg);
115 /* Interrupts disabled and cleared */
116 writel(0, &lpc32xx_nand_slc_regs->ien);
117 writel(INT_STAT_TC | INT_STAT_RDY,
118 &lpc32xx_nand_slc_regs->icr);
120 /* Configure NAND flash timings */
121 writel(TAC_W_RDY(CONFIG_LPC32XX_NAND_SLC_WDR_CLKS) |
122 TAC_W_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_WWIDTH) |
123 TAC_W_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_WHOLD) |
124 TAC_W_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_WSETUP) |
125 TAC_R_RDY(CONFIG_LPC32XX_NAND_SLC_RDR_CLKS) |
126 TAC_R_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_RWIDTH) |
127 TAC_R_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_RHOLD) |
128 TAC_R_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_RSETUP),
129 &lpc32xx_nand_slc_regs->tac);
132 static void lpc32xx_nand_cmd_ctrl(struct mtd_info *mtd,
133 int cmd, unsigned int ctrl)
135 debug("ctrl: 0x%08x, cmd: 0x%08x\n", ctrl, cmd);
138 setbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_CE_LOW);
140 clrbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_CE_LOW);
142 if (cmd == NAND_CMD_NONE)
146 writel(cmd & 0xFF, &lpc32xx_nand_slc_regs->cmd);
147 else if (ctrl & NAND_ALE)
148 writel(cmd & 0xFF, &lpc32xx_nand_slc_regs->addr);
151 static int lpc32xx_nand_dev_ready(struct mtd_info *mtd)
153 return readl(&lpc32xx_nand_slc_regs->stat) & STAT_NAND_READY;
156 #if defined(CONFIG_DMA_LPC32XX)
158 * Prepares DMA descriptors for NAND RD/WR operations
159 * If the size is < 256 Bytes then it is assumed to be
162 static void lpc32xx_nand_dma_configure(struct nand_chip *chip,
163 const u8 *buffer, int size,
166 u32 i, dmasrc, ctrl, ecc_ctrl, oob_ctrl, dmadst;
167 struct lpc32xx_dmac_ll *dmalist_cur;
168 struct lpc32xx_dmac_ll *dmalist_cur_ecc;
171 * CTRL descriptor entry for reading ECC
172 * Copy Multiple times to sync DMA with Flash Controller
175 DMAC_CHAN_SRC_BURST_1 |
176 DMAC_CHAN_DEST_BURST_1 |
177 DMAC_CHAN_SRC_WIDTH_32 |
178 DMAC_CHAN_DEST_WIDTH_32 |
181 /* CTRL descriptor entry for reading/writing Data */
182 ctrl = (CONFIG_SYS_NAND_ECCSIZE / 4) |
183 DMAC_CHAN_SRC_BURST_4 |
184 DMAC_CHAN_DEST_BURST_4 |
185 DMAC_CHAN_SRC_WIDTH_32 |
186 DMAC_CHAN_DEST_WIDTH_32 |
189 /* CTRL descriptor entry for reading/writing Spare Area */
190 oob_ctrl = (CONFIG_SYS_NAND_OOBSIZE / 4) |
191 DMAC_CHAN_SRC_BURST_4 |
192 DMAC_CHAN_DEST_BURST_4 |
193 DMAC_CHAN_SRC_WIDTH_32 |
194 DMAC_CHAN_DEST_WIDTH_32 |
198 dmasrc = lpc32xx_dmac_set_dma_data();
199 dmadst = (u32)buffer;
200 ctrl |= DMAC_CHAN_DEST_AUTOINC;
202 dmadst = lpc32xx_dmac_set_dma_data();
203 dmasrc = (u32)buffer;
204 ctrl |= DMAC_CHAN_SRC_AUTOINC;
208 * Write Operation Sequence for Small Block NAND
209 * ----------------------------------------------------------
210 * 1. X'fer 256 bytes of data from Memory to Flash.
211 * 2. Copy generated ECC data from Register to Spare Area
212 * 3. X'fer next 256 bytes of data from Memory to Flash.
213 * 4. Copy generated ECC data from Register to Spare Area.
214 * 5. X'fer 16 byets of Spare area from Memory to Flash.
215 * Read Operation Sequence for Small Block NAND
216 * ----------------------------------------------------------
217 * 1. X'fer 256 bytes of data from Flash to Memory.
218 * 2. Copy generated ECC data from Register to ECC calc Buffer.
219 * 3. X'fer next 256 bytes of data from Flash to Memory.
220 * 4. Copy generated ECC data from Register to ECC calc Buffer.
221 * 5. X'fer 16 bytes of Spare area from Flash to Memory.
222 * Write Operation Sequence for Large Block NAND
223 * ----------------------------------------------------------
224 * 1. Steps(1-4) of Write Operations repeate for four times
225 * which generates 16 DMA descriptors to X'fer 2048 bytes of
226 * data & 32 bytes of ECC data.
227 * 2. X'fer 64 bytes of Spare area from Memory to Flash.
228 * Read Operation Sequence for Large Block NAND
229 * ----------------------------------------------------------
230 * 1. Steps(1-4) of Read Operations repeate for four times
231 * which generates 16 DMA descriptors to X'fer 2048 bytes of
232 * data & 32 bytes of ECC data.
233 * 2. X'fer 64 bytes of Spare area from Flash to Memory.
236 for (i = 0; i < size/CONFIG_SYS_NAND_ECCSIZE; i++) {
237 dmalist_cur = &dmalist[i * 2];
238 dmalist_cur_ecc = &dmalist[(i * 2) + 1];
240 dmalist_cur->dma_src = (read ? (dmasrc) : (dmasrc + (i*256)));
241 dmalist_cur->dma_dest = (read ? (dmadst + (i*256)) : dmadst);
242 dmalist_cur->next_lli = lpc32xx_dmac_next_lli(dmalist_cur_ecc);
243 dmalist_cur->next_ctrl = ctrl;
245 dmalist_cur_ecc->dma_src = lpc32xx_dmac_set_ecc();
246 dmalist_cur_ecc->dma_dest = (u32)&ecc_buffer[i];
247 dmalist_cur_ecc->next_lli =
248 lpc32xx_dmac_next_lli(&dmalist[(i * 2) + 2]);
249 dmalist_cur_ecc->next_ctrl = ecc_ctrl;
252 if (i) { /* Data only transfer */
253 dmalist_cur_ecc = &dmalist[(i * 2) - 1];
254 dmalist_cur_ecc->next_lli = 0;
255 dmalist_cur_ecc->next_ctrl |= DMAC_CHAN_INT_TC_EN;
259 /* OOB only transfer */
261 dmasrc = lpc32xx_dmac_set_dma_data();
262 dmadst = (u32)buffer;
263 oob_ctrl |= DMAC_CHAN_DEST_AUTOINC;
265 dmadst = lpc32xx_dmac_set_dma_data();
266 dmasrc = (u32)buffer;
267 oob_ctrl |= DMAC_CHAN_SRC_AUTOINC;
270 /* Read/ Write Spare Area Data To/From Flash */
271 dmalist_cur = &dmalist[i * 2];
272 dmalist_cur->dma_src = dmasrc;
273 dmalist_cur->dma_dest = dmadst;
274 dmalist_cur->next_lli = 0;
275 dmalist_cur->next_ctrl = (oob_ctrl | DMAC_CHAN_INT_TC_EN);
278 static void lpc32xx_nand_xfer(struct mtd_info *mtd, const u8 *buf,
281 struct nand_chip *chip = mtd->priv;
285 /* DMA Channel Configuration */
286 config = (read ? DMAC_CHAN_FLOW_D_P2M : DMAC_CHAN_FLOW_D_M2P) |
287 (read ? DMAC_DEST_PERIP(0) : DMAC_DEST_PERIP(DMA_PERID_NAND1)) |
288 (read ? DMAC_SRC_PERIP(DMA_PERID_NAND1) : DMAC_SRC_PERIP(0)) |
291 /* Prepare DMA descriptors */
292 lpc32xx_nand_dma_configure(chip, buf, len, read);
294 /* Setup SLC controller and start transfer */
296 setbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_DMA_DIR);
297 else /* NAND_ECC_WRITE */
298 clrbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_DMA_DIR);
299 setbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_DMA_BURST);
301 /* Write length for new transfers */
302 if (!((readl(&lpc32xx_nand_slc_regs->stat) & STAT_DMA_FIFO) |
303 readl(&lpc32xx_nand_slc_regs->tc))) {
304 int tmp = (len != mtd->oobsize) ? mtd->oobsize : 0;
305 writel(len + tmp, &lpc32xx_nand_slc_regs->tc);
308 setbits_le32(&lpc32xx_nand_slc_regs->ctrl, CTRL_DMA_START);
310 /* Start DMA transfers */
311 ret = lpc32xx_dma_start_xfer(dmachan, dmalist, config);
312 if (unlikely(ret < 0))
316 /* Wait for NAND to be ready */
317 while (!lpc32xx_nand_dev_ready(mtd))
320 /* Wait till DMA transfer is DONE */
321 if (lpc32xx_dma_wait_status(dmachan))
322 pr_err("NAND DMA transfer error!\r\n");
324 /* Stop DMA & HW ECC */
325 clrbits_le32(&lpc32xx_nand_slc_regs->ctrl, CTRL_DMA_START);
326 clrbits_le32(&lpc32xx_nand_slc_regs->cfg,
327 CFG_DMA_DIR | CFG_DMA_BURST | CFG_ECC_EN | CFG_DMA_ECC);
330 static u32 slc_ecc_copy_to_buffer(u8 *spare, const u32 *ecc, int count)
333 for (i = 0; i < (count * CONFIG_SYS_NAND_ECCBYTES);
334 i += CONFIG_SYS_NAND_ECCBYTES) {
335 u32 ce = ecc[i / CONFIG_SYS_NAND_ECCBYTES];
336 ce = ~(ce << 2) & 0xFFFFFF;
337 spare[i+2] = (u8)(ce & 0xFF); ce >>= 8;
338 spare[i+1] = (u8)(ce & 0xFF); ce >>= 8;
339 spare[i] = (u8)(ce & 0xFF);
344 static int lpc32xx_ecc_calculate(struct mtd_info *mtd, const uint8_t *dat,
347 return slc_ecc_copy_to_buffer(ecc_code, ecc_buffer, ECCSTEPS);
351 * Enables and prepares SLC NAND controller
352 * for doing data transfers with H/W ECC enabled.
354 static void lpc32xx_hwecc_enable(struct mtd_info *mtd, int mode)
357 writel(CTRL_ECC_CLEAR, &lpc32xx_nand_slc_regs->ctrl);
359 /* Setup SLC controller for H/W ECC operations */
360 setbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_ECC_EN | CFG_DMA_ECC);
364 * lpc32xx_correct_data - [NAND Interface] Detect and correct bit error(s)
365 * mtd: MTD block structure
366 * dat: raw data read from the chip
367 * read_ecc: ECC from the chip
368 * calc_ecc: the ECC calculated from raw data
370 * Detect and correct a 1 bit error for 256 byte block
372 int lpc32xx_correct_data(struct mtd_info *mtd, u_char *dat,
373 u_char *read_ecc, u_char *calc_ecc)
377 u_char *r = read_ecc;
378 u_char *c = calc_ecc;
381 for (i = 0 ; i < ECCSTEPS ; i++) {
382 r += CONFIG_SYS_NAND_ECCBYTES;
383 c += CONFIG_SYS_NAND_ECCBYTES;
384 data_offset += CONFIG_SYS_NAND_ECCSIZE;
386 ret1 = nand_correct_data(mtd, dat + data_offset, r, c);
397 #if defined(CONFIG_DMA_LPC32XX)
398 static void lpc32xx_dma_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
400 lpc32xx_nand_xfer(mtd, buf, len, 1);
403 static void lpc32xx_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
406 *buf++ = readl(&lpc32xx_nand_slc_regs->data);
410 static uint8_t lpc32xx_read_byte(struct mtd_info *mtd)
412 return readl(&lpc32xx_nand_slc_regs->data);
415 #if defined(CONFIG_DMA_LPC32XX)
416 static void lpc32xx_dma_write_buf(struct mtd_info *mtd, const uint8_t *buf,
419 lpc32xx_nand_xfer(mtd, buf, len, 0);
422 static void lpc32xx_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
425 writel(*buf++, &lpc32xx_nand_slc_regs->data);
429 static void lpc32xx_write_byte(struct mtd_info *mtd, uint8_t byte)
431 writel(byte, &lpc32xx_nand_slc_regs->data);
434 #if defined(CONFIG_DMA_LPC32XX)
435 /* Reuse the logic from "nand_read_page_hwecc()" */
436 static int lpc32xx_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
437 uint8_t *buf, int oob_required, int page)
442 uint8_t *ecc_calc = chip->buffers->ecccalc;
443 uint8_t *ecc_code = chip->buffers->ecccode;
444 uint32_t *eccpos = chip->ecc.layout->eccpos;
445 unsigned int max_bitflips = 0;
448 * As per the "LPC32x0 and LPC32x0/01 User manual" table 173 notes
449 * and section 9.7, the NAND SLC & DMA allowed single DMA transaction
450 * of a page size using DMA controller scatter/gather mode through
451 * linked list; the ECC read is done without any software intervention.
454 lpc32xx_hwecc_enable(mtd, NAND_ECC_READ);
455 lpc32xx_dma_read_buf(mtd, p, chip->ecc.size * chip->ecc.steps);
456 lpc32xx_ecc_calculate(mtd, p, &ecc_calc[0]);
457 lpc32xx_dma_read_buf(mtd, chip->oob_poi, mtd->oobsize);
459 for (i = 0; i < chip->ecc.total; i++)
460 ecc_code[i] = chip->oob_poi[eccpos[i]];
462 stat = chip->ecc.correct(mtd, p, &ecc_code[0], &ecc_calc[0]);
464 mtd->ecc_stats.failed++;
466 mtd->ecc_stats.corrected += stat;
467 max_bitflips = max_t(unsigned int, max_bitflips, stat);
473 /* Reuse the logic from "nand_write_page_hwecc()" */
474 static int lpc32xx_write_page_hwecc(struct mtd_info *mtd,
475 struct nand_chip *chip,
476 const uint8_t *buf, int oob_required)
479 uint8_t *ecc_calc = chip->buffers->ecccalc;
480 const uint8_t *p = buf;
481 uint32_t *eccpos = chip->ecc.layout->eccpos;
484 * As per the "LPC32x0 and LPC32x0/01 User manual" table 173 notes
485 * and section 9.7, the NAND SLC & DMA allowed single DMA transaction
486 * of a page size using DMA controller scatter/gather mode through
487 * linked list; the ECC read is done without any software intervention.
490 lpc32xx_hwecc_enable(mtd, NAND_ECC_WRITE);
491 lpc32xx_dma_write_buf(mtd, p, chip->ecc.size * chip->ecc.steps);
492 lpc32xx_ecc_calculate(mtd, p, &ecc_calc[0]);
494 for (i = 0; i < chip->ecc.total; i++)
495 chip->oob_poi[eccpos[i]] = ecc_calc[i];
497 lpc32xx_dma_write_buf(mtd, chip->oob_poi, mtd->oobsize);
504 * LPC32xx has only one SLC NAND controller, don't utilize
505 * CONFIG_SYS_NAND_SELF_INIT to be able to reuse this function
506 * both in SPL NAND and U-boot images.
508 int board_nand_init(struct nand_chip *lpc32xx_chip)
510 #if defined(CONFIG_DMA_LPC32XX)
513 /* Acquire a channel for our use */
514 ret = lpc32xx_dma_get_channel();
515 if (unlikely(ret < 0)) {
516 pr_info("Unable to get free DMA channel for NAND transfers\n");
519 dmachan = (unsigned int)ret;
522 lpc32xx_chip->cmd_ctrl = lpc32xx_nand_cmd_ctrl;
523 lpc32xx_chip->dev_ready = lpc32xx_nand_dev_ready;
526 * The implementation of these functions is quite common, but
527 * they MUST be defined, because access to data register
528 * is strictly 32-bit aligned.
530 lpc32xx_chip->read_byte = lpc32xx_read_byte;
531 lpc32xx_chip->write_byte = lpc32xx_write_byte;
533 #if defined(CONFIG_DMA_LPC32XX)
534 /* Hardware ECC calculation is supported when DMA driver is selected */
535 lpc32xx_chip->ecc.mode = NAND_ECC_HW;
537 lpc32xx_chip->read_buf = lpc32xx_dma_read_buf;
538 lpc32xx_chip->write_buf = lpc32xx_dma_write_buf;
540 lpc32xx_chip->ecc.calculate = lpc32xx_ecc_calculate;
541 lpc32xx_chip->ecc.correct = lpc32xx_correct_data;
542 lpc32xx_chip->ecc.hwctl = lpc32xx_hwecc_enable;
543 lpc32xx_chip->chip_delay = 2000;
545 lpc32xx_chip->ecc.read_page = lpc32xx_read_page_hwecc;
546 lpc32xx_chip->ecc.write_page = lpc32xx_write_page_hwecc;
547 lpc32xx_chip->options |= NAND_NO_SUBPAGE_WRITE;
550 * Hardware ECC calculation is not supported by the driver,
551 * because it requires DMA support, see LPC32x0 User Manual,
552 * note after SLC_ECC register description (UM10326, p.198)
554 lpc32xx_chip->ecc.mode = NAND_ECC_SOFT;
557 * The implementation of these functions is quite common, but
558 * they MUST be defined, because access to data register
559 * is strictly 32-bit aligned.
561 lpc32xx_chip->read_buf = lpc32xx_read_buf;
562 lpc32xx_chip->write_buf = lpc32xx_write_buf;
566 * Use default ECC layout, but these values are predefined
567 * for both small and large page NAND flash devices.
569 lpc32xx_chip->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
570 lpc32xx_chip->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
571 lpc32xx_chip->ecc.strength = 1;
573 #if defined(CONFIG_SYS_NAND_USE_FLASH_BBT)
574 lpc32xx_chip->bbt_options |= NAND_BBT_USE_FLASH;
577 /* Initialize NAND interface */