2 * Copyright 2004-2007 Freescale Semiconductor, Inc.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 * Copyright 2009 Ilya Yanok, <yanok@emcraft.com>
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/err.h>
13 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) || \
14 defined(CONFIG_MX51) || defined(CONFIG_MX53)
15 #include <asm/arch/imx-regs.h>
19 #define DRIVER_NAME "mxc_nand"
21 struct mxc_nand_host {
23 struct nand_chip *nand;
25 struct mxc_nand_regs __iomem *regs;
27 struct mxc_nand_ip_regs __iomem *ip_regs;
34 unsigned int page_addr;
37 static struct mxc_nand_host mxc_host;
38 static struct mxc_nand_host *host = &mxc_host;
40 /* Define delays in microsec for NAND device operations */
41 #define TROP_US_DELAY 2000
42 /* Macros to get byte and bit positions of ECC */
43 #define COLPOS(x) ((x) >> 3)
44 #define BITPOS(x) ((x) & 0xf)
46 /* Define single bit Error positions in Main & Spare area */
47 #define MAIN_SINGLEBIT_ERROR 0x4
48 #define SPARE_SINGLEBIT_ERROR 0x1
50 /* OOB placement block for use with hardware ecc generation */
51 #if defined(MXC_NFC_V1)
52 #ifndef CONFIG_SYS_NAND_LARGEPAGE
53 static struct nand_ecclayout nand_hw_eccoob = {
55 .eccpos = {6, 7, 8, 9, 10},
56 .oobfree = { {0, 5}, {11, 5}, }
59 static struct nand_ecclayout nand_hw_eccoob2k = {
67 .oobfree = { {2, 4}, {11, 11}, {27, 11}, {43, 11}, {59, 5} },
70 #elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
71 #ifndef CONFIG_SYS_NAND_LARGEPAGE
72 static struct nand_ecclayout nand_hw_eccoob = {
74 .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
78 static struct nand_ecclayout nand_hw_eccoob2k = {
81 7, 8, 9, 10, 11, 12, 13, 14, 15,
82 23, 24, 25, 26, 27, 28, 29, 30, 31,
83 39, 40, 41, 42, 43, 44, 45, 46, 47,
84 55, 56, 57, 58, 59, 60, 61, 62, 63,
86 .oobfree = { {2, 5}, {16, 7}, {32, 7}, {48, 7} },
91 static int is_16bit_nand(void)
93 #if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT)
100 static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t size)
106 __raw_writel(__raw_readl(source++), d++);
111 * This function polls the NANDFC to wait for the basic operation to
112 * complete by checking the INT bit.
114 static void wait_op_done(struct mxc_nand_host *host, int max_retries,
119 while (max_retries-- > 0) {
120 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
121 tmp = readnfc(&host->regs->config2);
122 if (tmp & NFC_V1_V2_CONFIG2_INT) {
123 tmp &= ~NFC_V1_V2_CONFIG2_INT;
124 writenfc(tmp, &host->regs->config2);
125 #elif defined(MXC_NFC_V3_2)
126 tmp = readnfc(&host->ip_regs->ipc);
127 if (tmp & NFC_V3_IPC_INT) {
128 tmp &= ~NFC_V3_IPC_INT;
129 writenfc(tmp, &host->ip_regs->ipc);
135 if (max_retries < 0) {
136 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s(%d): INT not set\n",
142 * This function issues the specified command to the NAND device and
143 * waits for completion.
145 static void send_cmd(struct mxc_nand_host *host, uint16_t cmd)
147 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd);
149 writenfc(cmd, &host->regs->flash_cmd);
150 writenfc(NFC_CMD, &host->regs->operation);
152 /* Wait for operation to complete */
153 wait_op_done(host, TROP_US_DELAY, cmd);
157 * This function sends an address (or partial address) to the
158 * NAND device. The address is used to select the source/destination for
161 static void send_addr(struct mxc_nand_host *host, uint16_t addr)
163 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x)\n", addr);
165 writenfc(addr, &host->regs->flash_addr);
166 writenfc(NFC_ADDR, &host->regs->operation);
168 /* Wait for operation to complete */
169 wait_op_done(host, TROP_US_DELAY, addr);
173 * This function requests the NANDFC to initiate the transfer
174 * of data currently in the NANDFC RAM buffer to the NAND device.
176 static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
180 MTDDEBUG(MTD_DEBUG_LEVEL1, "send_prog_page (%d)\n", spare_only);
182 if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
185 * The controller copies the 64 bytes of spare data from
186 * the first 16 bytes of each of the 4 64 byte spare buffers.
187 * Copy the contiguous data starting in spare_area[0] to
188 * the four spare area buffers.
190 for (i = 1; i < 4; i++) {
191 void __iomem *src = &host->regs->spare_area[0][i * 16];
192 void __iomem *dst = &host->regs->spare_area[i][0];
194 mxc_nand_memcpy32(dst, src, 16);
198 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
199 writenfc(buf_id, &host->regs->buf_addr);
200 #elif defined(MXC_NFC_V3_2)
201 uint32_t tmp = readnfc(&host->regs->config1);
202 tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
203 tmp |= NFC_V3_CONFIG1_RBA(buf_id);
204 writenfc(tmp, &host->regs->config1);
207 /* Configure spare or page+spare access */
208 if (!host->pagesize_2k) {
209 uint32_t config1 = readnfc(&host->regs->config1);
211 config1 |= NFC_CONFIG1_SP_EN;
213 config1 &= ~NFC_CONFIG1_SP_EN;
214 writenfc(config1, &host->regs->config1);
217 writenfc(NFC_INPUT, &host->regs->operation);
219 /* Wait for operation to complete */
220 wait_op_done(host, TROP_US_DELAY, spare_only);
224 * Requests NANDFC to initiate the transfer of data from the
225 * NAND device into in the NANDFC ram buffer.
227 static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
230 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only);
232 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
233 writenfc(buf_id, &host->regs->buf_addr);
234 #elif defined(MXC_NFC_V3_2)
235 uint32_t tmp = readnfc(&host->regs->config1);
236 tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
237 tmp |= NFC_V3_CONFIG1_RBA(buf_id);
238 writenfc(tmp, &host->regs->config1);
241 /* Configure spare or page+spare access */
242 if (!host->pagesize_2k) {
243 uint32_t config1 = readnfc(&host->regs->config1);
245 config1 |= NFC_CONFIG1_SP_EN;
247 config1 &= ~NFC_CONFIG1_SP_EN;
248 writenfc(config1, &host->regs->config1);
251 writenfc(NFC_OUTPUT, &host->regs->operation);
253 /* Wait for operation to complete */
254 wait_op_done(host, TROP_US_DELAY, spare_only);
256 if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
260 * The controller copies the 64 bytes of spare data to
261 * the first 16 bytes of each of the 4 spare buffers.
262 * Make the data contiguous starting in spare_area[0].
264 for (i = 1; i < 4; i++) {
265 void __iomem *src = &host->regs->spare_area[i][0];
266 void __iomem *dst = &host->regs->spare_area[0][i * 16];
268 mxc_nand_memcpy32(dst, src, 16);
273 /* Request the NANDFC to perform a read of the NAND device ID. */
274 static void send_read_id(struct mxc_nand_host *host)
278 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
279 /* NANDFC buffer 0 is used for device ID output */
280 writenfc(0x0, &host->regs->buf_addr);
281 #elif defined(MXC_NFC_V3_2)
282 tmp = readnfc(&host->regs->config1);
283 tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
284 writenfc(tmp, &host->regs->config1);
287 /* Read ID into main buffer */
288 tmp = readnfc(&host->regs->config1);
289 tmp &= ~NFC_CONFIG1_SP_EN;
290 writenfc(tmp, &host->regs->config1);
292 writenfc(NFC_ID, &host->regs->operation);
294 /* Wait for operation to complete */
295 wait_op_done(host, TROP_US_DELAY, 0);
299 * This function requests the NANDFC to perform a read of the
300 * NAND device status and returns the current status.
302 static uint16_t get_dev_status(struct mxc_nand_host *host)
304 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
305 void __iomem *main_buf = host->regs->main_area[1];
309 /* Issue status request to NAND device */
311 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
312 /* store the main area1 first word, later do recovery */
313 store = readl(main_buf);
314 /* NANDFC buffer 1 is used for device status */
315 writenfc(1, &host->regs->buf_addr);
318 /* Read status into main buffer */
319 tmp = readnfc(&host->regs->config1);
320 tmp &= ~NFC_CONFIG1_SP_EN;
321 writenfc(tmp, &host->regs->config1);
323 writenfc(NFC_STATUS, &host->regs->operation);
325 /* Wait for operation to complete */
326 wait_op_done(host, TROP_US_DELAY, 0);
328 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
330 * Status is placed in first word of main buffer
331 * get status, then recovery area 1 data
333 ret = readw(main_buf);
334 writel(store, main_buf);
335 #elif defined(MXC_NFC_V3_2)
336 ret = readnfc(&host->regs->config1) >> 16;
342 /* This function is used by upper layer to checks if device is ready */
343 static int mxc_nand_dev_ready(struct mtd_info *mtd)
346 * NFC handles R/B internally. Therefore, this function
347 * always returns status as ready.
352 static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on)
354 struct nand_chip *nand_chip = mtd->priv;
355 struct mxc_nand_host *host = nand_chip->priv;
356 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
357 uint16_t tmp = readnfc(&host->regs->config1);
360 tmp |= NFC_V1_V2_CONFIG1_ECC_EN;
362 tmp &= ~NFC_V1_V2_CONFIG1_ECC_EN;
363 writenfc(tmp, &host->regs->config1);
364 #elif defined(MXC_NFC_V3_2)
365 uint32_t tmp = readnfc(&host->ip_regs->config2);
368 tmp |= NFC_V3_CONFIG2_ECC_EN;
370 tmp &= ~NFC_V3_CONFIG2_ECC_EN;
371 writenfc(tmp, &host->ip_regs->config2);
375 #ifdef CONFIG_MXC_NAND_HWECC
376 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
379 * If HW ECC is enabled, we turn it on during init. There is
380 * no need to enable again here.
384 #if defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
385 static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd,
386 struct nand_chip *chip,
389 struct mxc_nand_host *host = chip->priv;
390 uint8_t *buf = chip->oob_poi;
391 int length = mtd->oobsize;
392 int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
393 uint8_t *bufpoi = buf;
396 MTDDEBUG(MTD_DEBUG_LEVEL0,
397 "%s: Reading OOB area of page %u to oob %p\n",
398 __func__, page, buf);
400 chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
401 for (i = 0; i < chip->ecc.steps; i++) {
402 toread = min_t(int, length, chip->ecc.prepad);
404 chip->read_buf(mtd, bufpoi, toread);
408 bufpoi += chip->ecc.bytes;
409 host->col_addr += chip->ecc.bytes;
410 length -= chip->ecc.bytes;
412 toread = min_t(int, length, chip->ecc.postpad);
414 chip->read_buf(mtd, bufpoi, toread);
420 chip->read_buf(mtd, bufpoi, length);
422 _mxc_nand_enable_hwecc(mtd, 0);
423 chip->cmdfunc(mtd, NAND_CMD_READOOB,
424 mtd->writesize + chip->ecc.prepad, page);
425 bufpoi = buf + chip->ecc.prepad;
426 length = mtd->oobsize - chip->ecc.prepad;
427 for (i = 0; i < chip->ecc.steps; i++) {
428 toread = min_t(int, length, chip->ecc.bytes);
429 chip->read_buf(mtd, bufpoi, toread);
432 host->col_addr += chip->ecc.postpad + chip->ecc.prepad;
434 _mxc_nand_enable_hwecc(mtd, 1);
438 static int mxc_nand_read_page_raw_syndrome(struct mtd_info *mtd,
439 struct nand_chip *chip,
444 struct mxc_nand_host *host = chip->priv;
445 int eccsize = chip->ecc.size;
446 int eccbytes = chip->ecc.bytes;
447 int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
448 uint8_t *oob = chip->oob_poi;
452 _mxc_nand_enable_hwecc(mtd, 0);
453 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
455 for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
456 host->col_addr = n * eccsize;
457 chip->read_buf(mtd, buf, eccsize);
460 host->col_addr = mtd->writesize + n * eccpitch;
461 if (chip->ecc.prepad) {
462 chip->read_buf(mtd, oob, chip->ecc.prepad);
463 oob += chip->ecc.prepad;
466 chip->read_buf(mtd, oob, eccbytes);
469 if (chip->ecc.postpad) {
470 chip->read_buf(mtd, oob, chip->ecc.postpad);
471 oob += chip->ecc.postpad;
475 size = mtd->oobsize - (oob - chip->oob_poi);
477 chip->read_buf(mtd, oob, size);
478 _mxc_nand_enable_hwecc(mtd, 1);
483 static int mxc_nand_read_page_syndrome(struct mtd_info *mtd,
484 struct nand_chip *chip,
489 struct mxc_nand_host *host = chip->priv;
490 int n, eccsize = chip->ecc.size;
491 int eccbytes = chip->ecc.bytes;
492 int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
493 int eccsteps = chip->ecc.steps;
495 uint8_t *oob = chip->oob_poi;
497 MTDDEBUG(MTD_DEBUG_LEVEL1, "Reading page %u to buf %p oob %p\n",
500 /* first read the data area and the available portion of OOB */
501 for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
504 host->col_addr = n * eccsize;
506 chip->read_buf(mtd, p, eccsize);
508 host->col_addr = mtd->writesize + n * eccpitch;
510 if (chip->ecc.prepad) {
511 chip->read_buf(mtd, oob, chip->ecc.prepad);
512 oob += chip->ecc.prepad;
515 stat = chip->ecc.correct(mtd, p, oob, NULL);
518 mtd->ecc_stats.failed++;
520 mtd->ecc_stats.corrected += stat;
523 if (chip->ecc.postpad) {
524 chip->read_buf(mtd, oob, chip->ecc.postpad);
525 oob += chip->ecc.postpad;
529 /* Calculate remaining oob bytes */
530 n = mtd->oobsize - (oob - chip->oob_poi);
532 chip->read_buf(mtd, oob, n);
534 /* Then switch ECC off and read the OOB area to get the ECC code */
535 _mxc_nand_enable_hwecc(mtd, 0);
536 chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
537 eccsteps = chip->ecc.steps;
538 oob = chip->oob_poi + chip->ecc.prepad;
539 for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
540 host->col_addr = mtd->writesize +
543 chip->read_buf(mtd, oob, eccbytes);
544 oob += eccbytes + chip->ecc.postpad;
546 _mxc_nand_enable_hwecc(mtd, 1);
550 static int mxc_nand_write_oob_syndrome(struct mtd_info *mtd,
551 struct nand_chip *chip, int page)
553 struct mxc_nand_host *host = chip->priv;
554 int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
555 int length = mtd->oobsize;
556 int i, len, status, steps = chip->ecc.steps;
557 const uint8_t *bufpoi = chip->oob_poi;
559 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
560 for (i = 0; i < steps; i++) {
561 len = min_t(int, length, eccpitch);
563 chip->write_buf(mtd, bufpoi, len);
566 host->col_addr += chip->ecc.prepad + chip->ecc.postpad;
569 chip->write_buf(mtd, bufpoi, length);
571 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
572 status = chip->waitfunc(mtd, chip);
573 return status & NAND_STATUS_FAIL ? -EIO : 0;
576 static int mxc_nand_write_page_raw_syndrome(struct mtd_info *mtd,
577 struct nand_chip *chip,
581 struct mxc_nand_host *host = chip->priv;
582 int eccsize = chip->ecc.size;
583 int eccbytes = chip->ecc.bytes;
584 int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
585 uint8_t *oob = chip->oob_poi;
589 for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
590 host->col_addr = n * eccsize;
591 chip->write_buf(mtd, buf, eccsize);
594 host->col_addr = mtd->writesize + n * eccpitch;
596 if (chip->ecc.prepad) {
597 chip->write_buf(mtd, oob, chip->ecc.prepad);
598 oob += chip->ecc.prepad;
601 host->col_addr += eccbytes;
604 if (chip->ecc.postpad) {
605 chip->write_buf(mtd, oob, chip->ecc.postpad);
606 oob += chip->ecc.postpad;
610 size = mtd->oobsize - (oob - chip->oob_poi);
612 chip->write_buf(mtd, oob, size);
616 static int mxc_nand_write_page_syndrome(struct mtd_info *mtd,
617 struct nand_chip *chip,
621 struct mxc_nand_host *host = chip->priv;
622 int i, n, eccsize = chip->ecc.size;
623 int eccbytes = chip->ecc.bytes;
624 int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
625 int eccsteps = chip->ecc.steps;
626 const uint8_t *p = buf;
627 uint8_t *oob = chip->oob_poi;
629 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
633 n++, eccsteps--, i += eccbytes, p += eccsize) {
634 host->col_addr = n * eccsize;
636 chip->write_buf(mtd, p, eccsize);
638 host->col_addr = mtd->writesize + n * eccpitch;
640 if (chip->ecc.prepad) {
641 chip->write_buf(mtd, oob, chip->ecc.prepad);
642 oob += chip->ecc.prepad;
645 chip->write_buf(mtd, oob, eccbytes);
648 if (chip->ecc.postpad) {
649 chip->write_buf(mtd, oob, chip->ecc.postpad);
650 oob += chip->ecc.postpad;
654 /* Calculate remaining oob bytes */
655 i = mtd->oobsize - (oob - chip->oob_poi);
657 chip->write_buf(mtd, oob, i);
661 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
662 u_char *read_ecc, u_char *calc_ecc)
664 struct nand_chip *nand_chip = mtd->priv;
665 struct mxc_nand_host *host = nand_chip->priv;
666 uint32_t ecc_status = readl(&host->regs->ecc_status_result);
667 int subpages = mtd->writesize / nand_chip->subpagesize;
668 int pg2blk_shift = nand_chip->phys_erase_shift -
669 nand_chip->page_shift;
672 if ((ecc_status & 0xf) > 4) {
673 static int last_bad = -1;
675 if (last_bad != host->page_addr >> pg2blk_shift) {
676 last_bad = host->page_addr >> pg2blk_shift;
678 "MXC_NAND: HWECC uncorrectable ECC error"
679 " in block %u page %u subpage %d\n",
680 last_bad, host->page_addr,
681 mtd->writesize / nand_chip->subpagesize
688 } while (subpages > 0);
693 #define mxc_nand_read_page_syndrome NULL
694 #define mxc_nand_read_page_raw_syndrome NULL
695 #define mxc_nand_read_oob_syndrome NULL
696 #define mxc_nand_write_page_syndrome NULL
697 #define mxc_nand_write_page_raw_syndrome NULL
698 #define mxc_nand_write_oob_syndrome NULL
700 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
701 u_char *read_ecc, u_char *calc_ecc)
703 struct nand_chip *nand_chip = mtd->priv;
704 struct mxc_nand_host *host = nand_chip->priv;
707 * 1-Bit errors are automatically corrected in HW. No need for
708 * additional correction. 2-Bit errors cannot be corrected by
709 * HW ECC, so we need to return failure
711 uint16_t ecc_status = readnfc(&host->regs->ecc_status_result);
713 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
714 MTDDEBUG(MTD_DEBUG_LEVEL0,
715 "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
723 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
730 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
732 struct nand_chip *nand_chip = mtd->priv;
733 struct mxc_nand_host *host = nand_chip->priv;
736 uint16_t __iomem *main_buf =
737 (uint16_t __iomem *)host->regs->main_area[0];
738 uint16_t __iomem *spare_buf =
739 (uint16_t __iomem *)host->regs->spare_area[0];
745 /* Check for status request */
746 if (host->status_request)
747 return get_dev_status(host) & 0xFF;
749 /* Get column for 16-bit access */
750 col = host->col_addr >> 1;
752 /* If we are accessing the spare region */
753 if (host->spare_only)
754 nfc_word.word = readw(&spare_buf[col]);
756 nfc_word.word = readw(&main_buf[col]);
758 /* Pick upper/lower byte of word from RAM buffer */
759 ret = nfc_word.bytes[host->col_addr & 0x1];
761 /* Update saved column address */
762 if (nand_chip->options & NAND_BUSWIDTH_16)
770 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
772 struct nand_chip *nand_chip = mtd->priv;
773 struct mxc_nand_host *host = nand_chip->priv;
777 MTDDEBUG(MTD_DEBUG_LEVEL3,
778 "mxc_nand_read_word(col = %d)\n", host->col_addr);
780 col = host->col_addr;
781 /* Adjust saved column address */
782 if (col < mtd->writesize && host->spare_only)
783 col += mtd->writesize;
785 if (col < mtd->writesize) {
786 p = (uint16_t __iomem *)(host->regs->main_area[0] +
789 p = (uint16_t __iomem *)(host->regs->spare_area[0] +
790 ((col - mtd->writesize) >> 1));
799 nfc_word[0].word = readw(p);
800 nfc_word[1].word = readw(p + 1);
802 nfc_word[2].bytes[0] = nfc_word[0].bytes[1];
803 nfc_word[2].bytes[1] = nfc_word[1].bytes[0];
805 ret = nfc_word[2].word;
810 /* Update saved column address */
811 host->col_addr = col + 2;
817 * Write data of length len to buffer buf. The data to be
818 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
819 * Operation by the NFC, the data is written to NAND Flash
821 static void mxc_nand_write_buf(struct mtd_info *mtd,
822 const u_char *buf, int len)
824 struct nand_chip *nand_chip = mtd->priv;
825 struct mxc_nand_host *host = nand_chip->priv;
828 MTDDEBUG(MTD_DEBUG_LEVEL3,
829 "mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr,
832 col = host->col_addr;
834 /* Adjust saved column address */
835 if (col < mtd->writesize && host->spare_only)
836 col += mtd->writesize;
838 n = mtd->writesize + mtd->oobsize - col;
841 MTDDEBUG(MTD_DEBUG_LEVEL3,
842 "%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n);
847 if (col < mtd->writesize) {
848 p = host->regs->main_area[0] + (col & ~3);
850 p = host->regs->spare_area[0] -
851 mtd->writesize + (col & ~3);
854 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", __func__,
857 if (((col | (unsigned long)&buf[i]) & 3) || n < 4) {
863 nfc_word.word = readl(p);
864 nfc_word.bytes[col & 3] = buf[i++];
868 writel(nfc_word.word, p);
870 int m = mtd->writesize - col;
872 if (col >= mtd->writesize)
877 MTDDEBUG(MTD_DEBUG_LEVEL3,
878 "%s:%d: n = %d, m = %d, i = %d, col = %d\n",
879 __func__, __LINE__, n, m, i, col);
881 mxc_nand_memcpy32(p, (uint32_t *)&buf[i], m);
887 /* Update saved column address */
888 host->col_addr = col;
892 * Read the data buffer from the NAND Flash. To read the data from NAND
893 * Flash first the data output cycle is initiated by the NFC, which copies
894 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
896 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
898 struct nand_chip *nand_chip = mtd->priv;
899 struct mxc_nand_host *host = nand_chip->priv;
902 MTDDEBUG(MTD_DEBUG_LEVEL3,
903 "mxc_nand_read_buf(col = %d, len = %d)\n", host->col_addr, len);
905 col = host->col_addr;
907 /* Adjust saved column address */
908 if (col < mtd->writesize && host->spare_only)
909 col += mtd->writesize;
911 n = mtd->writesize + mtd->oobsize - col;
917 if (col < mtd->writesize) {
918 p = host->regs->main_area[0] + (col & ~3);
920 p = host->regs->spare_area[0] -
921 mtd->writesize + (col & ~3);
924 if (((col | (int)&buf[i]) & 3) || n < 4) {
930 nfc_word.word = readl(p);
931 buf[i++] = nfc_word.bytes[col & 3];
935 int m = mtd->writesize - col;
937 if (col >= mtd->writesize)
941 mxc_nand_memcpy32((uint32_t *)&buf[i], p, m);
948 /* Update saved column address */
949 host->col_addr = col;
953 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
955 * Used by the upper layer to verify the data in NAND Flash
956 * with the data in the buf.
958 static int mxc_nand_verify_buf(struct mtd_info *mtd,
959 const u_char *buf, int len)
965 bsize = min(len, 256);
966 mxc_nand_read_buf(mtd, tmp, bsize);
968 if (memcmp(buf, tmp, bsize))
981 * This function is used by upper layer for select and
982 * deselect of the NAND chip
984 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
986 struct nand_chip *nand_chip = mtd->priv;
987 struct mxc_nand_host *host = nand_chip->priv;
991 /* TODO: Disable the NFC clock */
996 /* TODO: Enable the NFC clock */
1007 * Used by the upper layer to write command to NAND Flash for
1008 * different operations to be carried out on NAND Flash
1010 void mxc_nand_command(struct mtd_info *mtd, unsigned command,
1011 int column, int page_addr)
1013 struct nand_chip *nand_chip = mtd->priv;
1014 struct mxc_nand_host *host = nand_chip->priv;
1016 MTDDEBUG(MTD_DEBUG_LEVEL3,
1017 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
1018 command, column, page_addr);
1020 /* Reset command state information */
1021 host->status_request = false;
1023 /* Command pre-processing step */
1026 case NAND_CMD_STATUS:
1028 host->status_request = true;
1031 case NAND_CMD_READ0:
1032 host->page_addr = page_addr;
1033 host->col_addr = column;
1034 host->spare_only = false;
1037 case NAND_CMD_READOOB:
1038 host->col_addr = column;
1039 host->spare_only = true;
1040 if (host->pagesize_2k)
1041 command = NAND_CMD_READ0; /* only READ0 is valid */
1044 case NAND_CMD_SEQIN:
1045 if (column >= mtd->writesize) {
1047 * before sending SEQIN command for partial write,
1048 * we need read one page out. FSL NFC does not support
1049 * partial write. It always sends out 512+ecc+512+ecc
1050 * for large page nand flash. But for small page nand
1051 * flash, it does support SPARE ONLY operation.
1053 if (host->pagesize_2k) {
1054 /* call ourself to read a page */
1055 mxc_nand_command(mtd, NAND_CMD_READ0, 0,
1059 host->col_addr = column - mtd->writesize;
1060 host->spare_only = true;
1062 /* Set program pointer to spare region */
1063 if (!host->pagesize_2k)
1064 send_cmd(host, NAND_CMD_READOOB);
1066 host->spare_only = false;
1067 host->col_addr = column;
1069 /* Set program pointer to page start */
1070 if (!host->pagesize_2k)
1071 send_cmd(host, NAND_CMD_READ0);
1075 case NAND_CMD_PAGEPROG:
1076 send_prog_page(host, 0, host->spare_only);
1078 if (host->pagesize_2k && is_mxc_nfc_1()) {
1079 /* data in 4 areas */
1080 send_prog_page(host, 1, host->spare_only);
1081 send_prog_page(host, 2, host->spare_only);
1082 send_prog_page(host, 3, host->spare_only);
1088 /* Write out the command to the device. */
1089 send_cmd(host, command);
1091 /* Write out column address, if necessary */
1094 * MXC NANDFC can only perform full page+spare or
1095 * spare-only read/write. When the upper layers perform
1096 * a read/write buffer operation, we will use the saved
1097 * column address to index into the full page.
1100 if (host->pagesize_2k)
1101 /* another col addr cycle for 2k page */
1105 /* Write out page address, if necessary */
1106 if (page_addr != -1) {
1107 u32 page_mask = nand_chip->pagemask;
1109 send_addr(host, page_addr & 0xFF);
1112 } while (page_mask);
1115 /* Command post-processing step */
1118 case NAND_CMD_RESET:
1121 case NAND_CMD_READOOB:
1122 case NAND_CMD_READ0:
1123 if (host->pagesize_2k) {
1124 /* send read confirm command */
1125 send_cmd(host, NAND_CMD_READSTART);
1126 /* read for each AREA */
1127 send_read_page(host, 0, host->spare_only);
1128 if (is_mxc_nfc_1()) {
1129 send_read_page(host, 1, host->spare_only);
1130 send_read_page(host, 2, host->spare_only);
1131 send_read_page(host, 3, host->spare_only);
1134 send_read_page(host, 0, host->spare_only);
1138 case NAND_CMD_READID:
1143 case NAND_CMD_PAGEPROG:
1146 case NAND_CMD_STATUS:
1149 case NAND_CMD_ERASE2:
1154 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1156 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
1157 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
1159 static struct nand_bbt_descr bbt_main_descr = {
1160 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
1161 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1166 .pattern = bbt_pattern,
1169 static struct nand_bbt_descr bbt_mirror_descr = {
1170 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
1171 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1176 .pattern = mirror_pattern,
1181 int board_nand_init(struct nand_chip *this)
1183 struct mtd_info *mtd;
1184 #if defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
1188 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1189 this->bbt_options |= NAND_BBT_USE_FLASH;
1190 this->bbt_td = &bbt_main_descr;
1191 this->bbt_md = &bbt_mirror_descr;
1194 /* structures must be linked */
1199 /* 5 us command delay time */
1200 this->chip_delay = 5;
1203 this->dev_ready = mxc_nand_dev_ready;
1204 this->cmdfunc = mxc_nand_command;
1205 this->select_chip = mxc_nand_select_chip;
1206 this->read_byte = mxc_nand_read_byte;
1207 this->read_word = mxc_nand_read_word;
1208 this->write_buf = mxc_nand_write_buf;
1209 this->read_buf = mxc_nand_read_buf;
1211 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
1212 this->verify_buf = mxc_nand_verify_buf;
1216 host->regs = (struct mxc_nand_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
1219 (struct mxc_nand_ip_regs __iomem *)CONFIG_MXC_NAND_IP_REGS_BASE;
1223 #ifdef CONFIG_MXC_NAND_HWECC
1224 this->ecc.calculate = mxc_nand_calculate_ecc;
1225 this->ecc.hwctl = mxc_nand_enable_hwecc;
1226 this->ecc.correct = mxc_nand_correct_data;
1227 if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
1228 this->ecc.mode = NAND_ECC_HW_SYNDROME;
1229 this->ecc.read_page = mxc_nand_read_page_syndrome;
1230 this->ecc.read_page_raw = mxc_nand_read_page_raw_syndrome;
1231 this->ecc.read_oob = mxc_nand_read_oob_syndrome;
1232 this->ecc.write_page = mxc_nand_write_page_syndrome;
1233 this->ecc.write_page_raw = mxc_nand_write_page_raw_syndrome;
1234 this->ecc.write_oob = mxc_nand_write_oob_syndrome;
1235 this->ecc.bytes = 9;
1236 this->ecc.prepad = 7;
1238 this->ecc.mode = NAND_ECC_HW;
1242 this->ecc.strength = 1;
1244 this->ecc.strength = 4;
1246 host->pagesize_2k = 0;
1248 this->ecc.size = 512;
1249 _mxc_nand_enable_hwecc(mtd, 1);
1251 this->ecc.layout = &nand_soft_eccoob;
1252 this->ecc.mode = NAND_ECC_SOFT;
1253 _mxc_nand_enable_hwecc(mtd, 0);
1256 this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1258 /* NAND bus width determines access functions used by upper layer */
1259 if (is_16bit_nand())
1260 this->options |= NAND_BUSWIDTH_16;
1262 #ifdef CONFIG_SYS_NAND_LARGEPAGE
1263 host->pagesize_2k = 1;
1264 this->ecc.layout = &nand_hw_eccoob2k;
1266 host->pagesize_2k = 0;
1267 this->ecc.layout = &nand_hw_eccoob;
1270 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
1272 tmp = readnfc(&host->regs->config1);
1273 tmp |= NFC_V2_CONFIG1_ONE_CYCLE;
1274 tmp |= NFC_V2_CONFIG1_ECC_MODE_4;
1275 writenfc(tmp, &host->regs->config1);
1276 if (host->pagesize_2k)
1277 writenfc(64/2, &host->regs->spare_area_size);
1279 writenfc(16/2, &host->regs->spare_area_size);
1284 * Unlock the internal RAM Buffer
1286 writenfc(0x2, &host->regs->config);
1288 /* Blocks to be unlocked */
1289 writenfc(0x0, &host->regs->unlockstart_blkaddr);
1290 /* Originally (Freescale LTIB 2.6.21) 0x4000 was written to the
1291 * unlockend_blkaddr, but the magic 0x4000 does not always work
1292 * when writing more than some 32 megabytes (on 2k page nands)
1293 * However 0xFFFF doesn't seem to have this kind
1294 * of limitation (tried it back and forth several times).
1295 * The linux kernel driver sets this to 0xFFFF for the v2 controller
1296 * only, but probably this was not tested there for v1.
1297 * The very same limitation seems to apply to this kernel driver.
1298 * This might be NAND chip specific and the i.MX31 datasheet is
1299 * extremely vague about the semantics of this register.
1301 writenfc(0xFFFF, &host->regs->unlockend_blkaddr);
1303 /* Unlock Block Command for given address range */
1304 writenfc(0x4, &host->regs->wrprot);
1305 #elif defined(MXC_NFC_V3_2)
1306 writenfc(NFC_V3_CONFIG1_RBA(0), &host->regs->config1);
1307 writenfc(NFC_V3_IPC_CREQ, &host->ip_regs->ipc);
1309 /* Unlock the internal RAM Buffer */
1310 writenfc(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
1311 &host->ip_regs->wrprot);
1313 /* Blocks to be unlocked */
1314 for (tmp = 0; tmp < CONFIG_SYS_NAND_MAX_CHIPS; tmp++)
1315 writenfc(0x0 | 0xFFFF << 16,
1316 &host->ip_regs->wrprot_unlock_blkaddr[tmp]);
1318 writenfc(0, &host->ip_regs->ipc);
1320 tmp = readnfc(&host->ip_regs->config2);
1321 tmp &= ~(NFC_V3_CONFIG2_SPAS_MASK | NFC_V3_CONFIG2_EDC_MASK |
1322 NFC_V3_CONFIG2_ECC_MODE_8 | NFC_V3_CONFIG2_PS_MASK);
1323 tmp |= NFC_V3_CONFIG2_ONE_CYCLE;
1325 if (host->pagesize_2k) {
1326 tmp |= NFC_V3_CONFIG2_SPAS(64/2);
1327 tmp |= NFC_V3_CONFIG2_PS_2048;
1329 tmp |= NFC_V3_CONFIG2_SPAS(16/2);
1330 tmp |= NFC_V3_CONFIG2_PS_512;
1333 writenfc(tmp, &host->ip_regs->config2);
1335 tmp = NFC_V3_CONFIG3_NUM_OF_DEVS(0) |
1336 NFC_V3_CONFIG3_NO_SDMA |
1337 NFC_V3_CONFIG3_RBB_MODE |
1338 NFC_V3_CONFIG3_SBB(6) | /* Reset default */
1339 NFC_V3_CONFIG3_ADD_OP(0);
1341 if (!(this->options & NAND_BUSWIDTH_16))
1342 tmp |= NFC_V3_CONFIG3_FW8;
1344 writenfc(tmp, &host->ip_regs->config3);
1346 writenfc(0, &host->ip_regs->delay_line);