2 * Copyright 2004-2007 Freescale Semiconductor, Inc.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 * Copyright 2009 Ilya Yanok, <yanok@emcraft.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
23 #include <linux/err.h>
25 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35)
26 #include <asm/arch/imx-regs.h>
30 #define DRIVER_NAME "mxc_nand"
32 typedef enum {false, true} bool;
34 struct mxc_nand_host {
36 struct nand_chip *nand;
38 struct fsl_nfc_regs __iomem *regs;
44 unsigned int page_addr;
47 static struct mxc_nand_host mxc_host;
48 static struct mxc_nand_host *host = &mxc_host;
50 /* Define delays in microsec for NAND device operations */
51 #define TROP_US_DELAY 2000
52 /* Macros to get byte and bit positions of ECC */
53 #define COLPOS(x) ((x) >> 3)
54 #define BITPOS(x) ((x) & 0xf)
56 /* Define single bit Error positions in Main & Spare area */
57 #define MAIN_SINGLEBIT_ERROR 0x4
58 #define SPARE_SINGLEBIT_ERROR 0x1
60 /* OOB placement block for use with hardware ecc generation */
61 #if defined(MXC_NFC_V1)
62 #ifndef CONFIG_SYS_NAND_LARGEPAGE
63 static struct nand_ecclayout nand_hw_eccoob = {
65 .eccpos = {6, 7, 8, 9, 10},
66 .oobfree = { {0, 5}, {11, 5}, }
69 static struct nand_ecclayout nand_hw_eccoob2k = {
77 .oobfree = { {2, 4}, {11, 11}, {27, 11}, {43, 11}, {59, 5} },
80 #elif defined(MXC_NFC_V2_1)
81 #ifndef CONFIG_SYS_NAND_LARGEPAGE
82 static struct nand_ecclayout nand_hw_eccoob = {
84 .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
88 static struct nand_ecclayout nand_hw_eccoob2k = {
91 7, 8, 9, 10, 11, 12, 13, 14, 15,
92 23, 24, 25, 26, 27, 28, 29, 30, 31,
93 39, 40, 41, 42, 43, 44, 45, 46, 47,
94 55, 56, 57, 58, 59, 60, 61, 62, 63,
96 .oobfree = { {2, 5}, {16, 7}, {32, 7}, {48, 7} },
102 static int is_16bit_nand(void)
104 struct system_control_regs *sc_regs =
105 (struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
107 if (readl(&sc_regs->fmcr) & NF_16BIT_SEL)
112 #elif defined(CONFIG_MX31)
113 static int is_16bit_nand(void)
115 struct clock_control_regs *sc_regs =
116 (struct clock_control_regs *)CCM_BASE;
118 if (readl(&sc_regs->rcsr) & CCM_RCSR_NF16B)
123 #elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
124 static int is_16bit_nand(void)
126 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
128 if (readl(&ccm->rcsr) & CCM_RCSR_NF_16BIT_SEL)
134 #warning "8/16 bit NAND autodetection not supported"
135 static int is_16bit_nand(void)
141 static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t size)
147 __raw_writel(__raw_readl(source++), d++);
152 * This function polls the NANDFC to wait for the basic operation to
153 * complete by checking the INT bit of config2 register.
155 static void wait_op_done(struct mxc_nand_host *host, int max_retries,
160 while (max_retries-- > 0) {
161 if (readw(&host->regs->config2) & NFC_INT) {
162 tmp = readw(&host->regs->config2);
164 writew(tmp, &host->regs->config2);
169 if (max_retries < 0) {
170 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s(%d): INT not set\n",
176 * This function issues the specified command to the NAND device and
177 * waits for completion.
179 static void send_cmd(struct mxc_nand_host *host, uint16_t cmd)
181 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd);
183 writew(cmd, &host->regs->flash_cmd);
184 writew(NFC_CMD, &host->regs->config2);
186 /* Wait for operation to complete */
187 wait_op_done(host, TROP_US_DELAY, cmd);
191 * This function sends an address (or partial address) to the
192 * NAND device. The address is used to select the source/destination for
195 static void send_addr(struct mxc_nand_host *host, uint16_t addr)
197 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x)\n", addr);
199 writew(addr, &host->regs->flash_addr);
200 writew(NFC_ADDR, &host->regs->config2);
202 /* Wait for operation to complete */
203 wait_op_done(host, TROP_US_DELAY, addr);
207 * This function requests the NANDFC to initiate the transfer
208 * of data currently in the NANDFC RAM buffer to the NAND device.
210 static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
214 MTDDEBUG(MTD_DEBUG_LEVEL1, "send_prog_page (%d)\n", spare_only);
216 if (is_mxc_nfc_21()) {
219 * The controller copies the 64 bytes of spare data from
220 * the first 16 bytes of each of the 4 64 byte spare buffers.
221 * Copy the contiguous data starting in spare_area[0] to
222 * the four spare area buffers.
224 for (i = 1; i < 4; i++) {
225 void __iomem *src = &host->regs->spare_area[0][i * 16];
226 void __iomem *dst = &host->regs->spare_area[i][0];
228 mxc_nand_memcpy32(dst, src, 16);
232 writew(buf_id, &host->regs->buf_addr);
234 /* Configure spare or page+spare access */
235 if (!host->pagesize_2k) {
236 uint16_t config1 = readw(&host->regs->config1);
238 config1 |= NFC_SP_EN;
240 config1 &= ~NFC_SP_EN;
241 writew(config1, &host->regs->config1);
244 writew(NFC_INPUT, &host->regs->config2);
246 /* Wait for operation to complete */
247 wait_op_done(host, TROP_US_DELAY, spare_only);
251 * Requests NANDFC to initiate the transfer of data from the
252 * NAND device into in the NANDFC ram buffer.
254 static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
257 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only);
259 writew(buf_id, &host->regs->buf_addr);
261 /* Configure spare or page+spare access */
262 if (!host->pagesize_2k) {
263 uint32_t config1 = readw(&host->regs->config1);
265 config1 |= NFC_SP_EN;
267 config1 &= ~NFC_SP_EN;
268 writew(config1, &host->regs->config1);
271 writew(NFC_OUTPUT, &host->regs->config2);
273 /* Wait for operation to complete */
274 wait_op_done(host, TROP_US_DELAY, spare_only);
276 if (is_mxc_nfc_21()) {
280 * The controller copies the 64 bytes of spare data to
281 * the first 16 bytes of each of the 4 spare buffers.
282 * Make the data contiguous starting in spare_area[0].
284 for (i = 1; i < 4; i++) {
285 void __iomem *src = &host->regs->spare_area[i][0];
286 void __iomem *dst = &host->regs->spare_area[0][i * 16];
288 mxc_nand_memcpy32(dst, src, 16);
293 /* Request the NANDFC to perform a read of the NAND device ID. */
294 static void send_read_id(struct mxc_nand_host *host)
298 /* NANDFC buffer 0 is used for device ID output */
299 writew(0x0, &host->regs->buf_addr);
301 /* Read ID into main buffer */
302 tmp = readw(&host->regs->config1);
304 writew(tmp, &host->regs->config1);
306 writew(NFC_ID, &host->regs->config2);
308 /* Wait for operation to complete */
309 wait_op_done(host, TROP_US_DELAY, 0);
313 * This function requests the NANDFC to perform a read of the
314 * NAND device status and returns the current status.
316 static uint16_t get_dev_status(struct mxc_nand_host *host)
318 void __iomem *main_buf = host->regs->main_area[1];
321 /* Issue status request to NAND device */
323 /* store the main area1 first word, later do recovery */
324 store = readl(main_buf);
325 /* NANDFC buffer 1 is used for device status */
326 writew(1, &host->regs->buf_addr);
328 /* Read status into main buffer */
329 tmp = readw(&host->regs->config1);
331 writew(tmp, &host->regs->config1);
333 writew(NFC_STATUS, &host->regs->config2);
335 /* Wait for operation to complete */
336 wait_op_done(host, TROP_US_DELAY, 0);
339 * Status is placed in first word of main buffer
340 * get status, then recovery area 1 data
342 ret = readw(main_buf);
343 writel(store, main_buf);
348 /* This function is used by upper layer to checks if device is ready */
349 static int mxc_nand_dev_ready(struct mtd_info *mtd)
352 * NFC handles R/B internally. Therefore, this function
353 * always returns status as ready.
358 static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on)
360 struct nand_chip *nand_chip = mtd->priv;
361 struct mxc_nand_host *host = nand_chip->priv;
362 uint16_t tmp = readw(&host->regs->config1);
368 writew(tmp, &host->regs->config1);
371 #ifdef CONFIG_MXC_NAND_HWECC
372 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
375 * If HW ECC is enabled, we turn it on during init. There is
376 * no need to enable again here.
381 static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd,
382 struct nand_chip *chip,
383 int page, int sndcmd)
385 struct mxc_nand_host *host = chip->priv;
386 uint8_t *buf = chip->oob_poi;
387 int length = mtd->oobsize;
388 int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
389 uint8_t *bufpoi = buf;
392 MTDDEBUG(MTD_DEBUG_LEVEL0,
393 "%s: Reading OOB area of page %u to oob %p\n",
394 __FUNCTION__, host->page_addr, buf);
396 chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
397 for (i = 0; i < chip->ecc.steps; i++) {
398 toread = min_t(int, length, chip->ecc.prepad);
400 chip->read_buf(mtd, bufpoi, toread);
404 bufpoi += chip->ecc.bytes;
405 host->col_addr += chip->ecc.bytes;
406 length -= chip->ecc.bytes;
408 toread = min_t(int, length, chip->ecc.postpad);
410 chip->read_buf(mtd, bufpoi, toread);
416 chip->read_buf(mtd, bufpoi, length);
418 _mxc_nand_enable_hwecc(mtd, 0);
419 chip->cmdfunc(mtd, NAND_CMD_READOOB,
420 mtd->writesize + chip->ecc.prepad, page);
421 bufpoi = buf + chip->ecc.prepad;
422 length = mtd->oobsize - chip->ecc.prepad;
423 for (i = 0; i < chip->ecc.steps; i++) {
424 toread = min_t(int, length, chip->ecc.bytes);
425 chip->read_buf(mtd, bufpoi, toread);
428 host->col_addr += chip->ecc.postpad + chip->ecc.prepad;
430 _mxc_nand_enable_hwecc(mtd, 1);
434 static int mxc_nand_read_page_raw_syndrome(struct mtd_info *mtd,
435 struct nand_chip *chip,
439 struct mxc_nand_host *host = chip->priv;
440 int eccsize = chip->ecc.size;
441 int eccbytes = chip->ecc.bytes;
442 int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
443 uint8_t *oob = chip->oob_poi;
447 _mxc_nand_enable_hwecc(mtd, 0);
448 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, host->page_addr);
450 for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
451 host->col_addr = n * eccsize;
452 chip->read_buf(mtd, buf, eccsize);
455 host->col_addr = mtd->writesize + n * eccpitch;
456 if (chip->ecc.prepad) {
457 chip->read_buf(mtd, oob, chip->ecc.prepad);
458 oob += chip->ecc.prepad;
461 chip->read_buf(mtd, oob, eccbytes);
464 if (chip->ecc.postpad) {
465 chip->read_buf(mtd, oob, chip->ecc.postpad);
466 oob += chip->ecc.postpad;
470 size = mtd->oobsize - (oob - chip->oob_poi);
472 chip->read_buf(mtd, oob, size);
473 _mxc_nand_enable_hwecc(mtd, 1);
478 static int mxc_nand_read_page_syndrome(struct mtd_info *mtd,
479 struct nand_chip *chip,
483 struct mxc_nand_host *host = chip->priv;
484 int n, eccsize = chip->ecc.size;
485 int eccbytes = chip->ecc.bytes;
486 int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
487 int eccsteps = chip->ecc.steps;
489 uint8_t *oob = chip->oob_poi;
491 MTDDEBUG(MTD_DEBUG_LEVEL1, "Reading page %u to buf %p oob %p\n",
492 host->page_addr, buf, oob);
494 /* first read the data area and the available portion of OOB */
495 for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
498 host->col_addr = n * eccsize;
500 chip->read_buf(mtd, p, eccsize);
502 host->col_addr = mtd->writesize + n * eccpitch;
504 if (chip->ecc.prepad) {
505 chip->read_buf(mtd, oob, chip->ecc.prepad);
506 oob += chip->ecc.prepad;
509 stat = chip->ecc.correct(mtd, p, oob, NULL);
512 mtd->ecc_stats.failed++;
514 mtd->ecc_stats.corrected += stat;
517 if (chip->ecc.postpad) {
518 chip->read_buf(mtd, oob, chip->ecc.postpad);
519 oob += chip->ecc.postpad;
523 /* Calculate remaining oob bytes */
524 n = mtd->oobsize - (oob - chip->oob_poi);
526 chip->read_buf(mtd, oob, n);
528 /* Then switch ECC off and read the OOB area to get the ECC code */
529 _mxc_nand_enable_hwecc(mtd, 0);
530 chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, host->page_addr);
531 eccsteps = chip->ecc.steps;
532 oob = chip->oob_poi + chip->ecc.prepad;
533 for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
534 host->col_addr = mtd->writesize +
537 chip->read_buf(mtd, oob, eccbytes);
538 oob += eccbytes + chip->ecc.postpad;
540 _mxc_nand_enable_hwecc(mtd, 1);
544 static int mxc_nand_write_oob_syndrome(struct mtd_info *mtd,
545 struct nand_chip *chip, int page)
547 struct mxc_nand_host *host = chip->priv;
548 int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
549 int length = mtd->oobsize;
550 int i, len, status, steps = chip->ecc.steps;
551 const uint8_t *bufpoi = chip->oob_poi;
553 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
554 for (i = 0; i < steps; i++) {
555 len = min_t(int, length, eccpitch);
557 chip->write_buf(mtd, bufpoi, len);
560 host->col_addr += chip->ecc.prepad + chip->ecc.postpad;
563 chip->write_buf(mtd, bufpoi, length);
565 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
566 status = chip->waitfunc(mtd, chip);
567 return status & NAND_STATUS_FAIL ? -EIO : 0;
570 static void mxc_nand_write_page_raw_syndrome(struct mtd_info *mtd,
571 struct nand_chip *chip,
574 struct mxc_nand_host *host = chip->priv;
575 int eccsize = chip->ecc.size;
576 int eccbytes = chip->ecc.bytes;
577 int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
578 uint8_t *oob = chip->oob_poi;
582 for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
583 host->col_addr = n * eccsize;
584 chip->write_buf(mtd, buf, eccsize);
587 host->col_addr = mtd->writesize + n * eccpitch;
589 if (chip->ecc.prepad) {
590 chip->write_buf(mtd, oob, chip->ecc.prepad);
591 oob += chip->ecc.prepad;
594 host->col_addr += eccbytes;
597 if (chip->ecc.postpad) {
598 chip->write_buf(mtd, oob, chip->ecc.postpad);
599 oob += chip->ecc.postpad;
603 size = mtd->oobsize - (oob - chip->oob_poi);
605 chip->write_buf(mtd, oob, size);
608 static void mxc_nand_write_page_syndrome(struct mtd_info *mtd,
609 struct nand_chip *chip,
612 struct mxc_nand_host *host = chip->priv;
613 int i, n, eccsize = chip->ecc.size;
614 int eccbytes = chip->ecc.bytes;
615 int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
616 int eccsteps = chip->ecc.steps;
617 const uint8_t *p = buf;
618 uint8_t *oob = chip->oob_poi;
620 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
624 n++, eccsteps--, i += eccbytes, p += eccsize) {
625 host->col_addr = n * eccsize;
627 chip->write_buf(mtd, p, eccsize);
629 host->col_addr = mtd->writesize + n * eccpitch;
631 if (chip->ecc.prepad) {
632 chip->write_buf(mtd, oob, chip->ecc.prepad);
633 oob += chip->ecc.prepad;
636 chip->write_buf(mtd, oob, eccbytes);
639 if (chip->ecc.postpad) {
640 chip->write_buf(mtd, oob, chip->ecc.postpad);
641 oob += chip->ecc.postpad;
645 /* Calculate remaining oob bytes */
646 i = mtd->oobsize - (oob - chip->oob_poi);
648 chip->write_buf(mtd, oob, i);
651 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
652 u_char *read_ecc, u_char *calc_ecc)
654 struct nand_chip *nand_chip = mtd->priv;
655 struct mxc_nand_host *host = nand_chip->priv;
656 uint32_t ecc_status = readl(&host->regs->ecc_status_result);
657 int subpages = mtd->writesize / nand_chip->subpagesize;
658 int pg2blk_shift = nand_chip->phys_erase_shift -
659 nand_chip->page_shift;
662 if ((ecc_status & 0xf) > 4) {
663 static int last_bad = -1;
665 if (last_bad != host->page_addr >> pg2blk_shift) {
666 last_bad = host->page_addr >> pg2blk_shift;
668 "MXC_NAND: HWECC uncorrectable ECC error"
669 " in block %u page %u subpage %d\n",
670 last_bad, host->page_addr,
671 mtd->writesize / nand_chip->subpagesize
678 } while (subpages > 0);
683 #define mxc_nand_read_page_syndrome NULL
684 #define mxc_nand_read_page_raw_syndrome NULL
685 #define mxc_nand_read_oob_syndrome NULL
686 #define mxc_nand_write_page_syndrome NULL
687 #define mxc_nand_write_page_raw_syndrome NULL
688 #define mxc_nand_write_oob_syndrome NULL
690 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
691 u_char *read_ecc, u_char *calc_ecc)
693 struct nand_chip *nand_chip = mtd->priv;
694 struct mxc_nand_host *host = nand_chip->priv;
697 * 1-Bit errors are automatically corrected in HW. No need for
698 * additional correction. 2-Bit errors cannot be corrected by
699 * HW ECC, so we need to return failure
701 uint16_t ecc_status = readw(&host->regs->ecc_status_result);
703 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
704 MTDDEBUG(MTD_DEBUG_LEVEL0,
705 "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
713 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
720 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
722 struct nand_chip *nand_chip = mtd->priv;
723 struct mxc_nand_host *host = nand_chip->priv;
726 uint16_t __iomem *main_buf =
727 (uint16_t __iomem *)host->regs->main_area[0];
728 uint16_t __iomem *spare_buf =
729 (uint16_t __iomem *)host->regs->spare_area[0];
735 /* Check for status request */
736 if (host->status_request)
737 return get_dev_status(host) & 0xFF;
739 /* Get column for 16-bit access */
740 col = host->col_addr >> 1;
742 /* If we are accessing the spare region */
743 if (host->spare_only)
744 nfc_word.word = readw(&spare_buf[col]);
746 nfc_word.word = readw(&main_buf[col]);
748 /* Pick upper/lower byte of word from RAM buffer */
749 ret = nfc_word.bytes[host->col_addr & 0x1];
751 /* Update saved column address */
752 if (nand_chip->options & NAND_BUSWIDTH_16)
760 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
762 struct nand_chip *nand_chip = mtd->priv;
763 struct mxc_nand_host *host = nand_chip->priv;
767 MTDDEBUG(MTD_DEBUG_LEVEL3,
768 "mxc_nand_read_word(col = %d)\n", host->col_addr);
770 col = host->col_addr;
771 /* Adjust saved column address */
772 if (col < mtd->writesize && host->spare_only)
773 col += mtd->writesize;
775 if (col < mtd->writesize) {
776 p = (uint16_t __iomem *)(host->regs->main_area[0] +
779 p = (uint16_t __iomem *)(host->regs->spare_area[0] +
780 ((col - mtd->writesize) >> 1));
789 nfc_word[0].word = readw(p);
790 nfc_word[1].word = readw(p + 1);
792 nfc_word[2].bytes[0] = nfc_word[0].bytes[1];
793 nfc_word[2].bytes[1] = nfc_word[1].bytes[0];
795 ret = nfc_word[2].word;
800 /* Update saved column address */
801 host->col_addr = col + 2;
807 * Write data of length len to buffer buf. The data to be
808 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
809 * Operation by the NFC, the data is written to NAND Flash
811 static void mxc_nand_write_buf(struct mtd_info *mtd,
812 const u_char *buf, int len)
814 struct nand_chip *nand_chip = mtd->priv;
815 struct mxc_nand_host *host = nand_chip->priv;
818 MTDDEBUG(MTD_DEBUG_LEVEL3,
819 "mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr,
822 col = host->col_addr;
824 /* Adjust saved column address */
825 if (col < mtd->writesize && host->spare_only)
826 col += mtd->writesize;
828 n = mtd->writesize + mtd->oobsize - col;
831 MTDDEBUG(MTD_DEBUG_LEVEL3,
832 "%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n);
837 if (col < mtd->writesize) {
838 p = host->regs->main_area[0] + (col & ~3);
840 p = host->regs->spare_area[0] -
841 mtd->writesize + (col & ~3);
844 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", __func__,
847 if (((col | (unsigned long)&buf[i]) & 3) || n < 4) {
853 nfc_word.word = readl(p);
854 nfc_word.bytes[col & 3] = buf[i++];
858 writel(nfc_word.word, p);
860 int m = mtd->writesize - col;
862 if (col >= mtd->writesize)
867 MTDDEBUG(MTD_DEBUG_LEVEL3,
868 "%s:%d: n = %d, m = %d, i = %d, col = %d\n",
869 __func__, __LINE__, n, m, i, col);
871 mxc_nand_memcpy32(p, (uint32_t *)&buf[i], m);
877 /* Update saved column address */
878 host->col_addr = col;
882 * Read the data buffer from the NAND Flash. To read the data from NAND
883 * Flash first the data output cycle is initiated by the NFC, which copies
884 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
886 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
888 struct nand_chip *nand_chip = mtd->priv;
889 struct mxc_nand_host *host = nand_chip->priv;
892 MTDDEBUG(MTD_DEBUG_LEVEL3,
893 "mxc_nand_read_buf(col = %d, len = %d)\n", host->col_addr, len);
895 col = host->col_addr;
897 /* Adjust saved column address */
898 if (col < mtd->writesize && host->spare_only)
899 col += mtd->writesize;
901 n = mtd->writesize + mtd->oobsize - col;
907 if (col < mtd->writesize) {
908 p = host->regs->main_area[0] + (col & ~3);
910 p = host->regs->spare_area[0] -
911 mtd->writesize + (col & ~3);
914 if (((col | (int)&buf[i]) & 3) || n < 4) {
920 nfc_word.word = readl(p);
921 buf[i++] = nfc_word.bytes[col & 3];
925 int m = mtd->writesize - col;
927 if (col >= mtd->writesize)
931 mxc_nand_memcpy32((uint32_t *)&buf[i], p, m);
938 /* Update saved column address */
939 host->col_addr = col;
943 * Used by the upper layer to verify the data in NAND Flash
944 * with the data in the buf.
946 static int mxc_nand_verify_buf(struct mtd_info *mtd,
947 const u_char *buf, int len)
953 bsize = min(len, 256);
954 mxc_nand_read_buf(mtd, tmp, bsize);
956 if (memcmp(buf, tmp, bsize))
967 * This function is used by upper layer for select and
968 * deselect of the NAND chip
970 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
972 struct nand_chip *nand_chip = mtd->priv;
973 struct mxc_nand_host *host = nand_chip->priv;
977 /* TODO: Disable the NFC clock */
982 /* TODO: Enable the NFC clock */
993 * Used by the upper layer to write command to NAND Flash for
994 * different operations to be carried out on NAND Flash
996 void mxc_nand_command(struct mtd_info *mtd, unsigned command,
997 int column, int page_addr)
999 struct nand_chip *nand_chip = mtd->priv;
1000 struct mxc_nand_host *host = nand_chip->priv;
1002 MTDDEBUG(MTD_DEBUG_LEVEL3,
1003 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
1004 command, column, page_addr);
1006 /* Reset command state information */
1007 host->status_request = false;
1009 /* Command pre-processing step */
1012 case NAND_CMD_STATUS:
1014 host->status_request = true;
1017 case NAND_CMD_READ0:
1018 host->page_addr = page_addr;
1019 host->col_addr = column;
1020 host->spare_only = false;
1023 case NAND_CMD_READOOB:
1024 host->col_addr = column;
1025 host->spare_only = true;
1026 if (host->pagesize_2k)
1027 command = NAND_CMD_READ0; /* only READ0 is valid */
1030 case NAND_CMD_SEQIN:
1031 if (column >= mtd->writesize) {
1033 * before sending SEQIN command for partial write,
1034 * we need read one page out. FSL NFC does not support
1035 * partial write. It always sends out 512+ecc+512+ecc
1036 * for large page nand flash. But for small page nand
1037 * flash, it does support SPARE ONLY operation.
1039 if (host->pagesize_2k) {
1040 /* call ourself to read a page */
1041 mxc_nand_command(mtd, NAND_CMD_READ0, 0,
1045 host->col_addr = column - mtd->writesize;
1046 host->spare_only = true;
1048 /* Set program pointer to spare region */
1049 if (!host->pagesize_2k)
1050 send_cmd(host, NAND_CMD_READOOB);
1052 host->spare_only = false;
1053 host->col_addr = column;
1055 /* Set program pointer to page start */
1056 if (!host->pagesize_2k)
1057 send_cmd(host, NAND_CMD_READ0);
1061 case NAND_CMD_PAGEPROG:
1062 send_prog_page(host, 0, host->spare_only);
1064 if (host->pagesize_2k && is_mxc_nfc_1()) {
1065 /* data in 4 areas */
1066 send_prog_page(host, 1, host->spare_only);
1067 send_prog_page(host, 2, host->spare_only);
1068 send_prog_page(host, 3, host->spare_only);
1074 /* Write out the command to the device. */
1075 send_cmd(host, command);
1077 /* Write out column address, if necessary */
1080 * MXC NANDFC can only perform full page+spare or
1081 * spare-only read/write. When the upper layers perform
1082 * a read/write buffer operation, we will use the saved
1083 * column address to index into the full page.
1086 if (host->pagesize_2k)
1087 /* another col addr cycle for 2k page */
1091 /* Write out page address, if necessary */
1092 if (page_addr != -1) {
1093 u32 page_mask = nand_chip->pagemask;
1095 send_addr(host, page_addr & 0xFF);
1098 } while (page_mask);
1101 /* Command post-processing step */
1104 case NAND_CMD_RESET:
1107 case NAND_CMD_READOOB:
1108 case NAND_CMD_READ0:
1109 if (host->pagesize_2k) {
1110 /* send read confirm command */
1111 send_cmd(host, NAND_CMD_READSTART);
1112 /* read for each AREA */
1113 send_read_page(host, 0, host->spare_only);
1114 if (is_mxc_nfc_1()) {
1115 send_read_page(host, 1, host->spare_only);
1116 send_read_page(host, 2, host->spare_only);
1117 send_read_page(host, 3, host->spare_only);
1120 send_read_page(host, 0, host->spare_only);
1124 case NAND_CMD_READID:
1129 case NAND_CMD_PAGEPROG:
1132 case NAND_CMD_STATUS:
1135 case NAND_CMD_ERASE2:
1140 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1142 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
1143 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
1145 static struct nand_bbt_descr bbt_main_descr = {
1146 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
1147 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1152 .pattern = bbt_pattern,
1155 static struct nand_bbt_descr bbt_mirror_descr = {
1156 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
1157 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1162 .pattern = mirror_pattern,
1167 int board_nand_init(struct nand_chip *this)
1169 struct mtd_info *mtd;
1174 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1175 this->options |= NAND_USE_FLASH_BBT;
1176 this->bbt_td = &bbt_main_descr;
1177 this->bbt_md = &bbt_mirror_descr;
1180 /* structures must be linked */
1185 /* 5 us command delay time */
1186 this->chip_delay = 5;
1189 this->dev_ready = mxc_nand_dev_ready;
1190 this->cmdfunc = mxc_nand_command;
1191 this->select_chip = mxc_nand_select_chip;
1192 this->read_byte = mxc_nand_read_byte;
1193 this->read_word = mxc_nand_read_word;
1194 this->write_buf = mxc_nand_write_buf;
1195 this->read_buf = mxc_nand_read_buf;
1196 this->verify_buf = mxc_nand_verify_buf;
1198 host->regs = (struct fsl_nfc_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
1201 #ifdef CONFIG_MXC_NAND_HWECC
1202 this->ecc.calculate = mxc_nand_calculate_ecc;
1203 this->ecc.hwctl = mxc_nand_enable_hwecc;
1204 this->ecc.correct = mxc_nand_correct_data;
1205 if (is_mxc_nfc_21()) {
1206 this->ecc.mode = NAND_ECC_HW_SYNDROME;
1207 this->ecc.read_page = mxc_nand_read_page_syndrome;
1208 this->ecc.read_page_raw = mxc_nand_read_page_raw_syndrome;
1209 this->ecc.read_oob = mxc_nand_read_oob_syndrome;
1210 this->ecc.write_page = mxc_nand_write_page_syndrome;
1211 this->ecc.write_page_raw = mxc_nand_write_page_raw_syndrome;
1212 this->ecc.write_oob = mxc_nand_write_oob_syndrome;
1213 this->ecc.bytes = 9;
1214 this->ecc.prepad = 7;
1216 this->ecc.mode = NAND_ECC_HW;
1219 host->pagesize_2k = 0;
1221 this->ecc.size = 512;
1222 _mxc_nand_enable_hwecc(mtd, 1);
1224 this->ecc.layout = &nand_soft_eccoob;
1225 this->ecc.mode = NAND_ECC_SOFT;
1226 _mxc_nand_enable_hwecc(mtd, 0);
1229 this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1231 /* NAND bus width determines access functions used by upper layer */
1232 if (is_16bit_nand())
1233 this->options |= NAND_BUSWIDTH_16;
1235 #ifdef CONFIG_SYS_NAND_LARGEPAGE
1236 host->pagesize_2k = 1;
1237 this->ecc.layout = &nand_hw_eccoob2k;
1239 host->pagesize_2k = 0;
1240 this->ecc.layout = &nand_hw_eccoob;
1244 tmp = readw(&host->regs->config1);
1245 tmp |= NFC_ONE_CYCLE;
1246 tmp |= NFC_4_8N_ECC;
1247 writew(tmp, &host->regs->config1);
1248 if (host->pagesize_2k)
1249 writew(64/2, &host->regs->spare_area_size);
1251 writew(16/2, &host->regs->spare_area_size);
1256 * Unlock the internal RAM Buffer
1258 writew(0x2, &host->regs->config);
1260 /* Blocks to be unlocked */
1261 writew(0x0, &host->regs->unlockstart_blkaddr);
1262 /* Originally (Freescale LTIB 2.6.21) 0x4000 was written to the
1263 * unlockend_blkaddr, but the magic 0x4000 does not always work
1264 * when writing more than some 32 megabytes (on 2k page nands)
1265 * However 0xFFFF doesn't seem to have this kind
1266 * of limitation (tried it back and forth several times).
1267 * The linux kernel driver sets this to 0xFFFF for the v2 controller
1268 * only, but probably this was not tested there for v1.
1269 * The very same limitation seems to apply to this kernel driver.
1270 * This might be NAND chip specific and the i.MX31 datasheet is
1271 * extremely vague about the semantics of this register.
1273 writew(0xFFFF, &host->regs->unlockend_blkaddr);
1275 /* Unlock Block Command for given address range */
1276 writew(0x4, &host->regs->wrprot);